IDT2309 3.3V ZERO DELAY CLOCK BUFFER
Part | Datasheet |
---|---|
![]() |
IDT2309-1HDC (pdf) |
Related Parts | Information |
---|---|
![]() |
IDT2309-1HPGI |
![]() |
IDT2309-1HPGI8 |
![]() |
IDT2309-1HPG8 |
![]() |
IDT2309-1HPG |
![]() |
IDT2309-1DC |
![]() |
IDT2309-1DC8 |
![]() |
IDT2309-1DCI |
![]() |
IDT2309-1HDCI8 |
![]() |
IDT2309-1HDCI |
![]() |
IDT2309-1HDC8 |
![]() |
IDT2309-1DCI8 |
PDF Datasheet Preview |
---|
IDT2309 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 3.3V ZERO DELAY CLOCK BUFFER IDT2309 FEATURES: • Phase-Lock Loop Clock Distribution • 10MHz to 133MHz operating frequency • Distributes one clock input to one bank of five and one bankd of four outputs • Separate output enable for each output bank • Output Skew < 250ps • Low jitter <200 ps cycle-to-cycle • IDT2309-1 for Standard Drive • IDT2309-1H for High Drive • No external RC network required • Operates at 3.3V VDD • Available in SOIC and TSSOP packages NOTE EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 DESCRIPTION: The IDT2309 is a high-speed phase-lock loop PLL clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is a 16-pin version of the IDT2305. The IDT2309 accepts one reference input, and drives two banks of four low skew clocks. The -1H version of this device operates at up to 133MHz frequency and has higher drive than the -1 device. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input clock, the IDT2309 enters power down, and the outputs are tri-stated. In this mode, the device will draw less than 25µA. The IDT2309 is characterized for both Industrial and Commercial operation. FUNCTIONAL BLOCK DIAGRAM Control Logic 16 CLKOUT CLKA1 CLKA2 CLKA3 15 CLKA4 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1 c 2002 Integrated Device Technology, Inc. CLKB1 7 CLKB2 CLKB3 CLKB4 AUGUST 2009 DSC 5175/7 IDT2309 3.3V ZERO DELAY CLOCK BUFFER PIN CONFIGURATION CLKA1 CLKA2 CLKB1 CLKB2 16 CLKOUT 15 CLKA4 14 CLKA3 CLKB4 CLKB3 SOIC/ TSSOP TOP VIEW ORDERING INFORMATION Device Type Package Process COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Blank I DC DCG PG PGG Commercial 0oC to +70oC Industrial -40oC to +85oC Small Outline SOIC - Green Thin Shrink Small Outline Package TSSOP - Green 2309-1 Zero Delay Clock Buffer 2309-1H High Drive Output *NOTE EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 IDT2309-1DC* IDT2309-1DCI* IDT2309-1HDC* IDT2309-1HDCG IDT2309-1HDCI* IDT2309-1HDCGI IDT2309-1HPG IDT2309-1HPGG IDT2309-1HPGI IDT2309-1HPGGI Ordering Code Package Type 16-Pin SOIC 16-Pin SOIC 16-Pin SOIC 16-Pin SOIC 16-Pin SOIC 16-Pin SOIC 16-Pin TSSOP 16-Pin TSSOP 16-Pin TSSOP 16-Pin TSSOP Commercial Industrial Commercial Industrial Commercial Industrial Operating Range CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support: |
More datasheets: IDT2309-1HPGI | IDT2309-1HPGI8 | IDT2309-1HPG8 | IDT2309-1HPG | IDT2309-1DC | IDT2309-1DC8 | IDT2309-1DCI | IDT2309-1HDCI8 | IDT2309-1HDCI | IDT2309-1HDC8 |
Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT2309-1HDC Datasheet file may be downloaded here without warranties.