IDT2308-2HDC8

IDT2308-2HDC8 Datasheet

IDT2308 3.3V ZERO DELAY CLOCK MULTIPLIER

Part	Datasheet
IDT2308-2HDC8	IDT2308-2HDC8 (pdf)

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PDF Datasheet Preview
IDT2308 3.3V ZERO DELAY CLOCK MULTIPLIER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 3.3V ZERO DELAY CLOCK MULTIPLIER IDT2308 FEATURES: • Phase-Lock Loop Clock Distribution for Applications ranging from 10MHz to 133MHz operating frequency • Distributes one clock input to two banks of four outputs • Separate output enable for each output bank • External feedback FBK pin is used to synchronize the outputs to the clock input • Output Skew <200 ps • Low jitter <200 ps cycle-to-cycle • 1x, 2x, 4x output options see table : IDT2308-1 1x IDT2308-2 1x, 2x IDT2308-3 2x, 4x IDT2308-4 2x IDT2308-1H, -2H, and -5H for High Drive • No external RC network required • Operates at 3.3V VDD • Available in SOIC and TSSOP packages NOTE EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 DESCRIPTION: The IDT2308 is a high-speed phase-lock loop PLL clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2308 has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the input clock directly drives the outputs for system testing purposes. In the absence of an input clock, the IDT2308 enters power down, and the outputs are tri-stated. In this mode, the device will draw less than 25µA. The IDT2308 is available in six unique configurations for both prescaling and multiplication of the Input REF Clock. See available options table. The PLL is closed externally to provide more flexibility by allowing the user to control the delay between the input clock and the outputs. The IDT2308 is characterized for both Industrial and Commercial operation. FUNCTIONAL BLOCK DIAGRAM -3, -4 2 CLKA1 3 CLKA2 14 CLKA3 15 CLKA4 S2 8 S1 9 Control Logic -2, -3 2 6 CLKB1 7 CLKB2 10 CLKB3 11 CLKB4 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1 c 2006 Integrated Device Technology, Inc. AUGUST 2009 DSC 5173/12 IDT2308 3.3V ZERO DELAY CLOCK MULTIPLIER PIN CONFIGURATION CLKA1 CLKA2 CLKB1 CLKB2 CLKA4 ORDERING INFORMATION Device Type Package Process COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Blank I Commercial 0oC to +70oC Industrial -40oC to +85oC DC DCG PG PGG Small Outline SOIC - Green Thin Shrink Small Outline Package TSSOP - Green 2308-1 2308-2 2308-3 Zero Delay Clock Buffer With Standard Drive 2308-4 2308-1H 2308-2H Zero Delay Clock Buffer with High Drive 2308-5H NOTE EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 Ordering Code Package Type IDT2308-1DC 16-Pin SOIC IDT2308-1DCI* 16-Pin SOIC IDT2308-1HDC* 16-Pin SOIC IDT2308-1HDCG 16-Pin SOIC IDT2308-1HDCI* 16-Pin SOIC IDT2308-1HPG 16-Pin TSSOP IDT2308-1HPGI 16-Pin TSSOP IDT2308-2DC* 16-Pin SOIC IDT2308-2DCG 16-Pin SOIC IDT2308-2DCI* 16-Pin SOIC IDT2308-2DCGI 16-Pin SOIC IDT2308-2HDC* 16-Pin SOIC IDT2308-2HDCI* 16-Pin SOIC IDT2308-3DC* 16-Pin SOIC IDT2308-3DCI* 16-Pin SOIC IDT2308-4DC* 16-Pin SOIC IDT2308-4DCI* 16-Pin SOIC IDT2308-5HDC* 16-Pin SOIC IDT2308-5HDCI* 16-Pin SOIC IDT2308-5HPG

PDF Datasheet Preview

IDT2308 3.3V ZERO DELAY CLOCK MULTIPLIER

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V ZERO DELAY CLOCK MULTIPLIER

IDT2308

FEATURES:
• Phase-Lock Loop Clock Distribution for Applications ranging from 10MHz to 133MHz operating frequency
• Distributes one clock input to two banks of four outputs
• Separate output enable for each output bank
• External feedback FBK pin is used to synchronize the outputs
to the clock input
• Output Skew <200 ps
• Low jitter <200 ps cycle-to-cycle
• 1x, 2x, 4x output options see table :

IDT2308-1 1x IDT2308-2 1x, 2x IDT2308-3 2x, 4x IDT2308-4 2x IDT2308-1H, -2H, and -5H for High Drive
• No external RC network required
• Operates at 3.3V VDD
• Available in SOIC and TSSOP packages

NOTE EOL for non-green parts to occur on 5/13/10 per PDN U-09-01

DESCRIPTION:

The IDT2308 is a high-speed phase-lock loop PLL clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz.

The IDT2308 has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the input clock directly drives the outputs for system testing purposes. In the absence of an input clock, the IDT2308 enters power down, and the outputs are tri-stated. In this mode, the device will draw less than 25µA.

The IDT2308 is available in six unique configurations for both prescaling and multiplication of the Input REF Clock. See available options table.

The PLL is closed externally to provide more flexibility by allowing the user to control the delay between the input clock and the outputs.

The IDT2308 is characterized for both Industrial and Commercial operation.

FUNCTIONAL BLOCK DIAGRAM
-3, -4
2 CLKA1
3 CLKA2
14 CLKA3
15 CLKA4

S2 8 S1 9

Control Logic
-2, -3 2
6 CLKB1
7 CLKB2
10 CLKB3
11 CLKB4

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1
c 2006 Integrated Device Technology, Inc.

AUGUST 2009

DSC 5173/12

IDT2308 3.3V ZERO DELAY CLOCK MULTIPLIER

PIN CONFIGURATION

CLKA1

CLKA2

CLKB1

CLKB2

CLKA4
ORDERING INFORMATION

Device Type Package Process

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

Blank I

Commercial 0oC to +70oC Industrial -40oC to +85oC

DC DCG PG PGG

Small Outline SOIC - Green Thin Shrink Small Outline Package TSSOP - Green
2308-1
2308-2
2308-3

Zero Delay Clock Buffer With Standard Drive
2308-4
2308-1H
2308-2H Zero Delay Clock Buffer with High Drive
2308-5H
*NOTE EOL for non-green parts to occur on 5/13/10 per PDN U-09-01
Ordering Code

Package Type

IDT2308-1DC*
16-Pin SOIC

IDT2308-1DCI*
16-Pin SOIC

IDT2308-1HDC*
16-Pin SOIC

IDT2308-1HDCG
16-Pin SOIC

IDT2308-1HDCI*
16-Pin SOIC

IDT2308-1HPG
16-Pin TSSOP

IDT2308-1HPGI
16-Pin TSSOP

IDT2308-2DC*
16-Pin SOIC

IDT2308-2DCG
16-Pin SOIC

IDT2308-2DCI*
16-Pin SOIC

IDT2308-2DCGI
16-Pin SOIC

IDT2308-2HDC*
16-Pin SOIC

IDT2308-2HDCI*
16-Pin SOIC

IDT2308-3DC*
16-Pin SOIC

IDT2308-3DCI*
16-Pin SOIC

IDT2308-4DC*
16-Pin SOIC

IDT2308-4DCI*
16-Pin SOIC

IDT2308-5HDC*
16-Pin SOIC

IDT2308-5HDCI*
16-Pin SOIC

IDT2308-5HPG

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT2308-2HDC8 Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT2308-2HDC8 637246