ICS9248AG-92LFT

ICS9248AG-92LFT Datasheet

ICS9248-92

Part	Datasheet
ICS9248AG-92LFT	ICS9248AG-92LFT (pdf)

Related Parts	Information
ICS9248AG-92LF	ICS9248AG-92LF

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Integrated Circuit Systems, Inc. ICS9248-92 Mobile Pentium System Clock Chip Recommended Application The ICS9248-92 is a fully compliant timing solution for the Intel mobile 440BX/MX chipset requirements. General Description Features include two strong CPU, seven PCI and eight SDRAM clocks. Three reference outputs are available equal to the crystal frequency. Stronger drive CPUCLK outputs typically provide greater than 1 V/ns slew rate into 20pF loads. This device meets rise and fall requirements with 2 loads per CPU output ie, one clock to CPU and NB chipset, one clock to two L2 cache inputs . PWR_DWN# pin allows low power mode by stopping crystal OSC and PLL stages. For optional power management, CPU_STOP# can stop CPU 0:1 clocks and PCI_STOP# will stop PCICLK 0:5 clocks PCICLK outputs typically provide better than 1V/ns slew rate into 30pF loads while maintaining 50±5% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates. The ICS9248-92 accepts a 14.318MHz reference crystal or clock as its input and runs on a 3.3V core supply. • Generates system clocks for CPU, SDRAM, PCI, plus MHz REF 0:2 , USB, Plus Super I/O • I2C serial configuration interface provides output clock disabling and other functions • MODE input pin selects optional power management input control pins • Two fixed outputs separately selectable as 24 or 48MHz • 2.5V outputs CPU • 3.3V outputs SDRAM, PCI, REF, 48/24 MHz • No power supply sequence requirements • Uses external 14.318MHz crystal • 48 pin 240 mil TSSOP package • Output enable register for serial port control: 1 = enable 0 = disable Block Diagram Pin Configuration 48-Pin TSSOP 240 mil Package Functionality Crystal X1, X2 = MHz SEL 100/66# CPUCLK MHz PCICLK MHz ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. Pin Descriptions PIN NUMBER 45, 1, 2 3, 10, 17, 24, 31, 37, 43 4 5 6 7, 15 8 9, 11, 12, 13, 14, 16 18 19 20 21 22 23 25 28, 34 40 Ordering Information ICS9248yG-92 Example: ICS XXXX y G - PPP Pattern Number 2 or 3 digit number for parts with ROM code patterns Package Type G=TSSOP Device Type consists of 3 or 4 digit numbers Prefix ICS, AV = Standard Device ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

PDF Datasheet Preview

Integrated Circuit Systems, Inc.

ICS9248-92

Mobile

Pentium

System

Clock

Chip

Recommended Application The ICS9248-92 is a fully compliant timing solution for the Intel mobile 440BX/MX chipset requirements.

General Description Features include two strong CPU, seven PCI and eight SDRAM clocks. Three reference outputs are available equal to the crystal frequency. Stronger drive CPUCLK outputs typically provide greater than 1 V/ns slew rate into 20pF loads. This device meets rise and fall requirements with 2 loads per CPU output ie, one clock to CPU and NB chipset, one clock to two L2 cache inputs .

PWR_DWN# pin allows low power mode by stopping crystal OSC and PLL stages. For optional power management, CPU_STOP# can stop CPU 0:1 clocks and PCI_STOP# will stop PCICLK 0:5 clocks

PCICLK outputs typically provide better than 1V/ns slew rate into 30pF loads while maintaining 50±5% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates.

The ICS9248-92 accepts a 14.318MHz reference crystal or clock as its input and runs on a 3.3V core supply.
• Generates system clocks for CPU, SDRAM, PCI, plus

MHz REF 0:2 , USB, Plus Super I/O
• I2C serial configuration interface provides output clock
disabling and other functions
• MODE input pin selects optional power management
input control pins
• Two fixed outputs separately selectable as 24 or 48MHz
• 2.5V outputs CPU
• 3.3V outputs SDRAM, PCI, REF, 48/24 MHz
• No power supply sequence requirements
• Uses external 14.318MHz crystal
• 48 pin 240 mil TSSOP package
• Output enable register
for serial port control:
1 = enable
0 = disable

Block Diagram

Pin Configuration
48-Pin TSSOP 240 mil Package

Functionality

Crystal X1, X2 = MHz

SEL 100/66#

CPUCLK MHz

PCICLK MHz

ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

Pin Descriptions

PIN NUMBER 45, 1, 2
3, 10, 17, 24, 31, 37, 43 4 5 6 7, 15 8
9, 11, 12, 13, 14, 16 18 19 20 21 22 23 25
28, 34 40
Ordering Information

ICS9248yG-92

Example:

ICS XXXX y G - PPP

Pattern Number 2 or 3 digit number for parts with ROM code patterns

Package Type G=TSSOP

Device Type consists of 3 or 4 digit numbers

Prefix ICS, AV = Standard Device

ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived ICS9248AG-92LFT Datasheet file may be downloaded here without warranties.

Datasheet ID: ICS9248AG-92LFT 637215