ICS8442AYILF

ICS8442AYILF Datasheet

ICS8442I

Part	Datasheet
ICS8442AYILF	ICS8442AYILF (pdf)

Related Parts	Information
ICS8442AYILFT	ICS8442AYILFT

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ICS8442I 700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER The ICS8442I is a general purpose, dual output Crystalto-Differential LVDS High Frequency Synthesizer. The ICS8442I has a selectable TEST_CLK or crystal input. The TEST_CLK input accepts LVCMOS or LVTTL input levels and translates them to LVDS levels. The VCO operates at a frequency range of 250MHz to 700MHz.The VCO frequency is programmed in steps equal to the value of the input reference or crystal frequency. The VCO and output frequency can be programmed using the serial or parallelinterface to the configuration logic. The low phase noisecharacteristics of the ICS8442I makes it an ideal clock source for Gigabit Ethernet and Sonet applications. • Dual differential LVDS outputs • Selectable crystal oscillator interface or LVCMOS/LVTTL TEST_CLK • Output frequency range 31.25MHz to 700MHz • Crystal input frequency range 10MHz to 25MHz • VCO range 250MHz to 700MHz • Parallel or serial interface for programming counter and output dividers • RMS period jitter 3.5ps typical • Cycle-to-cycle jitter 18ps typical • 3.3V supply voltage • -40°C to 85°C ambient operating temperature BLOCK DIAGRAM VCO_SEL XTAL_SEL TEST_CLK XTAL_IN XTAL_OUT 0 OSC 1 S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 N0:N1 PHASE DETECTOR ÷8 1 CONFIGURATION INTERFACE LOGIC PIN ASSIGNMENT XTAL_IN nP_LOAD VCO_SEL M0 M1 M2 M3 M4 FOUT0 nFOUT0 FOUT1 nFOUT1 M5 M6 M7 M8 N0 N1 nc GND 32 31 30 29 28 27 26 25 ICS8442I 21 9 10 11 12 13 14 15 16 XTAL_OUT TEST_CLK XTAL_SEL VDDA S_LOAD S_DATA S_CLOCK MR GND nFOUT0 FOUT0 VDD nFOUT1 FOUT1 VDD TEST TEST 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View 8442AYI ICS8442I 700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER FUNCTIONAL DESCRIPTION NOTE The functional description that follows describes operation using a 25MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE The ICS8442I features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A fundamental crystal is used as the input to the onchip oscillator. The output of the oscillator is fed into the phase detector. A 25MHz crystal provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of 250MHz to 700MHz. The output of the M divider is also applied to the phase detector. The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M either too high or too low , the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVDS output buffers. The divider provides a 50% output duty cycle. The programmable features of the ICS8442I support two input modes to program the M divider and N output divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to set the M divider and N output divider to a spe- cific default state that will automatically occur during powerup. The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fVCO = fxtal x M The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 25MHz reference are defined as 10 M The frequency out is defined as follows: FOUT = fVCO = fxtal x M TABLE ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS8442AYI ICS8442AYI 32 Lead LQFP tray -40°C to 85°C ICS8442AYIT ICS8442AYI 32 Lead LQFP 1000 tape & reel -40°C to 85°C ICS8442AYILF 32 Lead "Lead-Free" LQFP tray -40°C to 85°C ICS8442AYILFT 32 Lead "Lead-Free" LQFP 1000 tape & reel -40°C to 85°C NOTE Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. IDT assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. 8442AYI ICS8442I 700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER Page 6 9 10 14 14 16 Description of Change Input Frequency Characteristics Table - corrected minimum values from 14MHz to 10MHz and corrected within the note. Crystal Characteristics - corrected minimum frequency from 14MHz to 10MHz. AC Characteristics Table - added Note Added Application Note, "Differential Duty Cycle Improvement". Changed XTAL1/2 naming convention to XTAL_IN/_OUT throughout the datasheet. Pin Assignment, corrected pin 24 to read XTAL_OUT from XTAL1 and pin 25 to XTAL_IN from XTAL2. Updated Figure 1, Parallel & Serial Load Operations diagram. Crystal Characteristics Table - added Drive Level AC Characteristics Table - changed test conditions for Cycle-to-Cycle Jitter from = 350MHz to N = 1, 2 and 350MHz to N = Corrected Crystal Input Interface diagram. Updated Schematic Layout diagram. Add Lead-Free note to Ordering Information Table. Updated datasheet's header/footer with IDT from ICS. Removed ICS prefix from Part/Order Number column. Added Contact Page. Date 9/17/04 12/16/04 5/10/05 7/16/10 8442AYI ICS8442I 700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 Sales 800-345-7015 inside USA +408-284-8200 outside USA Fax 408-284-2775 Tech Support 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 8442AYI

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ICS8442I
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER

The ICS8442I is a general purpose, dual output Crystalto-Differential LVDS High Frequency Synthesizer. The ICS8442I has a selectable TEST_CLK or crystal input. The TEST_CLK input accepts LVCMOS or LVTTL input levels and translates them to LVDS levels. The VCO operates at a frequency range of 250MHz to 700MHz.The VCO frequency is programmed in steps equal to the value of the input reference or crystal frequency. The VCO and output frequency can be programmed using the serial or parallelinterface to the configuration logic. The low phase noisecharacteristics of the ICS8442I makes it an ideal clock source for Gigabit Ethernet and Sonet applications.
• Dual differential LVDS outputs
• Selectable crystal oscillator interface or

LVCMOS/LVTTL TEST_CLK
• Output frequency range 31.25MHz to 700MHz
• Crystal input frequency range 10MHz to 25MHz
• VCO range 250MHz to 700MHz
• Parallel or serial interface for programming counter
and output dividers
• RMS period jitter 3.5ps typical
• Cycle-to-cycle jitter 18ps typical
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature

BLOCK DIAGRAM

VCO_SEL XTAL_SEL TEST_CLK

XTAL_IN

XTAL_OUT
0 OSC 1

S_LOAD S_DATA S_CLOCK nP_LOAD

M0:M8 N0:N1

PHASE DETECTOR
÷8 1

CONFIGURATION INTERFACE LOGIC

PIN ASSIGNMENT

XTAL_IN nP_LOAD VCO_SEL

M0 M1 M2 M3 M4

FOUT0 nFOUT0 FOUT1 nFOUT1

M5 M6 M7 M8 N0 N1 nc GND
32 31 30 29 28 27 26 25

ICS8442I 21
9 10 11 12 13 14 15 16

XTAL_OUT TEST_CLK XTAL_SEL VDDA S_LOAD S_DATA S_CLOCK MR

GND nFOUT0 FOUT0 VDD nFOUT1 FOUT1 VDD TEST

TEST
32-Lead LQFP 7mm x 7mm x 1.4mm package body

Y Package Top View
8442AYI

ICS8442I
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER

FUNCTIONAL DESCRIPTION

NOTE The functional description that follows describes operation using a 25MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE

The ICS8442I features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A fundamental crystal is used as the input to the onchip oscillator. The output of the oscillator is fed into the phase detector. A 25MHz crystal provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of 250MHz to 700MHz. The output of the M divider is also applied to the phase detector.

The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M either too high or too low , the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVDS output buffers. The divider provides a 50% output duty cycle.

The programmable features of the ICS8442I support two input modes to program the M divider and N output divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to set the M divider and N output divider to a spe-
cific default state that will automatically occur during powerup. The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows:
fVCO = fxtal x M

The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 25MHz reference are defined as 10 M The frequency out is defined as follows:

FOUT = fVCO = fxtal x M
TABLE ORDERING INFORMATION

Part/Order Number

Marking

Package

Shipping Packaging Temperature

ICS8442AYI

ICS8442AYI
32 Lead LQFP
tray
-40°C to 85°C

ICS8442AYIT

ICS8442AYI
32 Lead LQFP
1000 tape & reel -40°C to 85°C

ICS8442AYILF
32 Lead "Lead-Free" LQFP
tray
-40°C to 85°C

ICS8442AYILFT
32 Lead "Lead-Free" LQFP
1000 tape & reel -40°C to 85°C

NOTE Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. IDT assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
8442AYI

ICS8442I
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER

Page 6
9 10 14
14 16
Description of Change Input Frequency Characteristics Table - corrected minimum values from 14MHz to 10MHz and corrected within the note. Crystal Characteristics - corrected minimum frequency from 14MHz to 10MHz. AC Characteristics Table - added Note Added Application Note, "Differential Duty Cycle Improvement". Changed XTAL1/2 naming convention to XTAL_IN/_OUT throughout the datasheet. Pin Assignment, corrected pin 24 to read XTAL_OUT from XTAL1 and pin 25 to XTAL_IN from XTAL2. Updated Figure 1, Parallel & Serial Load Operations diagram. Crystal Characteristics Table - added Drive Level AC Characteristics Table - changed test conditions for Cycle-to-Cycle Jitter from = 350MHz to N = 1, 2 and 350MHz to N = Corrected Crystal Input Interface diagram. Updated Schematic Layout diagram. Add Lead-Free note to Ordering Information Table. Updated datasheet's header/footer with IDT from ICS. Removed ICS prefix from Part/Order Number column. Added Contact Page.

Date 9/17/04 12/16/04
5/10/05
7/16/10
8442AYI

ICS8442I
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER

We’ve Got Your Timing Solution.
6024 Silver Creek Valley Road San Jose, CA 95138

Sales 800-345-7015 inside USA +408-284-8200 outside USA Fax 408-284-2775

Tech Support
2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA
8442AYI

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Datasheet ID: ICS8442AYILF 637135