ICS554G-01AIT

ICS554G-01AIT Datasheet

ICS554-01A

Part	Datasheet
ICS554G-01AIT	ICS554G-01AIT (pdf)

Related Parts	Information
ICS554G-01AILF	ICS554G-01AILF
ICS554G-01AI	ICS554G-01AI

PDF Datasheet Preview
LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT DATASHEET ICS554-01A The ICS554-01A is a low skew clock buffer with a single complimentary PECL input to four PECL outputs. Part of IDT’s Clock BlocksTM family, this is our lowest skew PECL clock buffer. The ICS554-01A is footprint compatible with the ICS554-01, but requires fewer passive components for termination thus providing a cost-saving alternative. For parts which do not require PECL inputs or outputs, see the ICS553 for a 1 to 4 low skew buffer, or the ICS552-02 for a 1 to 8 low skew buffer. For more than 8 outputs see the MK74CBxxx BuffaloTM series of clock drivers. IDT makes many non-PLL and PLL based low skew output devices as well as Zero Delay Buffers to synchronize clocks. Contact us for all of your clocking needs. • Input frequency up to 200 MHz • Advanced CMOS process • Outputs are skew matched to within 50 ps • Packaged in 16-pin TSSOP • One PECL input to 4 PECL output clock drivers • Operating Voltages of V or 5 V • Industrial temperature range • Functional equivalent to ICS554-01 • Simplified passive termination network compared to ICS554-01 NOTE EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 Block Diagram IDT / ICS LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT 1 ICS554-01A LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT Pin Assignment NC 1 VDD 2 Q0 3 Q0 4 Q1 5 Q1 6 GND 7 IN 8 16 NC 15 VDD 14 Q3 13 Q3 12 Q2 10 GND 16-pin 173 mil 0.65mm TSSOP PECL BUFFER Pin Descriptions Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name NC VDD Q0 Q1 GND IN GND Q2 Q3 VDD NC Type Power Output Power Input Power Output Power Pin Description No Connect. Connect to V or 5 V. Must be same as pin Clock Output Q0. Clock Output Q0. Clock Output Q1. Clock Output Q1. Connect to Ground. PECL Clock Input. Complementary PECL Clock Input. Connect to Ground Clock Output Q2. Clock Output Q2. Clock Output Q3. Clock Output Q3. Connect to V or 5 V. Must be same as pin No Connect. IDT / ICS LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT 2 ICS554-01A LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT PECL BUFFER External Components The ICS554-01A requires a decoupling capacitor of 0.01µF to be connected between VDD on pin 2 and GND on pin 7, as well as between VDD on pin 15 and GND on pin These decoupling capacitors should be placed as close to the device as possible. To achieve the low output skews that the ICS554-01A is capable of, careful attention must be paid to board layout. Essentially, all 8 outputs must have identical terminations, loads, and trace geometries. If they do not, the output skew will be degraded. For example, using a series termination on one output with on the others will cause at least 15ps of skew. Termination for PECL or LVPECL Outputs The clock layout topology shown below is a typical termination for PECL or LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate PECL/LVPECL compatible outputs. Therefore, termination resistors DC current path to ground or current sources must be used for functionality. These outputs are designed to drive 50 ohm transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. There are a few simple termination schemes. The figures below show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist, but it is recommended that board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT Z0 = 50 ohms Z0 = 50 ohms Ordering Information Part / Order Number 554G-01AI* 554G-01AIT* 554G-01AILF 554G-01AILFT Marking 554G01AI 554G1AIL Shipping Packaging Tubes Tape and Reel Tubes Tape and Reel Package 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP Temperature -40 to +85 ° C -40 to +85 ° C -40 to +85 ° C -40 to +85 ° C *NOTE EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology IDT assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT / ICS LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT 6 ICS554-01A LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT PECL BUFFER Innovate with IDT and accelerate your future networks. Contact: For Sales 800-345-7015 408-284-8200 Fax 408-284-2775 For Tech Support Corporate Headquarters Integrated Device Technology, Inc. 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT

DATASHEET

ICS554-01A

The ICS554-01A is a low skew clock buffer with a single complimentary PECL input to four PECL outputs. Part of IDT’s Clock BlocksTM family, this is our lowest skew PECL clock buffer. The ICS554-01A is footprint compatible with the ICS554-01, but requires fewer passive components for termination thus providing a cost-saving alternative. For parts which do not require PECL inputs or outputs, see the ICS553 for a 1 to 4 low skew buffer, or the ICS552-02 for a 1 to 8 low skew buffer. For more than 8 outputs see the MK74CBxxx BuffaloTM series of clock drivers.

IDT makes many non-PLL and PLL based low skew output devices as well as Zero Delay Buffers to synchronize clocks. Contact us for all of your clocking needs.
• Input frequency up to 200 MHz
• Advanced CMOS process
• Outputs are skew matched to within 50 ps
• Packaged in 16-pin TSSOP
• One PECL input to 4 PECL output clock drivers
• Operating Voltages of V or 5 V
• Industrial temperature range
• Functional equivalent to ICS554-01
• Simplified passive termination network compared to

ICS554-01

NOTE EOL for non-green parts to occur on 5/13/10 per PDN U-09-01

Block Diagram

IDT / ICS LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT 1

ICS554-01A LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT

Pin Assignment

NC 1 VDD 2

Q0 3 Q0 4 Q1 5 Q1 6 GND 7 IN 8
16 NC
15 VDD
14 Q3
13 Q3
12 Q2
10 GND
16-pin 173 mil 0.65mm TSSOP

PECL BUFFER

Pin Descriptions

Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Name

NC VDD Q0 Q1 GND

IN GND Q2 Q3 VDD NC

Type

Power Output Power Input Power Output Power

Pin Description

No Connect. Connect to V or 5 V. Must be same as pin Clock Output Q0. Clock Output Q0. Clock Output Q1. Clock Output Q1. Connect to Ground. PECL Clock Input. Complementary PECL Clock Input. Connect to Ground Clock Output Q2. Clock Output Q2. Clock Output Q3. Clock Output Q3. Connect to V or 5 V. Must be same as pin No Connect.

IDT / ICS LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT 2

ICS554-01A LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT

PECL BUFFER

External Components

The ICS554-01A requires a decoupling capacitor of 0.01µF to be connected between VDD on pin 2 and GND on pin 7, as well as between VDD on pin 15 and GND on pin These decoupling capacitors should be placed as close to the device as possible. To achieve the low output skews that the ICS554-01A is capable of, careful attention must be paid to board layout. Essentially, all 8 outputs must have identical terminations, loads, and trace geometries. If they do not, the output skew will be degraded. For example, using a series termination on one output with on the others will cause at least 15ps of skew.

Termination for PECL or LVPECL Outputs

The clock layout topology shown below is a typical termination for PECL or LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate PECL/LVPECL compatible outputs. Therefore, termination resistors DC current path to ground or current sources must be used for functionality. These outputs are designed to drive 50 ohm transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. There are a few simple termination schemes. The figures below show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist, but it is recommended that board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.

FOUT

Z0 = 50 ohms Z0 = 50 ohms
Ordering Information

Part / Order Number
554G-01AI* 554G-01AIT* 554G-01AILF 554G-01AILFT

Marking
554G01AI 554G1AIL

Shipping Packaging

Tubes Tape and Reel

Tubes Tape and Reel

Package
16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP

Temperature
-40 to +85 ° C -40 to +85 ° C -40 to +85 ° C -40 to +85 ° C
*NOTE EOL for non-green parts to occur on 5/13/10 per PDN U-09-01

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology IDT assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.

IDT / ICS LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT 6

ICS554-01A LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT

PECL BUFFER

Innovate with IDT and accelerate your future networks. Contact:

For Sales
800-345-7015 408-284-8200 Fax 408-284-2775

For Tech Support

Corporate Headquarters

Integrated Device Technology, Inc.
2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived ICS554G-01AIT Datasheet file may be downloaded here without warranties.

Datasheet ID: ICS554G-01AIT 637010