ICS1524AM

ICS1524AM Datasheet

ICS1524A

Part	Datasheet
ICS1524AM	ICS1524AM (pdf)

Related Parts	Information
ICS1524AMT	ICS1524AMT

PDF Datasheet Preview
Integrated Circuit Systems, Inc. ICS1524A Dual Output Phase Controlled SSTL_3/PECL Clock Generator The ICS1524A is a low-cost, very high-performance • frequency generator and phase controlled clock synthe- sizer. It is perfectly suited to phase controlled clock • synthesis and distribution as well as line-locked and genlocked applications. The ICS1524A offers two channels of clock phase con- trolled outputs CLK and DPACLK. These two output channels have both 250 MHz PECL differential and 150 MHz SSTL_3 single-ended output pins. The CLK output channel has a fixed phase relationship to the PLL’s input • and the DPACLK uses the Dynamic Phase Adjust circuitry to allow control of the clock phase relative to input • signal. Wide input frequency range • 8 kHz to 100 MHz 250 MHz balanced PECL differential outputs 150 MHz single-ended SSTL_3 clock outputs Dynamic Phase Adjust DPA for DPACLK outputs • Software controlled phase adjustment • 360o Adjustment down to 1/64 clock increments External or internal loop filter selection Uses VDC Inputs are 5 volt tolerant. I2C-bus serial interface runs at either low speed 100 kHz or high speed 400 kHz . Optionally, the CLK outputs can operate at half the clock rate and phase aligned with the DPACLK channel, enabling deMUXing of multiplexed analog-to-digital converters. The FUNC pin provides either the regenerated input from the phase-locked loop PLL divider chain output or a re-synchronized and sharpened input HSYNC. • Hardware and Software PLL Lock detection • Generic Frequency Synthesis • LCD Monitors and Projectors The advanced PLL uses either its internal program- mable feedback divider or an external divider and is programmed by a standard I2C-bus serial interface. • Genlocking Multiple Video Systems NOTE EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 Block Diagram Pin Configuration HSYNC OSC I2C Loop Filter CLK+/- DPACLK+/FUNC VDDD VSSD PDEN EXTFB HSYNC EXTFIL Ordering Information Part/Orde r Numbe r M arking Package IICCSS1152542A4MM IC1S52145A2M4M SIO C - 24 IICCSS1152542A4MMTT IC1S52145A2M4M SIO C - 24 ICS1524AMLF ICS1524AMLFT 1524AMLF SOIC-24 SOIC-24 Shipping Tubes Tape and Reel Tubes Tape and Reel While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated ICS assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. NOTES ICS1524A ICS1524A Integrated Circuit Systems, Inc. Corporate Headquarters: 2435 Boulevard of the Generals P.O. Box 968 Valley Forge, PA 19482-0968 Telephone 610-630-5300 Fax 610-630-5399 San Jose Operations: 525 Race Street San Jose, CA 95126-3448 Telephone 408-297-1201 Fax: 408-925-9460 Web Site:

PDF Datasheet Preview

Integrated Circuit Systems, Inc.

ICS1524A

Dual Output Phase Controlled SSTL_3/PECL Clock Generator

The ICS1524A is a low-cost, very high-performance
•
frequency generator and phase controlled clock synthe-
sizer. It is perfectly suited to phase controlled clock
•
synthesis and distribution as well as line-locked and
genlocked applications.

The ICS1524A offers two channels of clock phase con-
trolled outputs CLK and DPACLK. These two output
channels have both 250 MHz PECL differential and 150

MHz SSTL_3 single-ended output pins. The CLK output
channel has a fixed phase relationship to the PLL’s input
• and the DPACLK uses the Dynamic Phase Adjust circuitry to allow control of the clock phase relative to input
•
signal.

Wide input frequency range
• 8 kHz to 100 MHz
250 MHz balanced PECL differential outputs
150 MHz single-ended SSTL_3 clock outputs

Dynamic Phase Adjust DPA for DPACLK outputs
• Software controlled phase adjustment
• 360o Adjustment down to 1/64 clock increments

External or internal loop filter selection

Uses VDC Inputs are 5 volt tolerant. I2C-bus serial interface runs at either low speed 100 kHz or high speed 400 kHz .

Optionally, the CLK outputs can operate at half the clock rate and phase aligned with the DPACLK channel, enabling deMUXing of multiplexed analog-to-digital converters. The FUNC pin provides either the regenerated input from the phase-locked loop PLL divider chain output or a re-synchronized and sharpened input HSYNC.
• Hardware and Software PLL Lock detection
• Generic Frequency Synthesis
• LCD Monitors and Projectors

The advanced PLL uses either its internal program-
mable feedback divider or an external divider and is programmed by a standard I2C-bus serial interface.
• Genlocking Multiple Video Systems

NOTE EOL for non-green parts to occur on 5/13/10 per PDN U-09-01

Block Diagram

Pin Configuration

HSYNC OSC I2C

Loop Filter

CLK+/-

DPACLK+/FUNC

VDDD

VSSD

PDEN

EXTFB

HSYNC

EXTFIL
Ordering Information

Part/Orde r Numbe r

M arking

Package

IICCSS1152542A4MM

IC1S52145A2M4M

SIO C - 24

IICCSS1152542A4MMTT IC1S52145A2M4M

SIO C - 24

ICS1524AMLF ICS1524AMLFT
1524AMLF

SOIC-24 SOIC-24

Shipping

Tubes Tape and Reel

Tubes Tape and Reel

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated ICS assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.

NOTES

ICS1524A

ICS1524A

Integrated Circuit Systems, Inc.

Corporate Headquarters:
2435 Boulevard of the Generals P.O. Box 968 Valley Forge, PA 19482-0968 Telephone 610-630-5300 Fax 610-630-5399

San Jose Operations:
525 Race Street

San Jose, CA 95126-3448

Telephone 408-297-1201

Fax:
408-925-9460

Web Site:

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived ICS1524AM Datasheet file may be downloaded here without warranties.

Datasheet ID: ICS1524AM 636943