86004BGLF

86004BGLF Datasheet

86004

Part	Datasheet
86004BGLF	86004BGLF (pdf)

Related Parts	Information
86004BGLFT	86004BGLFT

PDF Datasheet Preview
15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/ LVTTL Zero Delay Clock Buffer 86004 DATASHEET The 86004 is a high performance 1:4 LVCMOS/LVTTL Clock Buffer. The 86004 has a fully integrated PLL and can be as zero delay buffer and has an input and output frequency range of 15.625MHz to 62.5MHz. The VCO operates at a frequency range of 250MHz to 500MHz. The external feedback allows the device to achieve “zero delay” between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output divider. • Four LVCMOS/LVTTL outputs, 7Ω typical output impedance • Single LVCMOS/LVTTL clock input • CLK accepts the following input levels LVCMOS or LVTTL • Output frequency range 15.625MHz to 62.5MHz • Input frequency range 15.625MHz to 62.5MHz • VCO range 250MHz to 500MHz • External feedback for “zero delay” clock regeneration with frequencies • Fully integrated PLL • Cycle-to-cycle jitter 65ps maximum • Output skew 65ps maximum • Full 3.3V or 2.5V, or 3.3V core/2.5V output operating supply • 0°C to 70° ambient operating temperature • Available in lead-free RoHS compliant package BLOCK DIAGRAM PIN ASSIGNMENT 86004 16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm package body G Package Top View 2015 Integrated Device Technology, Inc. 86004 DATA SHEET TABLE PIN DESCRIPTIONS Number Name Type 1, 3, 13, 15 Q1, Q0, Q3, Q2 Output Clock outputs. 7 typical output impedance. LVCMOS/LVTTL interface levels. Ω 2, 7, 14 GND Power Power supply ground. F_SEL Input Pulldown Frequency range select input. See Table 3A and 3B. LVCMOS/LVTTL interface levels. Power Core supply pin. CLK Input Pulldown LVCMOS/LVTTL clock input. Power Analog supply pin. Selects between the PLL and reference clock as input to the dividers. PLL_SEL Input Pullup When LOW, selects the reference clock PLL Bypass . When HIGH, selects PLL Enabled . LVCMOS/LVTTL interface levels. FB_IN Input Pulldown Feedback input to phase detector for regenerating clocks with “zero delay”. Connect to one of the outputs. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset Input Pulldown causing the outputs to go low. When logic LOW, the internal dividers and the TABLE ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 86004BGLF 86004BGL 16 Lead “Lead-Free” TSSOP Tube 0°C to 70°C 86004BGLFT 86004BGL 16 Lead “Lead-Free” TSSOP Tape & Reel 0°C to 70°C NOTE Parts that are ordered with an “LF” to the part number are the Pb-Free and are RoHS compliant. 15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/ LVTTL ZERO DELAY CLOCK BUFFER 86004 DATA SHEET Page 1 12 Description of Change Pin Assignment - corrected package body dimensions from 4mm x mm x 0.92mm to 4.4mm x5.0 mm x 0.925mm. Ordering Information Table - corrected marking from 86004BG from 86004BG. Added lead-free marking. 3.3V Power Supply Table - changed VD max from 3.465V to V , changed I from 79mA max. to 8mA max. 3.3V/2.5V Power Supply Table - changed VD max from 3.465V to V changed I from 79mA max. to 8mA max. 2.5V Power Supply Table - changed V max from 3.465V to V changed I from 79mA max. to 6mA max. Ordering Information - removed leaded devices. Updated data sheet format. Date 3/31/06 6/21/06 7/10/15 15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/ LVTTL ZERO DELAY CLOCK BUFFER Corporate Headquarters 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 or +408-284-8200 Fax 408-284-2775 Technical Support email: DISCLAIMER Integrated Device Technology, Inc. IDT and its subsidiaries reserve the right to modify the products and/or described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright All rights reserved.

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15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/ LVTTL Zero Delay Clock Buffer
86004

DATASHEET

The 86004 is a high performance 1:4 LVCMOS/LVTTL Clock Buffer. The 86004 has a fully integrated PLL and can be as zero delay buffer and has an input and output frequency range of 15.625MHz to 62.5MHz. The VCO operates at a frequency range of 250MHz to 500MHz. The external feedback allows the device to achieve “zero delay” between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output divider.
• Four LVCMOS/LVTTL outputs, 7Ω typical output impedance
• Single LVCMOS/LVTTL clock input
• CLK accepts the following input levels LVCMOS or LVTTL
• Output frequency range 15.625MHz to 62.5MHz
• Input frequency range 15.625MHz to 62.5MHz
• VCO range 250MHz to 500MHz
• External feedback for “zero delay” clock regeneration
with frequencies
• Fully integrated PLL
• Cycle-to-cycle jitter 65ps maximum
• Output skew 65ps maximum
• Full 3.3V or 2.5V, or 3.3V core/2.5V output operating supply
• 0°C to 70° ambient operating temperature
• Available in lead-free RoHS compliant package

BLOCK DIAGRAM

PIN ASSIGNMENT
86004
16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm package body

G Package Top View
2015 Integrated Device Technology, Inc.
86004 DATA SHEET

TABLE PIN DESCRIPTIONS

Number Name

Type
1, 3, 13, 15

Q1, Q0, Q3, Q2

Output

Clock outputs. 7 typical output impedance. LVCMOS/LVTTL interface levels. Ω
2, 7, 14

GND Power

Power supply ground.

F_SEL

Input

Pulldown

Frequency range select input. See Table 3A and 3B. LVCMOS/LVTTL interface levels.

Power

Core supply pin.

CLK Input Pulldown LVCMOS/LVTTL clock input.

Power

Analog supply pin.

Selects between the PLL and reference clock as input to the dividers.

PLL_SEL Input Pullup When LOW, selects the reference clock PLL Bypass . When HIGH,
selects PLL Enabled . LVCMOS/LVTTL interface levels.

FB_IN

Input

Pulldown

Feedback input to phase detector for regenerating clocks with “zero delay”. Connect to one of the outputs. LVCMOS/LVTTL interface levels.

Active HIGH Master Reset. When logic HIGH, the internal dividers are reset

Input Pulldown causing the outputs to go low. When logic LOW, the internal dividers and the
TABLE ORDERING INFORMATION

Part/Order Number

Marking

Package

Shipping Packaging Temperature
86004BGLF
86004BGL
16 Lead “Lead-Free” TSSOP

Tube
0°C to 70°C
86004BGLFT
86004BGL
16 Lead “Lead-Free” TSSOP

Tape & Reel
0°C to 70°C

NOTE Parts that are ordered with an “LF” to the part number are the Pb-Free and are RoHS compliant.
15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/

LVTTL ZERO DELAY CLOCK BUFFER
86004 DATA SHEET

Page 1 12

Description of Change

Pin Assignment - corrected package body dimensions from 4mm x mm x 0.92mm to 4.4mm x5.0 mm x 0.925mm.
Ordering Information Table - corrected marking from 86004BG from 86004BG. Added lead-free marking.
3.3V Power Supply Table - changed VD max from 3.465V to V ,
changed I from 79mA max. to 8mA max.
3.3V/2.5V Power Supply Table - changed VD max from 3.465V to V changed

I from 79mA max. to 8mA max.
2.5V Power Supply Table - changed V max from 3.465V to V
changed I from 79mA max. to 6mA max.
Ordering Information - removed leaded devices.

Updated data sheet format.

Date 3/31/06
6/21/06 7/10/15
15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/

LVTTL ZERO DELAY CLOCK BUFFER

Corporate Headquarters 6024 Silver Creek Valley Road San Jose, California 95138

Sales
800-345-7015 or +408-284-8200 Fax 408-284-2775

Technical Support email:

DISCLAIMER Integrated Device Technology, Inc. IDT and its subsidiaries reserve the right to modify the products and/or described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.

IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners.

Copyright All rights reserved.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 86004BGLF Datasheet file may be downloaded here without warranties.

Datasheet ID: 86004BGLF 636723