80KSBR201BRI8

80KSBR201BRI8 Datasheet

Product Brief 80KSBR201

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80KSBR201BRI8	80KSBR201BRI8 (pdf)

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80KSBR201BRI	80KSBR201BRI

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sRIO SERIAL BUFFER FLOW-CONTROL DEVICE Product Brief 80KSBR201 Device Overview The IDT80KSBR201 is a high speed Serial Buffer SerB that can connect up to two high-speed Serial RapidIO interfaces. This device is built to work with any sRIO device and especially with the IDT PreProcessing Switch PPS , IDT70K2000. The SerB performs buffering and off-loading of data as well as buffer-delay of data samples in various applications. This device can act as either a slave, waiting for other devices to read from it, or as a master in which the SerB writes data to a programmed location once some criteria have been meet. This combination of storage and flexibility make it the perfect buffering solution for sRIO systems. Two Independent Serial RapidIO Ports Partial Bridging Functions sRIO to sRIO to Parallel to sRIO Configurable Queues and Sizes Single/Dual Port Buffering Optional External QDR SRAM Available Up to 288 Mbit external QDR SRAM 200 MHz 18M, 36M, 72M, 144M or 288 M Seamless Integration of External and Internal Memory Internal and external memory functions as a single buffer Block Diagram Provides Status Flags for Combined Internal/External Memories Full, Empty, Partially Empty, Partially Full Direct or polled operation of flag status bus Optional Water mark Serial Buffer can Either Send a Flag or Transmit Data at a Specific Packet Count or Byte Count Interface - Serial Rapid IO sRIO One four-bit x4 link, configurable to one-bit x1 link Port Speeds selectable Gbps, Gbps, or Gbps Short haul or long haul reach for each PHY speed Error management supports standard and enhanced port operations sRIO version Class 1+ End Point Device Interface - Parallel Port Support for an optional external microprocessor or FPGA Supports QDRII Burst of 2 Interface Supports Packet or Raw-data format Interface - I2C Interface Port One I2C port for maintenance and error reporting Interface - JTAG JTAG Functionality for boundary scan and programming 10 Gbps Throughput High-Speed CMOS Technology 1.2V Core operation with 3.3/2.5V JTAG interface Package 484-pin Plastic Ball Grid Array 23mm x 23mm, 1.0mm ball pitch „2007 Integrated Device Technology, Inc. All rights reserved. Figure SerB Block Diagram 1 of 7 November 26, 2007 Notes Functional Description The IDT80KSBR201 is a Serial RapidIOTM sequential buffer SerB flow-control device consisting of up to 18Mbits of on-chip memory with expansion of one QDRII SRAM externally bringing the total buffering capacity to 90Mbits of storage. This device is built to work with any sRIO device and especially with the IDT Pre-Processing Switch PPS number IDT70K2000. In this configuration where multiple DSPs are used with the PPS, the SerB can function as an over-flow port to handle traffic that is on any given port or, as a delay buffer to store data and present it at a later time. This is important in DPS applications where time samples are compared with the previous sample such as Cellular Base Stations. Please refer to the application note “Serial Buffer and Pre-Processing Switch”. The 80KSBR201 fully complies to sRIO specification version and is implemented to a class 1+ end-point device. This device can operate as a master or a slave. In the sRIO environment, a master is defined as a device that originates data transfers, either to or from that device. A slave is one that responds to commands from other devices to move data. As a master, the SerB can receive data and at a pre-programmed water level either number of packets or bytes the device will form and transmit either packets or status e.g., doorbells to a programmed location. As a slave, the device will produce the data requested by other devices. For applications requiring larger buffers, an additional 72Mbits of QDR SRAM can be attached via the Parallel Port. The two memories are seamlessly connected by the Serial Buffer to form a large, 90 Mbit buffer memory. The QDR SRAM interface runs at speeds of only 155MHz allowing lower cost memories to be used as well as easier board layout. Data rates still support up to 10Gbits/s OC-192 throughput in the device to maintain full sRIO four-lane compliance. The device provides Full flag and Empty flag status for the queue selected for write and read operations respectively, and a Programmable Almost Full and Almost Empty flag for the queue is also provided. The device is configured into a single queue comprising the full internal memory and potentially the external memory if attached. The device treats the full amount of memory, internal or a combination of internal and external, as a single memory block. Status flags from that queue, either referring to the writes full flags or the reads empty flags to or from that queue represent the total amount of memory. Flags can be read from the serial port or from the I2C or JTAG port. Proactive flags can be configured to send a doorbell and/or change the interrupt pin once a flag is set. Partial full and empty flags can be programmed to provide reaction time for writes and reads respectively. Flags associated with reaching water marks are available in addition to the full and empty flags. The SerB is capable of translating between the selected protocols when more than one port is active. A JTAG test port is provided running at 3.3V, here the multi-queue flow-control device has a fully functional Boundary Scan feature, compliant with IEEE Standard Test Access Port and Boundary Scan Architecture. The SerB can also be programmed via the JTAG port. There is also an I2C processor port for programming and retrieving information from the configuration registers. In all applications, the SerB is a low pin count device, compared with equivalent FIFO storage devices that utilize parallel interfaces at an equivalent total bandwidth. The high-speed serial interfaces allow reduced pin count over parallel interfaces. Pre-Processing Switch Data Storage The SerB’s primary application is for a Basestation using the IDT’s Pre-Processing Switch PPS . The SerB will be a storage device, holding large amounts of data passed to it by the PPS. In this application, the S-Port 1 on the SerB will connect to one of the 4x ports of the PPS. The PPS will pass approximately 10ms of data to the SerB at which time the SerB will start to pass it back to the PPS as a multicast. It is expected that the data flow will remain constant with 10ms or other designated quantity worth of data always in storage. The Basestation uses the data for sample scattering noise reduction and alignment of control and data packets. „2007 Integrated Device Technology, Inc. All rights reserved. 2 of 7 November 26, 2007 Ordering Information For specific speeds, packages and powers, contact your sales office CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 7 of 7 „2007 Integrated Device Technology, Inc. All rights reserved. for Tech Support 408-360-1533 email: November 26, 2007

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sRIO SERIAL BUFFER FLOW-CONTROL DEVICE

Product Brief 80KSBR201

Device Overview

The IDT80KSBR201 is a high speed Serial Buffer SerB that can connect up to two high-speed Serial RapidIO interfaces. This device is built to work with any sRIO device and especially with the IDT PreProcessing Switch PPS , IDT70K2000. The SerB performs buffering and off-loading of data as well as buffer-delay of data samples in various applications. This device can act as either a slave, waiting for other devices to read from it, or as a master in which the SerB writes data to a programmed location once some criteria have been meet. This combination of storage and flexibility make it the perfect buffering solution for sRIO systems.

Two Independent Serial RapidIO Ports Partial Bridging Functions
sRIO to sRIO to Parallel to sRIO Configurable Queues and Sizes Single/Dual Port Buffering Optional External QDR SRAM Available Up to 288 Mbit external QDR SRAM 200 MHz 18M, 36M, 72M, 144M or 288 M Seamless Integration of External and Internal Memory Internal and external memory functions as a single buffer

Block Diagram

Provides Status Flags for Combined Internal/External

Memories

Full, Empty, Partially Empty, Partially Full Direct or polled operation of flag status bus

Optional Water mark

Serial Buffer can Either Send a Flag or Transmit Data at a Specific Packet Count or Byte Count

Interface - Serial Rapid IO sRIO

One four-bit x4 link, configurable to one-bit x1 link Port Speeds selectable Gbps, Gbps, or Gbps Short haul or long haul reach for each PHY speed Error management supports standard and enhanced port
operations sRIO version Class 1+ End Point Device Interface - Parallel Port

Support for an optional external microprocessor or FPGA Supports QDRII Burst of 2 Interface Supports Packet or Raw-data format Interface - I2C Interface Port One I2C port for maintenance and error reporting Interface - JTAG

JTAG Functionality for boundary scan and programming 10 Gbps Throughput

High-Speed CMOS Technology
1.2V Core operation with 3.3/2.5V JTAG interface Package 484-pin Plastic Ball Grid Array
23mm x 23mm, 1.0mm ball pitch
„2007 Integrated Device Technology, Inc. All rights reserved.

Figure SerB Block Diagram 1 of 7

November 26, 2007

Notes

Functional Description

The IDT80KSBR201 is a Serial RapidIOTM sequential buffer SerB flow-control device consisting of up to 18Mbits of on-chip memory with expansion of one QDRII SRAM externally bringing the total buffering capacity to 90Mbits of storage. This device is built to work with any sRIO device and especially with the IDT Pre-Processing Switch PPS number IDT70K2000.

In this configuration where multiple DSPs are used with the PPS, the SerB can function as an over-flow port to handle traffic that is on any given port or, as a delay buffer to store data and present it at a later time. This is important in DPS applications where time samples are compared with the previous sample such as Cellular Base Stations. Please refer to the application note “Serial Buffer and Pre-Processing Switch”.

The 80KSBR201 fully complies to sRIO specification version and is implemented to a class 1+ end-point device.

This device can operate as a master or a slave. In the sRIO environment, a master is defined as a device that originates data transfers, either to or from that device. A slave is one that responds to commands from other devices to move data. As a master, the SerB can receive data and at a pre-programmed water level either number of packets or bytes the device will form and transmit either packets or status e.g., doorbells to a programmed location. As a slave, the device will produce the data requested by other devices.

For applications requiring larger buffers, an additional 72Mbits of QDR SRAM can be attached via the Parallel Port. The two memories are seamlessly connected by the Serial Buffer to form a large, 90 Mbit buffer memory. The QDR SRAM interface runs at speeds of only 155MHz allowing lower cost memories to be used as well as easier board layout. Data rates still support up to 10Gbits/s OC-192 throughput in the device to maintain full sRIO four-lane compliance.

The device provides Full flag and Empty flag status for the queue selected for write and read operations respectively, and a Programmable Almost Full and Almost Empty flag for the queue is also provided.

The device is configured into a single queue comprising the full internal memory and potentially the external memory if attached. The device treats the full amount of memory, internal or a combination of internal and external, as a single memory block. Status flags from that queue, either referring to the writes full flags or the reads empty flags to or from that queue represent the total amount of memory. Flags can be read from the serial port or from the I2C or JTAG port. Proactive flags can be configured to send a doorbell and/or change the interrupt pin once a flag is set. Partial full and empty flags can be programmed to provide reaction time for writes and reads respectively. Flags associated with reaching water marks are available in addition to the full and empty flags.

The SerB is capable of translating between the selected protocols when more than one port is active.

A JTAG test port is provided running at 3.3V, here the multi-queue flow-control device has a fully functional Boundary Scan feature, compliant with IEEE Standard Test Access Port and Boundary Scan Architecture. The SerB can also be programmed via the JTAG port. There is also an I2C processor port for programming and retrieving information from the configuration registers.

In all applications, the SerB is a low pin count device, compared with equivalent FIFO storage devices that utilize parallel interfaces at an equivalent total bandwidth. The high-speed serial interfaces allow reduced pin count over parallel interfaces.

Pre-Processing Switch Data Storage

The SerB’s primary application is for a Basestation using the IDT’s Pre-Processing Switch PPS . The SerB will be a storage device, holding large amounts of data passed to it by the PPS. In this application, the S-Port 1 on the SerB will connect to one of the 4x ports of the PPS. The PPS will pass approximately 10ms of data to the SerB at which time the SerB will start to pass it back to the PPS as a multicast. It is expected that the data flow will remain constant with 10ms or other designated quantity worth of data always in storage.

The Basestation uses the data for sample scattering noise reduction and alignment of control and data packets.
„2007 Integrated Device Technology, Inc. All rights reserved.
2 of 7

November 26, 2007
Ordering Information

For specific speeds, packages and powers, contact your sales office

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775
7 of 7
„2007 Integrated Device Technology, Inc. All rights reserved.
for Tech Support 408-360-1533
email:

November 26, 2007

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 80KSBR201BRI8 Datasheet file may be downloaded here without warranties.

Datasheet ID: 80KSBR201BRI8 636643