IDT79RC32V334-100BBG

IDT79RC32V334-100BBG Datasheet

IDTTM InterpriseTM Integrated Communications Processor

Part	Datasheet
IDT79RC32V334-100BBG	IDT79RC32V334-100BBG (pdf)

Related Parts	Information
IDT79RC32V334-133BB	IDT79RC32V334-133BB
IDT79RC32V334-100BB	IDT79RC32V334-100BB
IDT79RC32V334-100BBGI	IDT79RC32V334-100BBGI
IDT79RC32V334-100BBI	IDT79RC32V334-100BBI
IDT79RC32V334-133BBG	IDT79RC32V334-133BBG
IDT79RC32V334-133BBGI	IDT79RC32V334-133BBGI
IDT79RC32V334-133BBI	IDT79RC32V334-133BBI
IDT79RC32V334-150BB	IDT79RC32V334-150BB
IDT79RC32V334-150BBG	IDT79RC32V334-150BBG
IDT79RC32V334-150BBGI	IDT79RC32V334-150BBGI
IDT79RC32V334-150BBI	IDT79RC32V334-150BBI

PDF Datasheet Preview
IDTTM InterpriseTM Integrated Communications Processor RC32300 32-bit Microprocessor Up to 150 MHz operation Enhanced MIPS-II Instruction Set Architecture ISA Cache prefetch instruction Conditional move instruction DSP instructions Supports big or little endian operation MMU with 32 page TLB 8kB Instruction Cache, 2-way set associative 2kB Data Cache, 2-way set associative Cache locking per line Programmable on a page basis to implement a write-through no write allocate, write-through write allocate, or write-back algorithms for cache management Compatible with a wide variety of operating systems Local Bus Interface Up to 75 MHz operation 26-bit address bus 32-bit data bus Direct control of local memory and peripherals Programmable system watch-dog timers Big or little endian support Interrupt Controller simplifies exception management Four general purpose 32-bit timer/counters Block Diagram Programmable I/O PIO Input/Output/Interrupt source Individually programmable SDRAM Controller 32-bit memory only 4 banks, non-interleaved Up to 512MB total SDRAM memory supported Implements full, direct control of discrete, SODIMM, or DIMM memories Supports 16Mb through 512Mb SDRAM device depths Automatic refresh generation Serial Peripheral Interface SPI master mode interface UART Interface Two 16550 compatible UARTs Baud rate support up to Mb/s Modem control signals available on one channel Memory & Peripheral Controller 6 banks, up to 64MB per bank Supports 8-,16-, and 32-bit interfaces Supports Flash ROM, SRAM, dual-port memory, and peripheral devices Supports external wait-state generation 8-bit boot PROM support Flexible I/O timing protocols EJTAG In-Circuit Emulator Interface RISCore32300 RC5000 Enhanced MIPS-II ISA Compatible Integer CPU 32-page TLB 2kB 2-set, Lockable Data Cache 2-set Lockable Instr. Cache IPBus Bridge Interrupt Control 32-bit Timers DMA Control Dual UART IDT Peripheral Bus Programmable I/O SPI Control Local Memory/IO Control SDRAM Control PCI Bridge 2004 Integrated Device Technology, Inc. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. 1 of 30 August 31, 2004 DSC 5701 IDT Y 4 DMA Channels 4 general purpose DMA, each with endianess swappers and byte lane data alignment Supports scatter/gather, chaining via linked lists of records Supports memory-to-memory, memory-to-I/O, memory-toPCI, PCI-to-PCI, and I/O-to-I/O transfers Supports unaligned transfers Supports burst transfers Programmable DMA bus transactions burst size up to 16 bytes Off-the-shelf development tools JTAG Interface IEEE Std. compatible 256-ball BGA 1.0mm spacing 3.3V operation with 5V tolerant I/O EJTAG in-circuit emulator interface Device Overview The IDT RC32334 device is an integrated processor based on the RC32300 CPU core. This product incorporates a high-performance, lowcost 32-bit CPU core with functionality common to a large number of embedded applications. The RC32334 integrates these functions to enable the use of low-cost PC commodity market memory and I/O devices, allowing the aggressive price/performance characteristics of the CPU to be realized quickly into low-cost systems. CPU Execution Core The RC32334 integrates the RISCore32300, the same CPU core found in the award-winning RC32364 microprocessor. The RISCore32300 implements the Enhanced MIPS-II ISA. Thus, it is upwardly compatible with applications written for a wide variety of MIPS architecture processors, and it is kernel compatible with the modern operating systems that support IDT’s 64-bit RISController product family. The RISCore32300 was explicitly defined and designed for integrated processor products such as the RC32334. Key attributes of the execution core found within this product include: memory transfers Selectable byte-ordering swapper 5V tolerant I/O. On-Chip DMA Controller To minimize CPU exception handling and maximize the efficiency of system bandwidth, the RC32334 integrates a very sophisticated 4channel DMA controller on chip. The RC32334 DMA controller is capable of Chaining and scatter/gather support through the use of a flexible, linked list of DMA transaction descriptors Capable of memory<->memory, memory<->I/O, and PCI<->memory DMA Unaligned transfer support Byte, halfword, word, quadword DMA support. On-Chip Peripherals The RC32334 also integrates peripherals that are common to a wide variety of embedded systems. Dual channel 16550 compatible UARTs, with modem control interface on one channel. SPI master mode interface for direct interface to EEPROM, A/D, etc. Interrupt Controller to speed interrupt decode and management Four 32-bit on-chip Timer/Counters Programmable I/O module Debug Support To facilitate rapid time to market, the RC32334 provides extensive support for system debug. First and foremost, this product integrates an EJTAG in-circuit emulation module, allowing a low-cost emulator to interoperate with programs executing on the controller. By using an augmented JTAG interface, the RC32334 is able to reuse the same low-cost emulators developed around the RC32364 CPU. Secondly, the RC32334 implements additional reporting signals intended to simplify the task of system debugging when using a logic analyzer. This product allows the logic analyzer to differentiate transactions initiated by DMA from those initiated by the CPU and further allows CPU transactions to be sorted into instruction fetches vs. data fetches. Finally, the RC32334 implements a full boundary scan capability, allowing board manufacturing diagnostics and debug. 3 of 30 August 31, 2004 IDT Y Packaging The RC32334 is packaged using a 256-lead PBGA package, with 1.0mm ball spacing. Thermal Considerations The RC32334 consumes less than W peak power. The device is guaranteed in an ambient temperature range of 0° to +70° C for commercial temperature devices -40° to +85° for industrial temperature devices. May 16, 2000 Initial version. June 8, 2000 In CPU Core Specific Signals section of Table 1, changed cpu_dr_r_n pin from Input to Output. Updated document from Advance to Preliminary Information. June 15, 2000 In Table 1, switched assertion and de-assertion for debug_cpu_dma_n signal. In the AC Timing Characteristics table, added SPI section and adjusted parameters in the Reset section. August 30, 2000 Added Standby mode and values to Power Consumption table. Extended Power Curve figure to 75 MHz. September 25, 2000 Changed MIPS32 ISA to Enhanced MIPS-II. In Local System Interface section of Table 6, changed Thld2 values for mem_data[31:0] from to ns and changed Tdoh3 values for mem_addr[25:2], etc. from to ns. December 12, 2000 Changed Max values for cpu_masterclock period in Table 5 and added footnote. In Table 1, added 2nd alternate function for spi_mosi, spi_miso, spi_sck. In Table 10, removed the “1” from Alt column for cpu_masterclk and added “2” in Alt column for pins G3, G4, H2. In RC32334 Alternate Signal Functions table added pin T2 added pin names in Alt #2 column for pins G3, G4, H2 added PIO[11] to Alt #2 column for pin R3. January 4, 2001 In Table 6 under Interrupt Handling, moved the values for Tsu9 from the Max to the Min columns. March 13, 2001 Changed upper ambient temperature for industrial and commercial uses from +70° C to +85° C. June 7, 2001 In the Clock Parameters table, added footnote 3 to output_clk category and added NA to Min and Max columns. In Figure 3 Reset Specification , enhanced signal line for cpu_masterclk. In Local System Interface section of AC Timing Characteristics table, changed values in Min column for last category of signals Tdoh3 from to for all speeds. In SDRAM Controller section of same table, changed values in Min column for last category of signals 9 signals from 1 to for all speeds. September 14, 2001 In the Reset category of Table 6 switched mem_addr[19:17] from Tsu22 and Thld22 to Tsu10 and Thld10 switched mem_addr[22:20] from Tsu10 and Thld10 to Tsu22 and Thld22 moved ejtag_pcst[2:0] from Reset to Debug Interface category under Tsu20 and Thld20. November 1, 2001 Added Input Voltage Undershoot parameter and 2 footnotes to Table March 20, 2002 In Local System Interface section of AC Timing Characteristics table, changed values in Min column for last category of signals Tdoh3 from to for all speeds. In Table 8, PCI Drive Output Pads, the Conditions for parameters VOL, VOH, VIL, and VIH were changed to read Per PCI September 18, 2002 Added cpu_coldreset_n rise time to Table 5, Clock Parameters. Added mem_addr[16] and sdram_addr[16] to Tables 1 and Changed Logic Diagram to include sdram_addr[16]. December 18, 2002 In the Reset section of Table 6, AC Timing Characteristics, setup and hold time categories for cpu_coldreset_n have been deleted. July 30, 2003 In Table 8, added 3 new categories Input Pads, PCI Input Pads, and All Pads and added footnotes 2 and March 24, 2004 In Table 1, changed description in Satellite Mode for pci_rst_n. Specified “cold” reset on pages 11 and Changed the maximum value for Vcc to in Table 10, Absolute Maximum Ratings, and changed footnote 1 to that table. Added Power Ramp-up section on page August 31, 2004 Added ”Green” orderable parts on page 4 of 30 August 31, 2004 IDT Y These signals provide the Memory or DRAM address, during a Memory or DRAM bus transaction. During [9:2] L [16:2] High each word data, the address increments either in linear or sub-block ordering, depending on the transac- tion type. The table below indicates how the memory write enable signals are used to address discreet memory port width types. Port Width Pin Signals mem_we_n[3] DMA 32-bit mem_we_n[3] mem_we_n[2] mem_we_n[1] mem_we_n[0] mem_we_n[2] mem_we_n[1] mem_we_n[0] 32-bit mem_we_n[3] mem_we_n[2] mem_we_n[1] mem_we_n[0] 16-bit 8-bit Byte High Write Enable mem_addr[1] Not Used Driven Low Not Used Driven High mem_addr[1] mem_addr[0] Byte Low Write Enable Byte Write Enable mem_cs_n[5:0] mem_oe_n Output H Output H mem_addr[22] Alternate function reset_boot_mode[1]. mem_addr[21] Alternate function reset_boot_mode[0]. mem_addr[20] Alternate function reset_pci_host_mode. mem_addr[19] Alternate function modebit mem_addr[18] Alternate function modebit mem_addr[17] Alternate function modebit mem_addr[16] Alternate function sdram_addr[16]. mem_addr[15] Alternate function sdram_addr[15]. mem_addr[14] Alternate function sdram_addr[14]. mem_addr[13] Alternate function sdram_addr[13]. mem_addr[11] Alternate function sdram_addr[11]. mem_addr[10] Alternate function sdram_addr[10]. mem_addr[9] Alternate function sdram_addr[9]. mem_addr[8] Alternate function sdram_addr[8]. mem_addr[7] Alternate function sdram_addr[7]. mem_addr[6] Alternate function sdram_addr[6]. mem_addr[5] Alternate function sdram_addr[5]. mem_addr[4] Alternate function sdram_addr[4]. mem_addr[3] Alternate function sdram_addr[3]. mem_addr[2] Alternate function sdram_addr[2]. Low with Memory Chip Select Negated internal Recommend external pull-up. pull-up Signals that a Memory Bank is actively selected. High Memory Output Enable Negated Recommend external pull-up. Signals that a Memory Bank can output its data lines onto the cpu_ad bus. Table 1 Pin Description Part 1 of 7 5 of 30 August 31, 2004 IDT Y Name mem_we_n[3:0] mem_wait_n mem_245_oe_n mem_245_dt_r_n output_clk PCI Interface pci_ad[31:0] pci_cbe_n[3:0] pci_par pci_frame_n pci_trdy_n pci_irdy_n pci_stop_n pci_idsel_n pci_perr_n pci_serr_n pci_clk Reset Drive Type State Strength Status Capability Output H High Memory Write Enable Negated Bus Signals which bytes are to be written during a memory transaction. Bits act as Byte Enable and mem_addr[1:0] signals for 8-bit or 16-bit wide addressing. Input Memory Wait Negated Requires external pull-up. SRAM/IOI/IOM modes Allows external wait-states to be injected during last cycle before data is sampled. DPM dual-port mode Allows dual-port busy signal to restart memory transaction. Alternate function sdram_wait_n. Mode Setting Multiply by 2 Multiply by 3 Multiply by 4 Reserved Little-endian ordering Big-endian ordering Enables timer interrupt Disables timer interrupt 11 of 30 August 31, 2004 IDT Y Mode Bit Value Mode Setting mem_addr[19:18] 9:8 MSB 9 Boot-Prom Width specifies the memory port width of the memory space which contains the boot prom. 00 8 bits 01 16 bits 10 32 bits 11 Reserved Table 2 Boot-Mode Configuration Settings Part 2 of 2 reset_boot_mode Settings By using the non-boot mode cold reset initialization mode the user can change the internal register addresses from base 1800_0000 to base 1900_0000, as required. The RC32334 cold reset-boot mode initialization setting values and mode descriptions are listed below. Reset Boot Mode Value Mode Settings mem_addr[22:21] 1:0 MSB 1 Tri-state memory bus and EEPROM bus during cold reset_n 11 Tri-state_bus_mode assertion Reserved PCI-boot mode pci_host_mode must be in satellite mode RC32334 will reset either from a cold reset or from a PCI reset. Boot code is provided via PCI. 01 PCI_boot_mode Standard-boot mode 00 standard_boot_mode Boot from the RC32334’s memory controller typical system . Table 3 RC32334 reset_boot_mode Initialization Settings pci_host_mode Settings During cold reset initialization, the RC32334’s PCI interface can be set to the Satellite or Host mode settings. When set to the Host mode, the CPU must configure the RC32334’s PCI configuration registers, including the read-only registers. If the RC32334’s PCI is in the PCI-boot mode Satellite mode, read-only configuration registers are loaded by the serial EEPROM. Reset Boot Mode Value Mode Settings mem_addr[20] PCI host mode PCI is in satellite mode 1 PCI_satellite PCI is in host mode typical system 0 PCI_host Table 4 RC32334 pci_host_mode Initialization Settings 12 of 30 August 31, 2004 Local System Interface SPI Interface SDRAM Signals IDT Y Logic Diagram RC32334 Ordering Information 79RCXX Product Type Operating Voltage Device Type CPU Frequency PP Package Temp range/ Process Blank = Commercial Temperature 0° C to +70° C Ambient I = Industrial Temperature -40° C to +85° C Ambient 100 MHz 133MHz BB = 256-pin PBGA BBG = 256-pin PBGA Green package 150MHz V = 3.3V ±5% 79RC32 = 32-bit family product Valid Combinations 79RC32V334 - 100BB, 133BB, 150BB 79RC32V334 - 100BBG, 133BBG, 150BBG 79RC32V334 - 100BBI, 133BBI, 150BBI 79RC32V334 - 100BBGI, 133BBGI, 150BBGI Commercial Green Industrial Green CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 30 of 30 for Tech Support email phone 408-284-8208 August 31, 2004

PDF Datasheet Preview

IDTTM InterpriseTM Integrated Communications Processor

RC32300 32-bit Microprocessor Up to 150 MHz operation Enhanced MIPS-II Instruction Set Architecture ISA Cache prefetch instruction Conditional move instruction DSP instructions Supports big or little endian operation MMU with 32 page TLB 8kB Instruction Cache, 2-way set associative 2kB Data Cache, 2-way set associative Cache locking per line Programmable on a page basis to implement a write-through no write allocate, write-through write allocate, or write-back algorithms for cache management Compatible with a wide variety of operating systems

Local Bus Interface Up to 75 MHz operation 26-bit address bus 32-bit data bus Direct control of local memory and peripherals Programmable system watch-dog timers Big or little endian support

Interrupt Controller simplifies exception management

Four general purpose 32-bit timer/counters

Block Diagram

Programmable I/O PIO Input/Output/Interrupt source Individually programmable

SDRAM Controller 32-bit memory only 4 banks, non-interleaved Up to 512MB total SDRAM memory supported Implements full, direct control of discrete, SODIMM, or DIMM memories Supports 16Mb through 512Mb SDRAM device depths Automatic refresh generation

Serial Peripheral Interface SPI master mode interface

UART Interface Two 16550 compatible UARTs Baud rate support up to Mb/s Modem control signals available on one channel

Memory & Peripheral Controller 6 banks, up to 64MB per bank Supports 8-,16-, and 32-bit interfaces Supports Flash ROM, SRAM, dual-port memory, and peripheral devices Supports external wait-state generation 8-bit boot PROM support Flexible I/O timing protocols

EJTAG In-Circuit Emulator Interface

RISCore32300

RC5000

Enhanced MIPS-II ISA Compatible

Integer CPU
32-page TLB
2kB 2-set, Lockable Data Cache
2-set Lockable Instr. Cache

IPBus Bridge

Interrupt Control 32-bit Timers DMA Control Dual UART

IDT Peripheral Bus

Programmable I/O

SPI Control

Local Memory/IO Control

SDRAM Control

PCI Bridge
2004 Integrated Device Technology, Inc.

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
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DSC 5701

IDT Y
4 DMA Channels 4 general purpose DMA, each with endianess swappers and byte lane data alignment Supports scatter/gather, chaining via linked lists of records Supports memory-to-memory, memory-to-I/O, memory-toPCI, PCI-to-PCI, and I/O-to-I/O transfers Supports unaligned transfers Supports burst transfers Programmable DMA bus transactions burst size up to 16 bytes

Off-the-shelf development tools JTAG Interface IEEE Std. compatible 256-ball BGA 1.0mm spacing 3.3V operation with 5V tolerant I/O EJTAG in-circuit emulator interface

Device Overview

The IDT RC32334 device is an integrated processor based on the RC32300 CPU core. This product incorporates a high-performance, lowcost 32-bit CPU core with functionality common to a large number of embedded applications. The RC32334 integrates these functions to enable the use of low-cost PC commodity market memory and I/O devices, allowing the aggressive price/performance characteristics of the CPU to be realized quickly into low-cost systems.

CPU Execution Core

The RC32334 integrates the RISCore32300, the same CPU core found in the award-winning RC32364 microprocessor.

The RISCore32300 implements the Enhanced MIPS-II ISA. Thus, it is upwardly compatible with applications written for a wide variety of MIPS architecture processors, and it is kernel compatible with the modern operating systems that support IDT’s 64-bit RISController product family.

The RISCore32300 was explicitly defined and designed for integrated processor products such as the RC32334. Key attributes of the execution core found within this product include:
memory transfers Selectable byte-ordering swapper 5V tolerant I/O.

On-Chip DMA Controller

To minimize CPU exception handling and maximize the efficiency of system bandwidth, the RC32334 integrates a very sophisticated 4channel DMA controller on chip.

The RC32334 DMA controller is capable of Chaining and scatter/gather support through the use of a flexible, linked list of DMA transaction descriptors Capable of memory<->memory, memory<->I/O, and PCI<->memory DMA Unaligned transfer support Byte, halfword, word, quadword DMA support.

On-Chip Peripherals

The RC32334 also integrates peripherals that are common to a wide variety of embedded systems.

Dual channel 16550 compatible UARTs, with modem control interface on one channel.

SPI master mode interface for direct interface to EEPROM, A/D, etc.

Interrupt Controller to speed interrupt decode and management Four 32-bit on-chip Timer/Counters Programmable I/O module

Debug Support

To facilitate rapid time to market, the RC32334 provides extensive support for system debug.

First and foremost, this product integrates an EJTAG in-circuit emulation module, allowing a low-cost emulator to interoperate with programs executing on the controller. By using an augmented JTAG interface, the RC32334 is able to reuse the same low-cost emulators developed around the RC32364 CPU.

Secondly, the RC32334 implements additional reporting signals intended to simplify the task of system debugging when using a logic analyzer. This product allows the logic analyzer to differentiate transactions initiated by DMA from those initiated by the CPU and further allows CPU transactions to be sorted into instruction fetches vs. data fetches.

Finally, the RC32334 implements a full boundary scan capability, allowing board manufacturing diagnostics and debug.
3 of 30

August 31, 2004

IDT Y

Packaging

The RC32334 is packaged using a 256-lead PBGA package, with 1.0mm ball spacing.

Thermal Considerations

The RC32334 consumes less than W peak power. The device is guaranteed in an ambient temperature range of 0° to +70° C for commercial temperature devices -40° to +85° for industrial temperature devices.

May 16, 2000 Initial version.

June 8, 2000 In CPU Core Specific Signals section of Table 1, changed cpu_dr_r_n pin from Input to Output. Updated document from Advance to Preliminary Information.

June 15, 2000 In Table 1, switched assertion and de-assertion for debug_cpu_dma_n signal. In the AC Timing Characteristics table, added SPI section and adjusted parameters in the Reset section.

August 30, 2000 Added Standby mode and values to Power Consumption table. Extended Power Curve figure to 75 MHz.

September 25, 2000 Changed MIPS32 ISA to Enhanced MIPS-II. In Local System Interface section of Table 6, changed Thld2 values for mem_data[31:0] from to ns and changed Tdoh3 values for mem_addr[25:2], etc. from to ns.

December 12, 2000 Changed Max values for cpu_masterclock period in Table 5 and added footnote. In Table 1, added 2nd alternate function for spi_mosi, spi_miso, spi_sck. In Table 10, removed the “1” from Alt column for cpu_masterclk and added “2” in Alt column for pins G3, G4, H2. In RC32334 Alternate Signal Functions table added pin T2 added pin names in Alt #2 column for pins G3, G4, H2 added PIO[11] to Alt #2 column for pin R3.

January 4, 2001 In Table 6 under Interrupt Handling, moved the values for Tsu9 from the Max to the Min columns.

March 13, 2001 Changed upper ambient temperature for industrial and commercial uses from +70° C to +85° C.

June 7, 2001 In the Clock Parameters table, added footnote 3 to output_clk category and added NA to Min and Max columns. In Figure 3 Reset Specification , enhanced signal line for cpu_masterclk. In Local System Interface section of AC Timing Characteristics table, changed values in Min column for last category of signals Tdoh3 from to for all speeds. In SDRAM Controller section of same table, changed values in Min column for last category of signals 9 signals from 1 to for all speeds.

September 14, 2001 In the Reset category of Table 6 switched mem_addr[19:17] from Tsu22 and Thld22 to Tsu10 and Thld10 switched mem_addr[22:20] from Tsu10 and Thld10 to Tsu22 and Thld22 moved ejtag_pcst[2:0] from Reset to Debug Interface category under Tsu20 and Thld20.

November 1, 2001 Added Input Voltage Undershoot parameter and 2 footnotes to Table

March 20, 2002 In Local System Interface section of AC Timing Characteristics table, changed values in Min column for last category of signals Tdoh3 from to for all speeds. In Table 8, PCI Drive Output Pads, the Conditions for parameters VOL, VOH, VIL, and VIH were changed to read Per PCI

September 18, 2002 Added cpu_coldreset_n rise time to Table 5, Clock Parameters. Added mem_addr[16] and sdram_addr[16] to Tables 1 and Changed Logic Diagram to include sdram_addr[16].

December 18, 2002 In the Reset section of Table 6, AC Timing Characteristics, setup and hold time categories for cpu_coldreset_n have been deleted.

July 30, 2003 In Table 8, added 3 new categories Input Pads, PCI Input Pads, and All Pads and added footnotes 2 and

March 24, 2004 In Table 1, changed description in Satellite Mode for pci_rst_n. Specified “cold” reset on pages 11 and Changed the maximum value for Vcc to in Table 10, Absolute Maximum Ratings, and changed footnote 1 to that table. Added Power Ramp-up section on page

August 31, 2004 Added ”Green” orderable parts on page
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IDT Y
These signals provide the Memory or DRAM address, during a Memory or DRAM bus transaction. During [9:2] L [16:2] High each word data, the address increments either in linear or sub-block ordering, depending on the transac-
tion type. The table below indicates how the memory write enable signals are used to address discreet memory port width types.

Port Width

Pin Signals mem_we_n[3]

DMA 32-bit mem_we_n[3]
mem_we_n[2] mem_we_n[1]
mem_we_n[0]
mem_we_n[2] mem_we_n[1]
mem_we_n[0]
32-bit
mem_we_n[3]
mem_we_n[2] mem_we_n[1]
mem_we_n[0]
16-bit 8-bit

Byte High Write Enable mem_addr[1] Not Used Driven Low

Not Used Driven High mem_addr[1] mem_addr[0]

Byte Low Write Enable

Byte Write Enable
mem_cs_n[5:0] mem_oe_n

Output H Output H
mem_addr[22] Alternate function reset_boot_mode[1]. mem_addr[21] Alternate function reset_boot_mode[0]. mem_addr[20] Alternate function reset_pci_host_mode. mem_addr[19] Alternate function modebit mem_addr[18] Alternate function modebit mem_addr[17] Alternate function modebit mem_addr[16] Alternate function sdram_addr[16]. mem_addr[15] Alternate function sdram_addr[15]. mem_addr[14] Alternate function sdram_addr[14]. mem_addr[13] Alternate function sdram_addr[13]. mem_addr[11] Alternate function sdram_addr[11]. mem_addr[10] Alternate function sdram_addr[10]. mem_addr[9] Alternate function sdram_addr[9]. mem_addr[8] Alternate function sdram_addr[8]. mem_addr[7] Alternate function sdram_addr[7]. mem_addr[6] Alternate function sdram_addr[6]. mem_addr[5] Alternate function sdram_addr[5]. mem_addr[4] Alternate function sdram_addr[4]. mem_addr[3] Alternate function sdram_addr[3]. mem_addr[2] Alternate function sdram_addr[2].

Low with Memory Chip Select Negated internal Recommend external pull-up. pull-up Signals that a Memory Bank is actively selected.

High Memory Output Enable Negated Recommend external pull-up. Signals that a Memory Bank can output its data lines onto the cpu_ad bus.

Table 1 Pin Description Part 1 of 7
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Name
mem_we_n[3:0] mem_wait_n
mem_245_oe_n mem_245_dt_r_n output_clk PCI Interface pci_ad[31:0] pci_cbe_n[3:0] pci_par pci_frame_n pci_trdy_n pci_irdy_n pci_stop_n pci_idsel_n pci_perr_n pci_serr_n
pci_clk

Reset Drive Type State Strength

Status Capability

Output H

High Memory Write Enable Negated Bus Signals which bytes are to be written during a memory transaction. Bits act as Byte Enable and mem_addr[1:0] signals for 8-bit or 16-bit wide addressing.

Input

Memory Wait Negated

Requires external pull-up.

SRAM/IOI/IOM modes Allows external wait-states to be injected during last cycle before data is sampled.

DPM dual-port mode Allows dual-port busy signal to restart memory transaction.

Alternate function sdram_wait_n.
Mode Setting Multiply by 2 Multiply by 3 Multiply by 4 Reserved Little-endian ordering Big-endian ordering

Enables timer interrupt Disables timer interrupt
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Mode Bit

Value Mode Setting
mem_addr[19:18] 9:8 MSB 9

Boot-Prom Width specifies the memory port width of the memory space which contains the boot prom.
00 8 bits 01 16 bits 10 32 bits
11 Reserved

Table 2 Boot-Mode Configuration Settings Part 2 of 2
reset_boot_mode Settings

By using the non-boot mode cold reset initialization mode the user can change the internal register addresses from base 1800_0000 to base 1900_0000, as required. The RC32334 cold reset-boot mode initialization setting values and mode descriptions are listed below.

Reset Boot Mode

Value Mode Settings
mem_addr[22:21] 1:0 MSB 1

Tri-state memory bus and EEPROM bus during cold reset_n 11 Tri-state_bus_mode assertion

Reserved

PCI-boot mode pci_host_mode must be in satellite mode RC32334 will reset either from a cold reset or from a PCI reset. Boot code is provided via PCI.
01 PCI_boot_mode

Standard-boot mode
00 standard_boot_mode

Boot from the RC32334’s memory controller typical system .

Table 3 RC32334 reset_boot_mode Initialization Settings
pci_host_mode Settings

During cold reset initialization, the RC32334’s PCI interface can be set to the Satellite or Host mode settings. When set to the Host mode, the CPU must configure the RC32334’s PCI configuration registers, including the read-only registers. If the RC32334’s PCI is in the PCI-boot mode Satellite mode, read-only configuration registers are loaded by the serial EEPROM.

Reset Boot Mode

Value Mode Settings
mem_addr[20] PCI host mode

PCI is in satellite mode
1 PCI_satellite

PCI is in host mode typical system 0 PCI_host

Table 4 RC32334 pci_host_mode Initialization Settings
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Local System Interface

SPI Interface

SDRAM Signals

IDT Y

Logic Diagram RC32334
Ordering Information
79RCXX

Product Type

Operating Voltage

Device Type

CPU Frequency

PP Package

Temp range/ Process

Blank = Commercial Temperature 0° C to +70° C Ambient I = Industrial Temperature -40° C to +85° C Ambient
100 MHz 133MHz

BB = 256-pin PBGA BBG = 256-pin PBGA Green package
150MHz

V = 3.3V ±5%
79RC32 = 32-bit family product

Valid Combinations
79RC32V334 - 100BB, 133BB, 150BB 79RC32V334 - 100BBG, 133BBG, 150BBG
79RC32V334 - 100BBI, 133BBI, 150BBI 79RC32V334 - 100BBGI, 133BBGI, 150BBGI

Commercial Green

Industrial Green

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775
30 of 30
for Tech Support email phone 408-284-8208

August 31, 2004

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Datasheet ID: IDT79RC32V334-100BBG 636641