WJLXT971ALC.A4-857342

WJLXT971ALC.A4-857342 Datasheet

Part	Datasheet
WJLXT971ALC.A4-857342	WJLXT971ALC.A4-857342 (pdf)

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WJLXT971ALC.A4-857344	WJLXT971ALC.A4-857344
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Cortina LXT971A Single-Port 10/100 Mbps PHY Transceiver Datasheet The Cortina LXT971A Single-Port 10/100 Mbps PHY Transceiver LXT971A PHY directly supports both 100BASE-TX and 10BASE-T applications. It provides a Media Independent Interface MII for easy attachment to 10/100 Media Access Controllers MACs . The LXT971A PHY is IEEE compliant, and provides a Low Voltage Positive Emitter Coupled Logic LVPECL interface for use with 100BASEFX fiber networks. The LXT971A PHY supports full-duplex operation at 10 Mbps and 100 Mbps. Operating conditions for the LXT971A PHY can be set using auto-negotiation, parallel detection, or manual control. The LXT971A PHY is fabricated with an advanced CMOS process and requires only a single V power supply. This Datasheet also supports the LXT971 PHY. - Combination 10BASE-T/100BASE-TX or 100BASE-FX Network Interface Cards NICs - Network printers - 10/100 Mbps PCMCIA cards - Cable Modems and Set-Top Boxes Product Features - V Operation - Carrier Sense Multiple Access / Collision - Low power consumption 300 mW typical Detection CSMA/CD or full-duplex operation - Low-power “Sleep” mode - JTAG boundary scan - 10BASE-T and 100BASE-TX using a single RJ- - MDIO serial port or hardware pin configurable 45 connection - 100BASE-FX fiber-optic capable - IEEE 802.3-compliant 10BASE-T or 100BASE- - Integrated, programmable LED drivers TX ports with integrated filters - 64-ball Plastic Ball Grid Array PBGA or 64-pin - Auto-negotiation and parallel detection Quad Flat Package LQFP - MII interface with extended register capability - Robust baseline wander correction - LXT971ABC - Commercial 0° to 70 °C amb. - LXT971ABE - Extended -40° to 85 °C amb. - LXT971ALC - Commercial 0° to 70 °C amb. - LXT971ALE - Extended -40° to 85 °C amb. - LXT972ALC - Commercial 0° to 70 °C amb. Legal Disclaimers INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH CORTINA PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN CORTINA’S TERMS AND CONDITIONS OF SALE OF SUCH PRODUCTS, CORTINA ASSUMES NO LIABILITY WHATSOEVER, AND CORTINA DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE AND/OR USE OF CORTINA PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Cortina products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Cortina and the Cortina Systems logo are the trademarks or registered trademarks of Cortina Systems, Inc. and its subsidiaries in the U.S. and other countries. Other names and brands may be claimed as the property of others. Copyright 2007 Cortina Systems, Inc. All rights reserved. Cortina LXT971A Single-Port 10/100 Mbps PHY Transceiver Contents Contents Introduction to This Document 10 Document Overview Related Documents 10 Block Diagram 11 Ball and Pin Assignments 12 Signal Descriptions 17 Functional 24 • Removed outdated Figure 4 64-Pin Pb-Free LQFP Package Pins Assignments • Removed the ordering information. This information is now available from Added Section Package Specifications back into Datasheet. First release of this document from Cortina Systems, Inc. Internal release. No changes. Front page text changed. Changed "PECL Interface" to "LVPECL Interface” in Figure 21 “Protocol Sublayers”. Replaced text under Section “Fiber PMD Sublayer”. Modified first paragraph under Section “The Fiber Interface”. Modified text and added a new bullet in first and second set of bullets under Section “The Fiber Interface”. Replaced Figure 27 “Recommended LXT971A-to-3.3 V Fiber PHY Interface Circuitry”. Replaced Figure 28 “Recommended LXT971A-to-5 V Fiber PHY Interface Circuitry”. Added Section Top Label Markings. Modified Section Product Ordering Information added RoHS information to Table 140, Product Ordering Information and changed Figure 123, Order Matrix for Cortina LXT971A Transceiver Sample. Globally replaced “pseudo-PECL” with Low-Voltage PECL”, except when identified with 5 V. Front Page Changed “pseudo-ECL PECL ” to “Low Voltage PECL LVPECL . Added “JTAG Boundary Scan” to Product Features on front page. Modified Figure 2 “LXT971A 64-Ball PBGA Assignments” replaced TEST1 and TEST0 with GND . Modified Figure 3 “LXT971A 64-Pin LQFP Assignments” replaced TEST1 and TEST0 with GND . Modified Table 1 “LQFP Numeric Pin List” replaced TEST1 and TEST0 with GND . Added note under Section “Signal Descriptions” “Intel recommends that all inputs and multi-function pins be tied to the inactive states and all outputs be left floating, if unused.” Cortina LXT971A Single-Port 10/100 Mbps PHY Transceiver Page 8 Modified SD/TP description in Table 3 “LXT971A Network Interface Signal Descriptions”. Added Table note Modified Table 4 “LXT971A Miscellaneous Signal Descriptions”. Modified Table 5 “LXT971A Power Supply Signal Descriptions”. Added Table 8 “LXT971A Pin Types and Modes”. Replaced second paragraph under Section “Fiber Interface”. Added Section “Increased MII Drive Strength”. Changed “Far-End Fault” title to ‘100BASE-FX Far-End Fault”. Modified first sentence under this heading. Modified Figure 8 “Hardware Configuration Settings”. Added paragraph after bullets under Section “Test Loopback”. Modified text under Section “Fiber PMD Sublayer”. Modified Table 13 “Supported JTAG Instructions”. Modified Table 14 “Device ID Register”. Added a new Section “The Fiber Interface”. Replaced Figure 25 “Recommended LXT971A-to-3.3 V Fiber PHY Interface Circuitry”. Added Figure 26 “Recommended LXT971A-to-5 V Fiber PHY Interface Circuitry”. Added Figure 27 “ON Semiconductor Triple PECL-to-LVPECL Logic Translator”. Modified Table 17 “Absolute Maximum Ratings”. Modified Table 18 “Operating Conditions” Added Typ values to Vcc current. Modified Table 20 “Digital I/O Characteristics - MII Pins”. Modified Table 22 “I/O Characteristics - LED/CFG Pins”. Added Table 23 “I/O Characteristics SD/TP Pin”. Added Table 28 “LXT971A Thermal Characteristics”. Modified Table 33 “10BASE-T Receive Timing Parameters” Modified Table 42 “register bit Map”. Added Table 26 information . Added Table 57 “Digital Configuration Register Address Modified Table 58 “Transmit Control Register Address Added Section “Product Ordering Information”. Clock Requirements Modified language under Clock Requirements heading. Table 21 I/O Characteristics REFCLK Changed values for Input Clock Duty Cycle under Min from 40 to 35 and under Max from 60 to Cortina LXT971A Single-Port 10/100 Mbps PHY Transceiver Page 9 Introduction to This Document Introduction to This Document This document includes information on the Cortina LXT971A Single-Port 10/ 100 Mbps PHY Transceiver LXT971A PHY . Document Overview This document includes the following subjects Block Diagram, on page 11 Ball and Pin Assignments, on page 12 Signal Descriptions, on page 17 Functional Description, on page 24 Application Information, on page 54 Electrical Specifications, on page 61 Register Definitions - IEEE Base Registers, on page 78 Register Definitions - Product-Specific Registers, on page 86 Related Documents Table 1 Related Documents Document Title Fiber Optic PHYs Connecting a PECL Interface Application Note Cortina 100BASE-FX Fiber Optic PHYs - Connecting a PECL/ LVPECL Interface Application Note Cortina LXT971A, LXT972A, LXT972M Single-Port 10/ 100 Mbps PHY Specification Update Cortina LXT971A, LXT972A, and LXT972M V PHY Design and Layout Guide - Application Note Magnetic Manufacturers for Networking Product Applications Application Note Document Number 249015 250781 249354 249016 248991 Cortina LXT971A Single-Port 10/100 Mbps PHY Transceiver Page 10 Block Diagram Block Diagram Figure 1 Block Diagram R ESET_ L ADDR[4:0] MDIO MDC MD I N T_ L MDDIS TX_EN TXD[3:0] TX_ER TX_CLK LED/CFG[3:1] RX_CLK RXD[3:0] RXDV CRS R X_ ER Management / Mode Select Logic Register Set Clock Generator Power Supply TX PCS Parallel /Serial Converter Manchester * Encoder 10 Scrambler 100 & Encoder For additional product and ordering information: ~ End of Document ~

PDF Datasheet Preview

Cortina LXT971A Single-Port 10/100 Mbps PHY Transceiver

Datasheet

The Cortina LXT971A Single-Port 10/100 Mbps PHY Transceiver LXT971A PHY directly supports both 100BASE-TX and 10BASE-T applications. It provides a Media Independent Interface MII for easy attachment to 10/100 Media Access Controllers MACs . The LXT971A PHY is IEEE compliant, and provides a Low Voltage Positive Emitter Coupled Logic LVPECL interface for use with 100BASEFX fiber networks. The LXT971A PHY supports full-duplex operation at 10 Mbps and 100 Mbps. Operating conditions for the LXT971A PHY can be set using auto-negotiation, parallel detection, or manual control. The LXT971A PHY is fabricated with an advanced CMOS process and requires only a single V power supply. This Datasheet also supports the LXT971 PHY.
- Combination 10BASE-T/100BASE-TX or 100BASE-FX Network Interface Cards NICs
- Network printers
- 10/100 Mbps PCMCIA cards - Cable Modems and Set-Top Boxes

Product Features
- V Operation
- Carrier Sense Multiple Access / Collision
- Low power consumption 300 mW typical

Detection CSMA/CD or full-duplex operation
- Low-power “Sleep” mode
- JTAG boundary scan
- 10BASE-T and 100BASE-TX using a single RJ- - MDIO serial port or hardware pin configurable
45 connection
- 100BASE-FX fiber-optic capable
- IEEE 802.3-compliant 10BASE-T or 100BASE- - Integrated, programmable LED drivers

TX ports with integrated filters
- 64-ball Plastic Ball Grid Array PBGA or 64-pin
- Auto-negotiation and parallel detection

Quad Flat Package LQFP
- MII interface with extended register capability - Robust baseline wander correction
- LXT971ABC - Commercial 0° to 70 °C amb. - LXT971ABE - Extended -40° to 85 °C amb.
- LXT971ALC - Commercial 0° to 70 °C amb.
- LXT971ALE - Extended -40° to 85 °C amb.
- LXT972ALC - Commercial 0° to 70 °C amb.

Legal Disclaimers

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH CORTINA PRODUCTS.

NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.

EXCEPT AS PROVIDED IN CORTINA’S TERMS AND CONDITIONS OF SALE OF SUCH PRODUCTS, CORTINA ASSUMES NO LIABILITY WHATSOEVER, AND CORTINA DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE AND/OR USE OF CORTINA PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

Cortina products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Cortina and the Cortina Systems logo are the trademarks or registered trademarks of Cortina Systems, Inc. and its subsidiaries in the U.S. and other countries. Other names and brands may be claimed as the property of others.

Copyright 2007 Cortina Systems, Inc. All rights reserved.

Cortina LXT971A Single-Port 10/100 Mbps PHY Transceiver

Contents

Contents

Introduction to This Document 10

Document Overview Related Documents 10

Block Diagram 11

Ball and Pin Assignments 12

Signal Descriptions 17

Functional 24
• Removed outdated Figure 4 64-Pin Pb-Free LQFP Package Pins Assignments
• Removed the ordering information. This information is now available from

Added Section Package Specifications back into Datasheet.

First release of this document from Cortina Systems, Inc.

Internal release. No changes.
Front page text changed. Changed "PECL Interface" to "LVPECL Interface” in Figure 21 “Protocol Sublayers”. Replaced text under Section “Fiber PMD Sublayer”. Modified first paragraph under Section “The Fiber Interface”. Modified text and added a new bullet in first and second set of bullets under Section “The Fiber Interface”. Replaced Figure 27 “Recommended LXT971A-to-3.3 V Fiber PHY Interface Circuitry”. Replaced Figure 28 “Recommended LXT971A-to-5 V Fiber PHY Interface Circuitry”. Added Section Top Label Markings. Modified Section Product Ordering Information added RoHS information to Table 140, Product Ordering Information and changed Figure 123, Order Matrix for Cortina LXT971A Transceiver Sample.

Globally replaced “pseudo-PECL” with Low-Voltage PECL”, except when identified with 5 V. Front Page Changed “pseudo-ECL PECL ” to “Low Voltage PECL LVPECL . Added “JTAG Boundary Scan” to Product Features on front page. Modified Figure 2 “LXT971A 64-Ball PBGA Assignments” replaced TEST1 and TEST0 with GND . Modified Figure 3 “LXT971A 64-Pin LQFP Assignments” replaced TEST1 and TEST0 with GND . Modified Table 1 “LQFP Numeric Pin List” replaced TEST1 and TEST0 with GND . Added note under Section “Signal Descriptions” “Intel recommends that all inputs and multi-function pins be tied to the inactive states and all outputs be left floating, if unused.”

Cortina LXT971A Single-Port 10/100 Mbps PHY Transceiver

Page 8
Modified SD/TP description in Table 3 “LXT971A Network Interface Signal Descriptions”. Added Table note Modified Table 4 “LXT971A Miscellaneous Signal Descriptions”. Modified Table 5 “LXT971A Power Supply Signal Descriptions”. Added Table 8 “LXT971A Pin Types and Modes”. Replaced second paragraph under Section “Fiber Interface”. Added Section “Increased MII Drive Strength”. Changed “Far-End Fault” title to ‘100BASE-FX Far-End Fault”. Modified first sentence under this heading. Modified Figure 8 “Hardware Configuration Settings”. Added paragraph after bullets under Section “Test Loopback”. Modified text under Section “Fiber PMD Sublayer”. Modified Table 13 “Supported JTAG Instructions”. Modified Table 14 “Device ID Register”. Added a new Section “The Fiber Interface”. Replaced Figure 25 “Recommended LXT971A-to-3.3 V Fiber PHY Interface Circuitry”. Added Figure 26 “Recommended LXT971A-to-5 V Fiber PHY Interface Circuitry”. Added Figure 27 “ON Semiconductor Triple PECL-to-LVPECL Logic Translator”. Modified Table 17 “Absolute Maximum Ratings”. Modified Table 18 “Operating Conditions” Added Typ values to Vcc current. Modified Table 20 “Digital I/O Characteristics - MII Pins”. Modified Table 22 “I/O Characteristics - LED/CFG Pins”. Added Table 23 “I/O Characteristics SD/TP Pin”. Added Table 28 “LXT971A Thermal Characteristics”. Modified Table 33 “10BASE-T Receive Timing Parameters” Modified Table 42 “register bit Map”. Added Table 26 information . Added Table 57 “Digital Configuration Register Address Modified Table 58 “Transmit Control Register Address Added Section “Product Ordering Information”.

Clock Requirements Modified language under Clock Requirements heading. Table 21 I/O Characteristics REFCLK Changed values for Input Clock Duty Cycle under Min from 40 to 35 and under Max from 60 to

Cortina LXT971A Single-Port 10/100 Mbps PHY Transceiver

Page 9

Introduction to This Document

Introduction to This Document

This document includes information on the Cortina LXT971A Single-Port 10/ 100 Mbps PHY Transceiver LXT971A PHY .

Document Overview

This document includes the following subjects Block Diagram, on page 11 Ball and Pin Assignments, on page 12 Signal Descriptions, on page 17 Functional Description, on page 24 Application Information, on page 54 Electrical Specifications, on page 61 Register Definitions - IEEE Base Registers, on page 78 Register Definitions - Product-Specific Registers, on page 86

Related Documents

Table 1

Related Documents

Document Title

Fiber Optic PHYs Connecting a PECL Interface Application Note Cortina 100BASE-FX Fiber Optic PHYs - Connecting a PECL/ LVPECL Interface Application Note Cortina LXT971A, LXT972A, LXT972M Single-Port 10/ 100 Mbps PHY Specification Update Cortina LXT971A, LXT972A, and LXT972M V PHY Design and Layout Guide - Application Note

Magnetic Manufacturers for Networking Product Applications Application Note

Document Number
249015 250781
249354
249016
248991

Cortina LXT971A Single-Port 10/100 Mbps PHY Transceiver

Page 10

Block Diagram

Block Diagram

Figure 1

Block Diagram

R ESET_ L ADDR[4:0]

MDIO MDC MD I N T_ L MDDIS TX_EN TXD[3:0] TX_ER TX_CLK

LED/CFG[3:1]

RX_CLK RXD[3:0]

RXDV CRS

R X_ ER

Management /

Mode Select Logic

Register Set

Clock Generator

Power Supply

TX PCS

Parallel /Serial Converter

Manchester * Encoder 10

Scrambler 100 & Encoder
For additional product and ordering information:
~ End of Document ~

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Datasheet ID: WJLXT971ALC.A4-857342 506894