PEB 20954 HT V1.1

PEB 20954 HT V1.1 Datasheet

Smart Integrated Digital Echo Canceller PEF/PEB 20954 HT, Version PEF/PEB 20954 E, Version

Part	Datasheet
PEB 20954 HT V1.1	PEB 20954 HT V1.1 (pdf)

Related Parts	Information
PEF 20954 HT V1.1	PEF 20954 HT V1.1

PDF Datasheet Preview
SIDEC Smart Integrated Digital Echo Canceller PEF/PEB 20954 HT, Version PEF/PEB 20954 E, Version Wireline Communications Never stop thinking. are registered trademarks of Infineon Technologies AG. 10BaseS , EasyPort , VDSLite are trademarks of Infineon Technologies AG. is a registered trademark of Microsoft Corporation, of Linus Torvalds, of Visio Corporation, and of Adobe Systems Incorporated. The information in this document is subject to change without notice. Edition 2004-07-28 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. SIDEC 2004-07-28 Previous Version: Data Sheet, DS1, 1999-04 Changes from previous version DS3, 2003-06-01 to DS4, 2003-09-01 Page 141 timing t_smon_delay document rearranged Additional configuration hints in the “Operational Description” on Page 51 and following pages wg_template_fm5_a5_2003-09-01.fm / DS4 PEB 20954 PEF 20954 Table of Contents Introduction 11 Key Features 12 Logic Symbol 15 Typical Applications 16 Pin Description 20 Pin Diagram 20 Pin Definitions and Functions for the P-TQFP-144-8 package 22 Pin Definitions and Functions for the P-LFBGA-160-2 Package 32 Functional Description 43 Functional Block Diagram and Description 43 Speech Control 43 Disabling Logic 44 Adaptive Echo Estimation Unit 44 PCM Input/Output Interface 44 Subtractor 45 Non Linear Processor 45 Microprocessor Interface 45 Universal Control and Communication Interface 45 Watchdog Timer 46 Clock Control 46 JTAG and RAM BIST 46 Test 46 Description of Functional Features 47 Channelwise and Global A- and m-Law Conversion 47 Bypass and Disabling Functions 48 UCC Interface 49 Operational Description 51 Pin Connection Diagram for SIDEC 51 Synchronization and Clock Modes 52 PCM Signal Timing and Frame Alignment 57 Timing of SYNCI and SYNCO 60 Clock Timing within External VCO Capture Range 61 Serial Interface Controlling and Monitoring Timing 62 UCC Interface Signal Timing and Frame Alignment 63 Speech Highway Control Signals for CAS in T1 Systems 66 Microprocessor Interface 67 Operational functions overview 67 Adaptive filter function 67 Filter 67 Filter coefficient adaptation 67 Stability / divergence protection 68 Data Sheet PEB 20954 PEF 20954 Ordering Information 14 General Pins 22 Synchronization 22 Microprocessor Interface 24 Microcontroller Port Extension 25 Processor Watchdog Circuit 26 Speech Highways 26 UCC Interface 27 Speech Highway Control Signals for CAS in T1 Systems 28 Channelwise Serial Interface 28 Test Interface for Boundary Scan according to IEEE 30 Test Interface 30 Power Supply. 31 Unused Pins. 31 General Pins 32 Synchronization 32 Microprocessor Interface 34 Microcontroller Port Extension 35 Processor Watchdog Circuit 36 Speech Highways 36 UCC Interface 37 Speech Highway Control Signals for CAS in T1 Systems 38 Channelwise Serial Interface 38 Test Interface for Boundary Scan according to IEEE 40 Test Interface 40 Power Supply. 41 Unused Pins. 42 Filter Parameter 70 Filter coefficient adaptation speed adjustment. 70 Coefficient damping 71 Auxiliary coefficient supervision 71 Sinusoidal non-voice signal protection 72 Overcompensation protection 74 Background noise measurement 75 Background noise insertion 76 SGMOD1/0 Configuration 100 AFI Coefficients to Absolute Linear Value Conversion 121 Conversion of Monitor Register Values to dBm0 Values 123 Clock Timing Characteristics preliminary . 132 Periods of Clock Signals 133 PCM Signal Timing and Frame Characteristics preliminary 136 Characteristics of Timing of SYNCI and SYNCO preliminary 138 Data Sheet PEB 20954 PEF 20954 List of Tables Table 43 Table 44 Table 45 Table 46 Table 47 Serial Interface Controlling and Monitoring Timing preliminary . 140 UCC Interface Signal Timing and Frame Alignment preliminary 145 Preliminary Internal Read and Write Signal Timing 147 Prliminary Microprocessor Interface Timing Values. 152 JTAG Boundary Scan Timing 156 Data Sheet PEB 20954 PEF 20954 Introduction Introduction The Smart Integrated Digital Echo Canceller SIDEC suppresses echoes in telecommunication networks which might disturb any kind of terrestrial or wireless communication. It incorporates leading edge CMOS technology as well as INFINEON’s' many years' experience in Telecommunication ICs. In communication links reflections resulting in an electrical echo are due to hybrid splits or imperfect terminations in subscribe loops. Acoustical echoes may occur due to poor isolation of microphone and speaker of some telephone system. These electrical and acoustical echoes disturb the quality of the transmission. To ensure high quality, pure data transmission the ITU-T International Telecommunications Union, Telecommunication Standardization Sector suggests in the recommendation G.131 the use of echo cancellers. Echo cancellation is extremely desirable for data links with total round trip transmission times of more than 50 ms. Data Sheet SIDEC Smart Integrated Digital Echo Canceller PEF/PEB 20954 HT Version Key Features • MHz PCM input and output interfaces with selectable µ- and A-Law coding according to ITU G.711 • Rapid convergence of patented algorithm at the beginning or during a connection even in the presence of background noise at the near end subscriber P-TQFP-144-6, -8, -14 • Echo return loss enhancement of > 30 dB ERLE • Detection of double talk for adaptive convergence control • Independently controlled voiceband echo cancelling according to ITU G.165 and G.168 for 32 channels with end echo path delay of less than 16 channels with end echo path delay of less than ms usage of two SIDEC in parallel for P-LFBGA-160-2 simultaneous processing of 32 channels is easily possible • Smart Non Linear Processor controlled by echoloss, echo path delay and background noise • Various options for comfort noise injection • Maskable disabling functions 2010 Hz continuity check SS7 via PCM timeslot 16 Bit a, b, c or d according to ITU G.704 individual channels maskable via Microprocessor Interface, UCC Interface and Serial Interface Ordering Information Table 1 Ordering Information Product Package PEB 20954 HT P-TQFP 144-8 0°C - 70°C PEF 20954 HT P-TQFP 144-8 -40°C - 85°C PEB 20954 E P-LFBGA-160-2 0°C - 70°C PEF 20954E P-LFBGA-160-2 -40°C - 85°C Q-Number Q67003 H9363 Q67003 H9364 Q67003 H9422 Q67003 H9423 PEB 20954 PEF 20954 Introduction Data Sheet Logic Symbol PEB 20954 PEF 20954 Introduction Boundary Scan Test Interface Test Interface Microcontroller Port Extension TMS TCK TDO TRST KSCMOD TEST KSCEN UPIO0 UPIO2 UPIO1 UPIO3 General Pins PORES MODE1 MODE0 Synchronization CLK32SEL CLK32 CTRL32 SCLKI SCLKO SYNCI SYNCO SDECI SDECO RFCLKF RFCLKN RFCLKEX CLK16 CTRL16 RFSPF RFSPN CLK4O Speech Highway Interface SI RI SO RO SO128 RO128 Processor Interface IM0 IM1 CS0 CS1 ALE RD/DS WR/RW INT RDY SIDEC PEB 20954 UPRES DISWD UPRES UPRESI Watchdog Interface UCCI TSIGM TMFBI UCCO TUCCO TMFBO UCC Interface Speech Highway Control Interface A0 - A6

PDF Datasheet Preview

SIDEC

Smart Integrated Digital Echo Canceller PEF/PEB 20954 HT, Version PEF/PEB 20954 E, Version

Wireline Communications

Never stop thinking.
are registered trademarks of Infineon Technologies AG. 10BaseS , EasyPort , VDSLite are trademarks of Infineon Technologies AG. is a registered trademark of Microsoft Corporation, of Linus Torvalds, of Visio Corporation, and of Adobe Systems Incorporated.

The information in this document is subject to change without notice.

Edition 2004-07-28

Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany

Infineon Technologies AG

All Rights Reserved.

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

SIDEC
2004-07-28

Previous Version:

Data Sheet, DS1, 1999-04

Changes from previous version DS3, 2003-06-01 to DS4, 2003-09-01

Page 141 timing t_smon_delay
document rearranged

Additional configuration hints in the “Operational Description” on Page 51 and following pages
wg_template_fm5_a5_2003-09-01.fm / DS4

PEB 20954 PEF 20954

Table of Contents

Introduction 11

Key Features 12

Logic Symbol 15

Typical Applications 16

Pin Description 20

Pin Diagram 20

Pin Definitions and Functions for the P-TQFP-144-8 package 22

Pin Definitions and Functions for the P-LFBGA-160-2 Package 32

Functional Description 43 Functional Block Diagram and Description 43

Speech Control 43 Disabling Logic 44 Adaptive Echo Estimation Unit 44 PCM Input/Output Interface 44 Subtractor 45 Non Linear Processor 45 Microprocessor Interface 45 Universal Control and Communication Interface 45 Watchdog Timer 46 Clock Control 46 JTAG and RAM BIST 46 Test 46 Description of Functional Features 47 Channelwise and Global A- and m-Law Conversion 47 Bypass and Disabling Functions 48 UCC Interface 49

Operational Description 51 Pin Connection Diagram for SIDEC 51 Synchronization and Clock Modes 52

PCM Signal Timing and Frame Alignment 57 Timing of SYNCI and SYNCO 60 Clock Timing within External VCO Capture Range 61 Serial Interface Controlling and Monitoring Timing 62 UCC Interface Signal Timing and Frame Alignment 63 Speech Highway Control Signals for CAS in T1 Systems 66 Microprocessor Interface 67 Operational functions overview 67 Adaptive filter function 67 Filter 67 Filter coefficient adaptation 67 Stability / divergence protection 68

Data Sheet

PEB 20954 PEF 20954
Ordering Information 14 General Pins 22 Synchronization 22 Microprocessor Interface 24 Microcontroller Port Extension 25 Processor Watchdog Circuit 26 Speech Highways 26 UCC Interface 27 Speech Highway Control Signals for CAS in T1 Systems 28 Channelwise Serial Interface 28 Test Interface for Boundary Scan according to IEEE 30 Test Interface 30 Power Supply. 31 Unused Pins. 31 General Pins 32 Synchronization 32 Microprocessor Interface 34 Microcontroller Port Extension 35 Processor Watchdog Circuit 36 Speech Highways 36 UCC Interface 37 Speech Highway Control Signals for CAS in T1 Systems 38 Channelwise Serial Interface 38 Test Interface for Boundary Scan according to IEEE 40 Test Interface 40 Power Supply. 41 Unused Pins. 42 Filter Parameter 70 Filter coefficient adaptation speed adjustment. 70 Coefficient damping 71 Auxiliary coefficient supervision 71 Sinusoidal non-voice signal protection 72 Overcompensation protection 74 Background noise measurement 75 Background noise insertion 76 SGMOD1/0 Configuration 100 AFI Coefficients to Absolute Linear Value Conversion 121 Conversion of Monitor Register Values to dBm0 Values 123 Clock Timing Characteristics preliminary . 132 Periods of Clock Signals 133 PCM Signal Timing and Frame Characteristics preliminary 136 Characteristics of Timing of SYNCI and SYNCO preliminary 138

Data Sheet

PEB 20954 PEF 20954

List of Tables

Table 43 Table 44 Table 45 Table 46 Table 47

Serial Interface Controlling and Monitoring Timing preliminary . 140 UCC Interface Signal Timing and Frame Alignment preliminary 145 Preliminary Internal Read and Write Signal Timing 147 Prliminary Microprocessor Interface Timing Values. 152 JTAG Boundary Scan Timing 156

Data Sheet

PEB 20954 PEF 20954

Introduction

Introduction

The Smart Integrated Digital Echo Canceller SIDEC suppresses echoes in telecommunication networks which might disturb any kind of terrestrial or wireless communication. It incorporates leading edge CMOS technology as well as INFINEON’s' many years' experience in Telecommunication ICs.

In communication links reflections resulting in an electrical echo are due to hybrid splits or imperfect terminations in subscribe loops. Acoustical echoes may occur due to poor isolation of microphone and speaker of some telephone system. These electrical and acoustical echoes disturb the quality of the transmission. To ensure high quality, pure data transmission the ITU-T International Telecommunications Union, Telecommunication Standardization Sector suggests in the recommendation G.131 the use of echo cancellers. Echo cancellation is extremely desirable for data links with total round trip transmission times of more than 50 ms.

Data Sheet

SIDEC Smart Integrated Digital Echo Canceller

PEF/PEB 20954 HT

Version

Key Features
• MHz PCM input and output interfaces with
selectable µ- and A-Law coding according to ITU

G.711
• Rapid convergence of patented algorithm at the
beginning or during a connection even in the presence
of background noise at the near end subscriber

P-TQFP-144-6, -8, -14
• Echo return loss enhancement of > 30 dB ERLE
• Detection of double talk for adaptive convergence
control
• Independently controlled voiceband echo cancelling
according to ITU G.165 and G.168 for
32 channels with end echo path delay of less than
16 channels with end echo path delay of less than ms usage of two SIDEC in parallel for P-LFBGA-160-2
simultaneous processing of 32 channels is easily
possible
• Smart Non Linear Processor controlled by echoloss, echo path delay and background
noise
• Various options for comfort noise injection
• Maskable disabling functions
2010 Hz continuity check SS7
via PCM timeslot 16 Bit a, b, c or d according to ITU G.704
individual channels maskable via Microprocessor Interface, UCC Interface and

Serial Interface
Ordering Information

Table 1
Ordering Information

Product

Package

PEB 20954 HT P-TQFP 144-8 0°C - 70°C

PEF 20954 HT P-TQFP 144-8 -40°C - 85°C

PEB 20954 E P-LFBGA-160-2 0°C - 70°C

PEF 20954E P-LFBGA-160-2 -40°C - 85°C

Q-Number Q67003 H9363 Q67003 H9364 Q67003 H9422 Q67003 H9423

PEB 20954 PEF 20954

Introduction

Data Sheet

Logic Symbol

PEB 20954 PEF 20954

Introduction

Boundary Scan Test Interface

Test Interface

Microcontroller Port

Extension

TMS TCK

TDO TRST

KSCMOD TEST KSCEN

UPIO0 UPIO2 UPIO1 UPIO3

General Pins

PORES MODE1 MODE0

Synchronization

CLK32SEL CLK32 CTRL32 SCLKI SCLKO SYNCI SYNCO SDECI SDECO RFCLKF RFCLKN RFCLKEX CLK16 CTRL16 RFSPF RFSPN CLK4O

Speech Highway Interface

SI RI SO RO SO128 RO128

Processor

Interface

IM0 IM1 CS0 CS1 ALE RD/DS WR/RW INT RDY

SIDEC PEB 20954

UPRES DISWD UPRES UPRESI

Watchdog Interface

UCCI

TSIGM TMFBI

UCCO TUCCO

TMFBO

UCC Interface

Speech Highway Control Interface

A0 - A6

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived PEB20954HTV1.1 Datasheet file may be downloaded here without warranties.

Datasheet ID: PEB20954HTV1.1 638418