XR16V2551IMTR-F

XR16V2551IMTR-F Datasheet

XR16V2551

Part	Datasheet
XR16V2551IMTR-F	XR16V2551IMTR-F (pdf)

Related Parts	Information
XR16V2551ILTR-F	XR16V2551ILTR-F

PDF Datasheet Preview
XR16V2551 DECEMBER 2011 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE The XR16V25511 V2551 is a high performance dual universal asynchronous receiver and transmitter UART with 16 byte TX and RX FIFOs. The device operates from to volts with 5 Volt tolerant inputs and is pin-to-pin compatible to Exar’s XR16V2651 and XR16L2551. The device includes 2 additional capabilities over the XR16V2550 Intel and Motorola data bus selection and a “PowerSave” mode to further reduce sleep current to a minimum during sleep mode. It supports Exar’s enhanced features of selectable FIFO trigger level, automatic hardware RTS/CTS and software flow control, and a complete modem interface. An internal loopback capability allows system diagnostics. Independent programmable fractional baud rate generators are provided in each channel to select data rates up to 16 Mbps at Volt and 4X sampling clock. The V2551 is available in 48-pin TQFP and 32-pin QFN packages. NOTE 1 Covered by U.S. Patent #5,649,122 • Portable Appliances • Telecommunication Network Routers • Ethernet Network Routers • Cellular Data Devices • Factory Automation and Process Controls • to Volt Operation • 5 Volt Tolerant Inputs • Intel or Motorola Mode • Pin-to-pin compatible to Exar’s XR16V2651 and the XR16L2551 • Two independent UART channels • Register set identical to 16V2550 • Data rate of up to 16 Mbps at V, and Mbps at V with 4X sampling rate • Fractional Baud Rate Generator • Transmit and Receive FIFOs of 16 bytes • Selectable TX and RX FIFO Trigger Levels • Automatic Hardware RTS/CTS Flow Control • Automatic Software Xon/Xoff Flow Control • Wireless Infrared IrDA Encoder/Decoder • Automatic sleep mode with wake-up interrupt • Full modem interface up to 64MHz input • 48-TQFP and 32-QFN packages FIGURE XR16V2551 BLOCK DIAGRAM PwrSave A2:A0 D7:D0 IOR# VCC IOW# R/W# CSA# CS# CSB# A3 INTA IRQ# INTB logic 0 TXRDYA# TXRDYB# RXRDYA# RXRDYB# Reset# 16/68# CLKSEL Intel or Motorola Data Bus Interface *5 Volt Tolerant Inputs UART Channel A UART Regs 16 Byte TX FIFO TX & RX IR ENDEC 16 Byte RX FIFO UART Channel B same as Channel A Crystal Osc/Buffer to 3.6V VCC GND TXA, RXA, DTRA#, DSRA#, RTSA#, DTSA#, CDA#, RIA#, OP2A# TXB, RXB, DTRB#, DSRB#, RTSB#, CTSB#, CDB#, RIB#, OP2B# XTAL1 XTAL2 Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510 668-7000 • FAX 510 668-7017 • XR16V2551 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE FIGURE PIN OUT ASSIGNMENT 32 D5 31 D4 30 D3 29 D2 28 D1 27 D0 26 VCC 25 CTSA# 32 D5 31 D4 30 D3 29 D2 28 D1 27 D0 26 VCC 25 CTSA# ORDERING INFORMATION PART NUMBER XR16V2551IL-F XR16V2551ILTR-F XR16V2551IM-F XR16V2551IMTR-F PACKAGE 32-pin QFN 32-pin QFN 48-Lead TQFP 48-Lead TQFP NOTE TR = Tape and Reel, F = Green / RoHS OPERATING TEMPERATURE RANGE -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C DEVICE STATUS Active XR16V2551 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE PIN DESCRIPTIONS Pin Description NAME 32-QFN 48-TQFP TYPE PIN # PIN # DATA BUS INTERFACE IOR# IOW# R/W# CSA# CSB# INTA IRQ# I Address data lines These 3 address lines select one of the internal registers in UART channel A/B during a data bus transaction. I/O Data bus lines [7:0] bidirectional . I When 16/68# pin is HIGH, the Intel bus interface is selected and this input becomes read strobe active low . The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed by the address lines [A2:A0], puts the data byte on the data bus to allow the host processor to read it on the rising edge. When 16/68# pin is LOW, the Motorola bus interface is selected and this input is not used and should be connected to VCC. I When 16/68# pin is HIGH, it selects Intel bus interface and this input becomes write strobe active low . The falling edge instigates the internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. When 16/68# pin is LOW, the Motorola bus interface is selected and this input becomes read HIGH and write LOW signal. I When 16/68# pin is HIGH, this input is chip select A active low to enable channel A in the device. When 16/68# pin is LOW, this input becomes the chip select active low for the Motorola bus interface. I When 16/68# pin is HIGH, this input is chip select B active low to enable channel B in the device. When 16/68# pin is LOW, this input becomes address line A3 which is used for channel selection in the Motorola bus interface. Input logic 0 selects channel A and logic 1 selects channel B. O When 16/68# pin is HIGH for Intel bus interface, this output becomes channel A interrupt output. The output state is defined by the user through the software setting of MCR[3]. INTA is set to the active mode and OP2A# output to a logic 0 when MCR[3] is set to a logic INTA is set to the three state mode and OP2A# to a logic 1 when MCR[3] is set to a logic See MCR[3]. When 16/68# pin is LOW for Motorola bus interface, this output becomes device interrupt output active low, open drain . An external pull-up resistor is required for proper operation. XR16V2551 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE Pin Description NAME 32-QFN 48-TQFP TYPE PIN # PIN # INTB O UART channel B Interrupt output. The output state is defined by the user through the software setting of MCR[3]. INTB is set to the active mode and OP2B# output LOW when MCR[3] is set to a logic INTB is set to the three state mode and OP2B# output HIGH when MCR[3] is set to a logic 0 default . See MCR[3]. TXRDYA# - O UART channel A Transmitter Ready active low . The output provides the TX FIFO/ THR status for transmit channel A. See Table If it is not used, leave it uncon- DESCRIPTION Preliminary Datasheet Final Datasheet. Updated AC Electrical Characteristics. Added "GND Center Pad" to pin description. Updated 32 pin QFN package dimensions drawing to show minimum "k" parameter. Updated "AC electrical characteristc" table and pin description table. Corrected "CLKSEL" pin to NC No connection Updated ordering information. NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that a the risk of injury or damage has been minimized b the user assumes all such risks c potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2011 EXAR Corporation Datasheet December Send your UART technical inquiry with technical details to hotline: Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

PDF Datasheet Preview

XR16V2551

DECEMBER 2011

HIGH PERFORMANCE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE

The XR16V25511 V2551 is a high performance dual universal asynchronous receiver and transmitter UART with 16 byte TX and RX FIFOs. The device operates from to volts with 5 Volt tolerant inputs and is pin-to-pin compatible to Exar’s XR16V2651 and XR16L2551. The device includes 2 additional capabilities over the XR16V2550 Intel and Motorola data bus selection and a “PowerSave” mode to further reduce sleep current to a minimum during sleep mode. It supports Exar’s enhanced features of selectable FIFO trigger level, automatic hardware RTS/CTS and software flow control, and a complete modem interface. An internal loopback capability allows system diagnostics. Independent programmable fractional baud rate generators are provided in each channel to select data rates up to 16 Mbps at Volt and 4X sampling clock. The V2551 is available in 48-pin TQFP and 32-pin QFN packages.

NOTE 1 Covered by U.S. Patent #5,649,122
• Portable Appliances
• Telecommunication Network Routers
• Ethernet Network Routers
• Cellular Data Devices
• Factory Automation and Process Controls
• to Volt Operation
• 5 Volt Tolerant Inputs
• Intel or Motorola Mode
• Pin-to-pin compatible to Exar’s XR16V2651 and the

XR16L2551
• Two independent UART channels
• Register set identical to 16V2550
• Data rate of up to 16 Mbps at V, and

Mbps at V with 4X sampling rate
• Fractional Baud Rate Generator
• Transmit and Receive FIFOs of 16 bytes
• Selectable TX and RX FIFO Trigger Levels
• Automatic Hardware RTS/CTS Flow Control
• Automatic Software Xon/Xoff Flow Control
• Wireless Infrared IrDA Encoder/Decoder
• Automatic sleep mode with wake-up interrupt
• Full modem interface
up to 64MHz input
• 48-TQFP and 32-QFN packages

FIGURE XR16V2551 BLOCK DIAGRAM

PwrSave

A2:A0 D7:D0 IOR# VCC IOW# R/W# CSA# CS# CSB# A3 INTA IRQ# INTB logic 0

TXRDYA# TXRDYB# RXRDYA# RXRDYB#

Reset# 16/68# CLKSEL

Intel or Motorola Data Bus Interface
*5 Volt Tolerant Inputs

UART Channel A

UART Regs
16 Byte TX FIFO

TX & RX

IR ENDEC
16 Byte RX FIFO

UART Channel B same as Channel A

Crystal Osc/Buffer
to 3.6V VCC GND

TXA, RXA, DTRA#, DSRA#, RTSA#, DTSA#, CDA#, RIA#, OP2A#

TXB, RXB, DTRB#, DSRB#, RTSB#, CTSB#, CDB#, RIB#, OP2B# XTAL1 XTAL2

Exar Corporation 48720 Kato Road, Fremont CA, 94538
• 510 668-7000
• FAX 510 668-7017
•

XR16V2551

HIGH PERFORMANCE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE

FIGURE PIN OUT ASSIGNMENT
32 D5 31 D4 30 D3 29 D2 28 D1 27 D0 26 VCC 25 CTSA#
32 D5 31 D4 30 D3 29 D2 28 D1 27 D0 26 VCC 25 CTSA#
ORDERING INFORMATION

PART NUMBER XR16V2551IL-F XR16V2551ILTR-F XR16V2551IM-F XR16V2551IMTR-F

PACKAGE 32-pin QFN 32-pin QFN 48-Lead TQFP 48-Lead TQFP

NOTE TR = Tape and Reel, F = Green / RoHS

OPERATING TEMPERATURE RANGE -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C

DEVICE STATUS Active

XR16V2551

HIGH PERFORMANCE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE

PIN DESCRIPTIONS

Pin Description

NAME
32-QFN 48-TQFP TYPE

PIN # PIN #

DATA BUS INTERFACE

IOR#

IOW#

R/W#

CSA#

CSB#

INTA

IRQ#

I Address data lines These 3 address lines select one of the internal registers in UART channel A/B during a data bus transaction.

I/O Data bus lines [7:0] bidirectional .

I When 16/68# pin is HIGH, the Intel bus interface is selected and this input becomes read strobe active low . The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed by the address lines [A2:A0], puts the data byte on the data bus to allow the host processor to read it on the rising edge. When 16/68# pin is LOW, the Motorola bus interface is selected and this input is not used and should be connected to VCC.

I When 16/68# pin is HIGH, it selects Intel bus interface and this input becomes write strobe active low . The falling edge instigates the internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. When 16/68# pin is LOW, the Motorola bus interface is selected and this input becomes read HIGH and write LOW signal.

I When 16/68# pin is HIGH, this input is chip select A active low to enable channel A in the device. When 16/68# pin is LOW, this input becomes the chip select active low for the Motorola bus interface.

I When 16/68# pin is HIGH, this input is chip select B active low to enable channel B in the device. When 16/68# pin is LOW, this input becomes address line A3 which is used for channel selection in the Motorola bus interface. Input logic 0 selects channel A and logic 1 selects channel B.

O When 16/68# pin is HIGH for Intel bus interface, this output becomes channel A interrupt output. The output state is defined by the user through the software setting of MCR[3]. INTA is set to the active mode and OP2A# output to a logic 0 when MCR[3] is set to a logic INTA is set to the three state mode and OP2A# to a logic 1 when MCR[3] is set to a logic See MCR[3]. When 16/68# pin is LOW for Motorola bus interface, this output becomes device interrupt output active low, open drain . An external pull-up resistor is required for proper operation.

XR16V2551

HIGH PERFORMANCE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE Pin Description

NAME
32-QFN 48-TQFP TYPE

PIN # PIN #

INTB

O UART channel B Interrupt output. The output state is defined by the user through
the software setting of MCR[3]. INTB is set to the active mode and OP2B# output

LOW when MCR[3] is set to a logic INTB is set to the three state mode and

OP2B# output HIGH when MCR[3] is set to a logic 0 default . See MCR[3].

TXRDYA# -

O UART channel A Transmitter Ready active low . The output provides the TX FIFO/

THR status for transmit channel A. See Table If it is not used, leave it uncon-
DESCRIPTION Preliminary Datasheet Final Datasheet. Updated AC Electrical Characteristics. Added "GND Center Pad" to pin description. Updated 32 pin QFN package dimensions drawing to show minimum "k" parameter. Updated "AC electrical characteristc" table and pin description table. Corrected "CLKSEL" pin to NC No connection Updated ordering information.

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that a the risk of injury or damage has been minimized b the user assumes all such risks c potential liability of EXAR Corporation is adequately protected under the circumstances.

Copyright 2011 EXAR Corporation

Datasheet December

Send your UART technical inquiry with technical details to hotline:

Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

More datasheets: 4N46-500E | 4N46#300 | 4N46#060 | 4N45#300 | 4N45#060 | 4N45#500 | 4N45 | 4N46 | 4N46-000E | XR16V2551ILTR-F

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived XR16V2551IMTR-F Datasheet file may be downloaded here without warranties.

Datasheet ID: XR16V2551IMTR-F 512921