XR16M554IJ68TR-F

XR16M554IJ68TR-F Datasheet

XR16M554/554D

Part	Datasheet
XR16M554IJ68TR-F	XR16M554IJ68TR-F (pdf)

Related Parts	Information
XR16M554DIV64TR-F	XR16M554DIV64TR-F
XR16M554IL48TR-F	XR16M554IL48TR-F

PDF Datasheet Preview
XR16M554/554D 1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO MAY 2008 The XR16M554 M554 is a quad Universal Asynchronous Receiver and Transmitter UART with 16 bytes of transmit and receive FIFOs, selectable receive FIFO trigger levels and data rates of up to 4 Mbps at V. Each UART has a set of registers that provide the user with operating status and control, receiver error indications, and modem serial interface controls. An internal loopback capability allows onboard diagnostics. The M554 is available in a 48pin QFN, 64-pin LQFP, 68-pin PLCC and 80-pin LQFP packages. The 64-pin and 80-pin packages only offer the 16 mode interface, but the 48- and 68pin packages offer an additional 68 mode interface which allows easy integration with Motorola processors. The XR16M554IV 64-pin offers three state interrupt output while the XR16M554DIV provides continuous interrupt output. The XR16M554 is compatible with the industry standard ST16C554. • Pin-to-pin compatible with ST16C454, ST16C554, TI’s TL16C554A and NXP’s SC16C554B • Intel or Motorola Data Bus Interface select • Four independent UART channels • Register Set Compatible to 16C550 • Data rates of up to 4 Mbps at V, Mbps at V and 2 Mbps at V • 16 byte Transmit FIFO • 16 byte Receive FIFO with error tags • 4 Selectable RX FIFO Trigger Levels • Full modem interface • 1.62V to 3.63V supply operation • Crystal oscillator or external clock input • Portable Appliances • Telecommunication Network Routers • Ethernet Network Routers • Cellular Data Devices • Factory Automation and Process Controls FIGURE XR16M554 BLOCK DIAGRAM A2:A0 D7:D0 IOR# IOW# CSA# CSB# CSC# CSD# INTA INTB INTC INTD TXRDY# A-D RXRDY# A-D Reset 16/68# INTSEL Data Bus Interface UART Channel A UART 16 Byte TX FIFO Regs TX & RX BRG 16 Byte RX FIFO UART Channel B same as Channel A UART Channel C same as Channel A UART Channel D same as Channel A Crystal Osc / Buffer V to V VCC GND TXA, RXA, DTRA#, DSRA#, RTSA#, CTSA#, CDA#, RIA# TXB, RXB, DTRB#, DSRB#, RTSB#, CTSB#, CDB#, RIB# TXC, RXC, DTRC#, DSRC#, RTSC#, CTSC#, CDC#, RIC# TXD, RXD, DTRD#, DSRD#, RTSD#, CTSD#, CDD#, RID# XTAL1 XTAL2 554 BLK Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510 668-7000 • FAX 510 668-7017 • XR16M554/554D 1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO FIGURE PIN OUT ASSIGNMENT FOR 68-PIN PLCC PACKAGES IN 16 AND 68 MODE AND 64-PIN LQFP PACKAGES 9 CDA# 8 RIA# 7 RXA 6 GND 5 D7 4 D6 3 D5 2 D4 1 D3 68 D2 67 D1 66 D0 65 INTSEL 64 VCC 63 RXD 62 RID# 63 CDD# 9 CDA# 8 RIA# 7 RXA 6 GND 5 D7 4 D6 3 D5 2 D4 1 D3 68 D2 67 D1 66 D0 65 GND 64 VCC 63 RXD 62 RID# 63 CDD# DSRA# 10 CTSA# 11 DTRA# 12 VCC 13 RTSA# 14 INTA 15 CSA# 16 TXA 17 IOW# 18 1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO ORDERING INFORMATION PACKAGE XR16M554IJ68 XR16M554IV64 XR16M554DIV64 XR16M554IL48 XR16M554IV80 68-Lead PLCC 64-Lead LQFP 64-Lead LQFP 48-pin QFN 80-Lead LQFP OPERATING TEMPERATURE RANGE -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C DEVICE STATUS Active PIN DESCRIPTIONS Pin Description NAME 48-QFN PIN # 64-LQFP PIN # 68-PLCC PIN# 80-LQFP PIN # TYPE DATA BUS INTERFACE I Address data lines These 3 address lines select one of the internal registers in UART channel A-D during a data bus transaction. I/O Data bus lines [7:0] bidirectional . IOR# I When 16/68# pin is HIGH, the Intel bus interface is selected and this input becomes read strobe active low . The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed by the address lines [A2:A0], puts the data byte on the data bus to allow the host processor to read it on the rising edge. When 16/68# pin is LOW, the Motorola bus interface is selected and this input is not used and should be connected to VCC. IOW# R/W# I When 16/68# pin is HIGH, it selects Intel bus interface and this input becomes write strobe active low . The falling edge instigates the internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. When 16/68# pin is LOW, the Motorola bus interface is selected and this input becomes read HIGH and write LOW signal. CSA# I When 16/68# pin is HIGH, this input is chip select A active low to enable channel A in the device. When 16/68# pin is LOW, this input becomes the chip select active low for the Motorola bus interface. ORDERING INFORMATION 4 PRODUCT DESCRIPTION 9 FUNCTIONAL DESCRIPTIONS 10 CPU INTERFACE 10 FIGURE XR16M554 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS 10 DEVICE RESET 11 CHANNEL SELECTION 11 TABLE 1 CHANNEL A-D SELECT IN 16 MODE 11 TABLE 2 CHANNEL A-D SELECT IN 68 MODE 11 CHANNELS A-D INTERNAL REGISTERS 12 INT OUPUTS FOR CHANNELS 12 TABLE 3 INT PIN OPERATION FOR TRANSMITTER FOR CHANNELS A-D 12 TABLE 4 INT PIN OPERATION FOR RECEIVER FOR CHANNELS A-D 12 DMA MODE 12 TABLE 5 TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE FOR CHANNELS A-D 13 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK 13 FIGURE TYPICAL CRYSTAL CONNECTIONS 13 PROGRAMMABLE BAUD RATE 13 FIGURE BAUD RATE GENERATOR 14 TABLE 6 TYPICAL DATA RATES WITH A MHZ CRYSTAL OR EXTERNAL CLOCK 14 TRANSMIT HOLDING REGISTER THR - WRITE 15 TRANSMITTER OPERATION IN NON-FIFO MODE 15 FIGURE TRANSMITTER OPERATION IN NON-FIFO MODE 15 TRANSMITTER OPERATION IN FIFO MODE 15 FIGURE TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE 15 RECEIVER 16 RECEIVE HOLDING REGISTER RHR - READ-ONLY 16 FIGURE RECEIVER OPERATION IN NON-FIFO 16 FIGURE RECEIVER OPERATION IN 17 INTERNAL 18 FIGURE INTERNAL LOOP BACK IN CHANNELS A - D 18 UART INTERNAL 19 TABLE 7 UART CHANNEL A AND B UART INTERNAL REGISTERS 19 TABLE 8 INTERNAL REGISTERS DESCRIPTION. 20 INTERNAL REGISTER DESCRIPTIONS 20 RECEIVE HOLDING REGISTER RHR - READ- ONLY 20 TRANSMIT HOLDING REGISTER THR - WRITE-ONLY 20 INTERRUPT ENABLE REGISTER IER - READ/WRITE 20 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION 21 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE 21 INTERRUPT STATUS REGISTER 22 INTERRUPT GENERATION 22 INTERRUPT CLEARING 22 TABLE 9 INTERRUPT SOURCE AND PRIORITY LEVEL 22 FIFO CONTROL REGISTER FCR - WRITE-ONLY 23 TABLE 10 RECEIVE FIFO TRIGGER LEVEL SELECTION 23 LINE CONTROL REGISTER LCR - READ/WRITE 24 TABLE 11 PARITY SELECTION 25 MODEM CONTROL REGISTER MCR OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE 25 TABLE 12 INT OUTPUT MODES 26 LINE STATUS REGISTER LSR - READ/WRITE 26 MODEM STATUS REGISTER MSR - 27 XR16M554/554D 1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO SCRATCH PAD REGISTER SPR - READ/WRITE 28 BAUD RATE GENERATOR REGISTERS DLL AND DLM - 28 TABLE 13 UART RESET CONDITIONS FOR CHANNELS A-D 29 ABSOLUTE MAXIMUM 30 TYPICAL PACKAGE THERMAL RESISTANCE DATA MARGIN OF ERROR ± 15% 30 ELECTRICAL CHARACTERISTICS 30 DC ELECTRICAL CHARACTERISTICS 30 AC ELECTRICAL CHARACTERISTICS 31 TA = -40O TO +85OC, VCC IS TO 3.63V, 70 PF LOAD WHERE APPLICABLE 31 FIGURE CLOCK 32 FIGURE MODEM INPUT/OUTPUT TIMING FOR CHANNELS A-D 33 FIGURE 16 MODE INTEL DATA BUS READ TIMING FOR CHANNELS 33 FIGURE 16 MODE INTEL DATA BUS WRITE TIMING FOR CHANNELS A-D 34 FIGURE 68 MODE MOTOROLA DATA BUS READ TIMING FOR CHANNELS 34 FIGURE RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D 35 FIGURE 68 MODE MOTOROLA DATA BUS WRITE TIMING FOR CHANNELS A-D 35 FIGURE TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D 36 FIGURE RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS 36 FIGURE RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS 37 FIGURE TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A-D............................... 37 FIGURE TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A-D 38

PDF Datasheet Preview

XR16M554/554D
1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO

MAY 2008

The XR16M554 M554 is a quad Universal Asynchronous Receiver and Transmitter UART with 16 bytes of transmit and receive FIFOs, selectable receive FIFO trigger levels and data rates of up to 4 Mbps at V. Each UART has a set of registers that provide the user with operating status and control, receiver error indications, and modem serial interface controls. An internal loopback capability allows onboard diagnostics. The M554 is available in a 48pin QFN, 64-pin LQFP, 68-pin PLCC and 80-pin LQFP packages. The 64-pin and 80-pin packages only offer the 16 mode interface, but the 48- and 68pin packages offer an additional 68 mode interface which allows easy integration with Motorola processors. The XR16M554IV 64-pin offers three state interrupt output while the XR16M554DIV provides continuous interrupt output. The XR16M554 is compatible with the industry standard ST16C554.
• Pin-to-pin compatible with ST16C454, ST16C554,

TI’s TL16C554A and NXP’s SC16C554B
• Intel or Motorola Data Bus Interface select
• Four independent UART channels
• Register Set Compatible to 16C550
• Data rates of up to 4 Mbps at V,

Mbps at V and 2 Mbps at V
• 16 byte Transmit FIFO
• 16 byte Receive FIFO with error tags
• 4 Selectable RX FIFO Trigger Levels
• Full modem interface
• 1.62V to 3.63V supply operation
• Crystal oscillator or external clock input
• Portable Appliances
• Telecommunication Network Routers
• Ethernet Network Routers
• Cellular Data Devices
• Factory Automation and Process Controls

FIGURE XR16M554 BLOCK DIAGRAM

A2:A0 D7:D0 IOR# IOW# CSA# CSB# CSC# CSD#

INTA INTB INTC INTD TXRDY# A-D RXRDY# A-D Reset 16/68# INTSEL

Data Bus Interface

UART Channel A

UART 16 Byte TX FIFO

Regs

TX & RX

BRG 16 Byte RX FIFO

UART Channel B same as Channel A

UART Channel C same as Channel A

UART Channel D same as Channel A

Crystal Osc / Buffer

V to V VCC GND

TXA, RXA, DTRA#, DSRA#, RTSA#, CTSA#, CDA#, RIA#

TXB, RXB, DTRB#, DSRB#, RTSB#, CTSB#, CDB#, RIB#

TXC, RXC, DTRC#, DSRC#, RTSC#, CTSC#, CDC#, RIC#

TXD, RXD, DTRD#, DSRD#, RTSD#, CTSD#, CDD#, RID#

XTAL1 XTAL2
554 BLK

Exar Corporation 48720 Kato Road, Fremont CA, 94538
• 510 668-7000
• FAX 510 668-7017
•

XR16M554/554D
1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO

FIGURE PIN OUT ASSIGNMENT FOR 68-PIN PLCC PACKAGES IN 16 AND 68 MODE AND 64-PIN LQFP PACKAGES
9 CDA# 8 RIA# 7 RXA 6 GND 5 D7 4 D6 3 D5 2 D4 1 D3 68 D2 67 D1 66 D0 65 INTSEL 64 VCC 63 RXD 62 RID# 63 CDD#
9 CDA# 8 RIA# 7 RXA 6 GND 5 D7 4 D6 3 D5 2 D4 1 D3 68 D2 67 D1 66 D0 65 GND 64 VCC 63 RXD 62 RID# 63 CDD#

DSRA# 10 CTSA# 11 DTRA# 12

VCC 13 RTSA# 14

INTA 15 CSA# 16

TXA 17 IOW# 18
1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO ORDERING INFORMATION

PACKAGE

XR16M554IJ68 XR16M554IV64 XR16M554DIV64 XR16M554IL48 XR16M554IV80
68-Lead PLCC 64-Lead LQFP 64-Lead LQFP
48-pin QFN 80-Lead LQFP

OPERATING TEMPERATURE RANGE
-40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C

DEVICE STATUS

Active

PIN DESCRIPTIONS

Pin Description

NAME
48-QFN PIN #
64-LQFP PIN #
68-PLCC PIN#
80-LQFP PIN #

TYPE

DATA BUS INTERFACE

I Address data lines These 3 address lines select
one of the internal registers in UART channel A-D during a data bus transaction.

I/O Data bus lines [7:0] bidirectional .

IOR#

I When 16/68# pin is HIGH, the Intel bus interface is
selected and this input becomes read strobe active low . The falling edge instigates an internal read cycle
and retrieves the data byte from an internal register
pointed by the address lines [A2:A0], puts the data byte
on the data bus to allow the host processor to read it on
the rising edge.

When 16/68# pin is LOW, the Motorola bus interface is selected and this input is not used and should be connected to VCC.

IOW#

R/W#

I When 16/68# pin is HIGH, it selects Intel bus interface
and this input becomes write strobe active low . The
falling edge instigates the internal write cycle and the
rising edge transfers the data byte on the data bus to
an internal register pointed by the address lines.

When 16/68# pin is LOW, the Motorola bus interface is selected and this input becomes read HIGH and write LOW signal.

CSA#

I When 16/68# pin is HIGH, this input is chip select A
active low to enable channel A in the device.

When 16/68# pin is LOW, this input becomes the chip select active low for the Motorola bus interface.
ORDERING INFORMATION 4 PRODUCT DESCRIPTION 9 FUNCTIONAL DESCRIPTIONS 10

CPU INTERFACE 10

FIGURE XR16M554 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS 10

DEVICE RESET 11 CHANNEL SELECTION 11

TABLE 1 CHANNEL A-D SELECT IN 16 MODE 11 TABLE 2 CHANNEL A-D SELECT IN 68 MODE 11

CHANNELS A-D INTERNAL REGISTERS 12 INT OUPUTS FOR CHANNELS 12

TABLE 3 INT PIN OPERATION FOR TRANSMITTER FOR CHANNELS A-D 12 TABLE 4 INT PIN OPERATION FOR RECEIVER FOR CHANNELS A-D 12

DMA MODE 12

TABLE 5 TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE FOR CHANNELS A-D 13

CRYSTAL OSCILLATOR OR EXTERNAL CLOCK 13

FIGURE TYPICAL CRYSTAL CONNECTIONS 13

PROGRAMMABLE BAUD RATE 13

FIGURE BAUD RATE GENERATOR 14 TABLE 6 TYPICAL DATA RATES WITH A MHZ CRYSTAL OR EXTERNAL CLOCK 14

TRANSMIT HOLDING REGISTER THR - WRITE 15 TRANSMITTER OPERATION IN NON-FIFO MODE 15 FIGURE TRANSMITTER OPERATION IN NON-FIFO MODE 15 TRANSMITTER OPERATION IN FIFO MODE 15 FIGURE TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE 15

RECEIVER 16

RECEIVE HOLDING REGISTER RHR - READ-ONLY 16 FIGURE RECEIVER OPERATION IN NON-FIFO 16 FIGURE RECEIVER OPERATION IN 17

INTERNAL 18

FIGURE INTERNAL LOOP BACK IN CHANNELS A - D 18

UART INTERNAL 19

TABLE 7 UART CHANNEL A AND B UART INTERNAL REGISTERS 19 TABLE 8 INTERNAL REGISTERS DESCRIPTION. 20

INTERNAL REGISTER DESCRIPTIONS 20 RECEIVE HOLDING REGISTER RHR - READ- ONLY 20 TRANSMIT HOLDING REGISTER THR - WRITE-ONLY 20 INTERRUPT ENABLE REGISTER IER - READ/WRITE 20

IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION 21 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE 21

INTERRUPT STATUS REGISTER 22

INTERRUPT GENERATION 22 INTERRUPT CLEARING 22 TABLE 9 INTERRUPT SOURCE AND PRIORITY LEVEL 22

FIFO CONTROL REGISTER FCR - WRITE-ONLY 23

TABLE 10 RECEIVE FIFO TRIGGER LEVEL SELECTION 23

LINE CONTROL REGISTER LCR - READ/WRITE 24

TABLE 11 PARITY SELECTION 25

MODEM CONTROL REGISTER MCR OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE 25

TABLE 12 INT OUTPUT MODES 26

LINE STATUS REGISTER LSR - READ/WRITE 26 MODEM STATUS REGISTER MSR - 27

XR16M554/554D
1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO

SCRATCH PAD REGISTER SPR - READ/WRITE 28 BAUD RATE GENERATOR REGISTERS DLL AND DLM - 28

TABLE 13 UART RESET CONDITIONS FOR CHANNELS A-D 29

ABSOLUTE MAXIMUM 30 TYPICAL PACKAGE THERMAL RESISTANCE DATA MARGIN OF ERROR ± 15% 30 ELECTRICAL CHARACTERISTICS 30

DC ELECTRICAL CHARACTERISTICS 30 AC ELECTRICAL CHARACTERISTICS 31 TA = -40O TO +85OC, VCC IS TO 3.63V, 70 PF LOAD WHERE APPLICABLE 31

FIGURE CLOCK 32 FIGURE MODEM INPUT/OUTPUT TIMING FOR CHANNELS A-D 33 FIGURE 16 MODE INTEL DATA BUS READ TIMING FOR CHANNELS 33 FIGURE 16 MODE INTEL DATA BUS WRITE TIMING FOR CHANNELS A-D 34 FIGURE 68 MODE MOTOROLA DATA BUS READ TIMING FOR CHANNELS 34 FIGURE RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D 35 FIGURE 68 MODE MOTOROLA DATA BUS WRITE TIMING FOR CHANNELS A-D 35 FIGURE TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D 36 FIGURE RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS 36 FIGURE RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS 37 FIGURE TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A-D............................... 37 FIGURE TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A-D 38

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived XR16M554IJ68TR-F Datasheet file may be downloaded here without warranties.

Datasheet ID: XR16M554IJ68TR-F 512920