XR16M2650IM48TR-F

XR16M2650IM48TR-F Datasheet

XR16M2650

Part	Datasheet
XR16M2650IM48TR-F	XR16M2650IM48TR-F (pdf)

Related Parts	Information
XR16M2650IL32TR-F	XR16M2650IL32TR-F

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XR16M2650 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 32-BYTE FIFO MAY 2007 The XR16M26501 M2650 is a high performance dual universal asynchronous receiver and transmitter UART with 32 bytes TX and RX FIFOs. The device operates from to volts and is pin-to-pin and software compatible to the ST16C2550, XR16V2550 and XR16V2650. It supports Exar’s enhanced features of selectable FIFO trigger level, automatic hardware RTS/CTS and software flow control, and a complete modem interface. Onboard registers provide the user with operational status and data error flags. An internal loopback capability allows system diagnostics. Independent programmable baud rate generators are provided in each channel to select data rates up to 16 Mbps at Volt with 4X sampling clock. The M2650 is available in 48-pin TQFP and 32-pin QFN packages. NOTE 1 Covered by U.S. Patent #5,649,122 • Portable Appliances • Telecommunication Network Routers • Ethernet Network Routers • Cellular Data Devices • Factory Automation and Process Controls • to Volt Operation • Pin-to-pin and software compatible to ST16C2550 in the 48-TQFP package • Pin-to-pin and software compatible to XR16L2550, XR16V2550 and XR16V2650 • Two independent UART channels • Register set is 16550 compatible • Data rate of up to 16 Mbps at V • Data rate of up to Mbps at V • Data rate of up to 8 Mbps at 1.8V • Fractional Baud Rate Generator • Transmit and Receive FIFOs of 32 bytes • Selectable TX and RX FIFO Trigger Levels • Automatic Hardware RTS/CTS Flow Control • Automatic Software Xon/Xoff Flow Control • Wireless Infrared IrDA Encoder/Decoder • Automatic sleep mode • Full modem interface up to 64MHz input • 48-TQFP and 32-QFN packages FIGURE XR16M2650 BLOCK DIAGRAM A2:A0 D7:D0 IOR# IOW# CSA# CSB# INTA INTB TXRDYA# TXRDYB# RXRDYA# RXRDYB# Reset 8-bit Data Bus Interface UART Channel A UART 32 Byte TX FIFO Regs TX & RX IR ENDEC BRG 32 Byte RX FIFO UART Channel B same as Channel A Crystal Osc/Buffer to Volt VCC TXA, RXA, DTRA#, DSRA#, RTSA#, CTSA#, CDA#, RIA#, OP2A# TXB, RXB, DTRB#, DSRB#, RTSB#, CTSB#, CDB#, RIB#, OP2B# XTAL1 XTAL2 Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510 668-7000 • FAX 510 668-7017 • XR16M2650 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 32-BYTE FIFO FIGURE PIN OUT ASSIGNMENT 48 D4 47 D3 46 D2 45 D1 44 D0 43 TXRDYA# 42 VCC 41 RIA# 40 CDA# 39 DSRA# 38 CTSA# 37 NC D5 1 D6 2 D7 3 RXB 4 RXA 5 TXRDYB# 6 TXA 7 TXB 8 OP2B# 9 CSA# 10 CSB# 11 ORDERING INFORMATION PART NUMBER XR16M2650IL32 XR16M2650IM48 PACKAGE 32-Pin QFN 48-Lead TQFP OPERATING TEMPERATURE RANGE -40°C to +85°C -40°C to +85°C DEVICE STATUS Active PIN DESCRIPTIONS XR16M2650 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 32-BYTE FIFO Pin Description NAME 32-QFN PIN # 48-TQFP PIN # TYPE DATA BUS INTERFACE IOR# IOW# CSA# CSB# INTA INTB TXRDYA# RXRDYA# TXRDYB# I Address data lines These 3 address lines select one of the internal registers in UART channel A/B during a data bus transaction. I/O Data bus lines [7:0] bidirectional . I Input/Output Read Strobe active low . The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed to by the address lines [A2:A0]. The data byte is placed on the data bus to allow the host processor to read it on the rising edge. I Input/Output Write Strobe active low . The falling edge instigates an internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. I UART channel A select active low to enable UART channel A in the device for data bus operation. I UART channel B select active low to enable UART channel B in the device for data bus operation. O UART channel A Interrupt output. The output state is defined by the user through the software setting of MCR[3]. INTA is set to the active mode and OP2A# output LOW when MCR[3] is set to HIGH. INTA is set to the three state mode and OP2A# output HIGH when MCR[3] is set to LOW default . See MCR[3]. O UART channel B Interrupt output. The output state is defined by the user through the software setting of MCR[3]. INTB is set to the active mode and OP2B# output LOW when MCR[3] is set to HIGH. INTB is set to the three state mode and OP2B# output HIGH when MCR[3] is set to LOW default . See MCR[3]. O UART channel A Transmitter Ready active low . The output provides the TX FIFO/THR status for transmit channel A. See Table If it is not used, leave it unconnected. O UART channel A Receiver Ready active low . This output provides the RX FIFO/RHR status for receive channel A. See Table If it is not used, leave it unconnected. O UART channel B Transmitter Ready active low . The output provides the TX FIFO/THR status for transmit channel B. See Table If it is not used, leave it unconnected. XR16M2650 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 32-BYTE FIFO Pin Description NAME RXRDYB# 32-QFN PIN # 48-TQFP PIN # TYPE O UART channel B Receiver Ready active low . This output provides the RX FIFO/RHR status for receive channel B. See Table If it is not used, leave it unconnected. ORDERING 2 PIN DESCRIPTIONS 3 PRODUCT 6 FUNCTIONAL 7 CPU 7 FIGURE XR16M2650 DATA BUS INTERCONNECTIONS 7 DEVICE RESET 7 DEVICE IDENTIFICATION AND 7 CHANNEL A AND B 7 TABLE 1 CHANNEL A AND B SELECT 8 CHANNEL A AND B INTERNAL REGISTERS 8 DMA 8 TABLE 2 TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE 8 INTA AND INTB OUTPUTS 9 TABLE 3 INTA AND INTB PINS OPERATION FOR TRANSMITTER 9 TABLE 4 INTA AND INTB PINS OPERATION FOR RECEIVER 9 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT 9 FIGURE TYPICAL CRYSTAL CONNECTIONS 9 PROGRAMMABLE BAUD RATE GENERATOR WITH FRACTIONAL 10 FIGURE BAUD RATE GENERATOR 11 TABLE 5 TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING 11 TRANSMITTER 12 TRANSMIT HOLDING REGISTER THR - WRITE ONLY 12 TRANSMITTER OPERATION IN NON-FIFO MODE 12 FIGURE TRANSMITTER OPERATION IN NON-FIFO MODE 12 TRANSMITTER OPERATION IN FIFO MODE 12 FIGURE TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE 13 RECEIVER 13 RECEIVE HOLDING REGISTER RHR - READ-ONLY 13 FIGURE RECEIVER OPERATION IN NON-FIFO MODE 14 FIGURE RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE 14 AUTO RTS HARDWARE FLOW CONTROL 15 AUTO RTS 15 TABLE 6 AUTO RTS HARDWARE FLOW CONTROL 15 AUTO CTS FLOW CONTROL 15 FIGURE AUTO RTS AND CTS FLOW CONTROL 16 AUTO XON/XOFF SOFTWARE FLOW 17 TABLE 7 AUTO XON/XOFF SOFTWARE FLOW CONTROL 17 SPECIAL CHARACTER DETECT 17 INFRARED MODE 18 FIGURE INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING 18 SLEEP MODE WITH AUTO 19 INTERNAL LOOPBACK 20 FIGURE INTERNAL LOOP BACK IN CHANNEL A AND B 20 UART INTERNAL REGISTERS 21 TABLE 8 UART CHANNEL A AND B UART INTERNAL REGISTERS 21 TABLE 9 INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1 22 INTERNAL REGISTER 23 RECEIVE HOLDING REGISTER RHR - READ- ONLY 23 TRANSMIT HOLDING REGISTER THR - WRITE-ONLY 23 INTERRUPT ENABLE REGISTER IER - 23 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION 23 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION 23 INTERRUPT STATUS REGISTER ISR - READ-ONLY 25 XR16M2650 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 32-BYTE FIFO INTERRUPT GENERATION 25 INTERRUPT CLEARING 25 TABLE 10 INTERRUPT SOURCE AND PRIORITY LEVEL 25 FIFO CONTROL REGISTER FCR - WRITE-ONLY 26 TABLE 11 TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION 27 LINE CONTROL REGISTER LCR - READ/WRITE 27 TABLE 12 PARITY SELECTION 28

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XR16M2650

HIGH PERFORMANCE LOW VOLTAGE DUART WITH 32-BYTE FIFO

MAY 2007

The XR16M26501 M2650 is a high performance dual universal asynchronous receiver and transmitter UART with 32 bytes TX and RX FIFOs. The device operates from to volts and is pin-to-pin and software compatible to the ST16C2550, XR16V2550 and XR16V2650. It supports Exar’s enhanced features of selectable FIFO trigger level, automatic hardware RTS/CTS and software flow control, and a complete modem interface. Onboard registers provide the user with operational status and data error flags. An internal loopback capability allows system diagnostics. Independent programmable baud rate generators are provided in each channel to select data rates up to 16 Mbps at Volt with 4X sampling clock. The M2650 is available in 48-pin TQFP and 32-pin QFN packages.

NOTE 1 Covered by U.S. Patent #5,649,122
• Portable Appliances
• Telecommunication Network Routers
• Ethernet Network Routers
• Cellular Data Devices
• Factory Automation and Process Controls
• to Volt Operation
• Pin-to-pin and software compatible to ST16C2550
in the 48-TQFP package
• Pin-to-pin and software compatible to XR16L2550,

XR16V2550 and XR16V2650
• Two independent UART channels
• Register set is 16550 compatible
• Data rate of up to 16 Mbps at V
• Data rate of up to Mbps at V
• Data rate of up to 8 Mbps at 1.8V
• Fractional Baud Rate Generator
• Transmit and Receive FIFOs of 32 bytes
• Selectable TX and RX FIFO Trigger Levels
• Automatic Hardware RTS/CTS Flow Control
• Automatic Software Xon/Xoff Flow Control
• Wireless Infrared IrDA Encoder/Decoder
• Automatic sleep mode
• Full modem interface
up to 64MHz input
• 48-TQFP and 32-QFN packages

FIGURE XR16M2650 BLOCK DIAGRAM

A2:A0 D7:D0 IOR# IOW# CSA# CSB# INTA INTB TXRDYA# TXRDYB# RXRDYA# RXRDYB#

Reset
8-bit Data Bus

Interface

UART Channel A

UART 32 Byte TX FIFO

Regs

TX & RX

IR ENDEC

BRG 32 Byte RX FIFO

UART Channel B same as Channel A

Crystal Osc/Buffer
to Volt VCC

TXA, RXA, DTRA#, DSRA#, RTSA#, CTSA#, CDA#, RIA#, OP2A#

TXB, RXB, DTRB#, DSRB#, RTSB#, CTSB#, CDB#, RIB#, OP2B#

XTAL1 XTAL2

Exar Corporation 48720 Kato Road, Fremont CA, 94538
• 510 668-7000
• FAX 510 668-7017
•

XR16M2650

HIGH PERFORMANCE LOW VOLTAGE DUART WITH 32-BYTE FIFO

FIGURE PIN OUT ASSIGNMENT
48 D4 47 D3 46 D2 45 D1 44 D0 43 TXRDYA# 42 VCC 41 RIA# 40 CDA# 39 DSRA# 38 CTSA# 37 NC

D5 1 D6 2 D7 3 RXB 4 RXA 5 TXRDYB# 6 TXA 7 TXB 8 OP2B# 9 CSA# 10 CSB# 11
ORDERING INFORMATION

PART NUMBER XR16M2650IL32 XR16M2650IM48

PACKAGE 32-Pin QFN 48-Lead TQFP

OPERATING TEMPERATURE RANGE -40°C to +85°C -40°C to +85°C

DEVICE STATUS Active

PIN DESCRIPTIONS

XR16M2650

HIGH PERFORMANCE LOW VOLTAGE DUART WITH 32-BYTE FIFO

Pin Description

NAME
32-QFN PIN #
48-TQFP PIN #

TYPE

DATA BUS INTERFACE

IOR#

IOW#

CSA#

CSB#

INTA

INTB

TXRDYA#

RXRDYA#

TXRDYB#

I Address data lines These 3 address lines select one of the internal registers in UART channel A/B during a data bus transaction.

I/O Data bus lines [7:0] bidirectional .

I Input/Output Read Strobe active low . The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed to by the address lines [A2:A0]. The data byte is placed on the data bus to allow the host processor to read it on the rising edge.

I Input/Output Write Strobe active low . The falling edge instigates an internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines.

I UART channel A select active low to enable UART channel A in the device for data bus operation.

I UART channel B select active low to enable UART channel B in the device for data bus operation.

O UART channel A Interrupt output. The output state is defined by the user through the software setting of MCR[3]. INTA is set to the active mode and OP2A# output LOW when MCR[3] is set to HIGH. INTA is set to the three state mode and OP2A# output HIGH when MCR[3] is set to LOW default . See MCR[3].

O UART channel B Interrupt output. The output state is defined by the user through the software setting of MCR[3]. INTB is set to the active mode and OP2B# output LOW when MCR[3] is set to HIGH. INTB is set to the three state mode and OP2B# output HIGH when MCR[3] is set to LOW default . See MCR[3].

O UART channel A Transmitter Ready active low . The output provides the TX FIFO/THR status for transmit channel A. See Table If it is not used, leave it unconnected.

O UART channel A Receiver Ready active low . This output provides the RX FIFO/RHR status for receive channel A. See Table If it is not used, leave it unconnected.

O UART channel B Transmitter Ready active low . The output provides the TX FIFO/THR status for transmit channel B. See Table If it is not used, leave it unconnected.

XR16M2650

HIGH PERFORMANCE LOW VOLTAGE DUART WITH 32-BYTE FIFO Pin Description

NAME RXRDYB#
32-QFN PIN #
48-TQFP PIN #

TYPE

O UART channel B Receiver Ready active low . This output provides the RX FIFO/RHR status for receive channel B. See Table If it is not used, leave it unconnected.
ORDERING 2

PIN DESCRIPTIONS 3

PRODUCT 6 FUNCTIONAL 7

CPU 7

FIGURE XR16M2650 DATA BUS INTERCONNECTIONS 7

DEVICE RESET 7 DEVICE IDENTIFICATION AND 7 CHANNEL A AND B 7

TABLE 1 CHANNEL A AND B SELECT 8

CHANNEL A AND B INTERNAL REGISTERS 8 DMA 8

TABLE 2 TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE 8

INTA AND INTB OUTPUTS 9

TABLE 3 INTA AND INTB PINS OPERATION FOR TRANSMITTER 9 TABLE 4 INTA AND INTB PINS OPERATION FOR RECEIVER 9

CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT 9

FIGURE TYPICAL CRYSTAL CONNECTIONS 9

PROGRAMMABLE BAUD RATE GENERATOR WITH FRACTIONAL 10

FIGURE BAUD RATE GENERATOR 11 TABLE 5 TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING 11

TRANSMITTER 12

TRANSMIT HOLDING REGISTER THR - WRITE ONLY 12 TRANSMITTER OPERATION IN NON-FIFO MODE 12 FIGURE TRANSMITTER OPERATION IN NON-FIFO MODE 12 TRANSMITTER OPERATION IN FIFO MODE 12 FIGURE TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE 13

RECEIVER 13

RECEIVE HOLDING REGISTER RHR - READ-ONLY 13 FIGURE RECEIVER OPERATION IN NON-FIFO MODE 14 FIGURE RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE 14

AUTO RTS HARDWARE FLOW CONTROL 15 AUTO RTS 15

TABLE 6 AUTO RTS HARDWARE FLOW CONTROL 15

AUTO CTS FLOW CONTROL 15

FIGURE AUTO RTS AND CTS FLOW CONTROL 16

AUTO XON/XOFF SOFTWARE FLOW 17

TABLE 7 AUTO XON/XOFF SOFTWARE FLOW CONTROL 17

SPECIAL CHARACTER DETECT 17 INFRARED MODE 18

FIGURE INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING 18

SLEEP MODE WITH AUTO 19 INTERNAL LOOPBACK 20

FIGURE INTERNAL LOOP BACK IN CHANNEL A AND B 20

UART INTERNAL REGISTERS 21

TABLE 8 UART CHANNEL A AND B UART INTERNAL REGISTERS 21 TABLE 9 INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1 22

INTERNAL REGISTER 23 RECEIVE HOLDING REGISTER RHR - READ- ONLY 23 TRANSMIT HOLDING REGISTER THR - WRITE-ONLY 23 INTERRUPT ENABLE REGISTER IER - 23

IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION 23 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION 23

INTERRUPT STATUS REGISTER ISR - READ-ONLY 25

XR16M2650

HIGH PERFORMANCE LOW VOLTAGE DUART WITH 32-BYTE FIFO

INTERRUPT GENERATION 25 INTERRUPT CLEARING 25 TABLE 10 INTERRUPT SOURCE AND PRIORITY LEVEL 25

FIFO CONTROL REGISTER FCR - WRITE-ONLY 26

TABLE 11 TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION 27

LINE CONTROL REGISTER LCR - READ/WRITE 27

TABLE 12 PARITY SELECTION 28

More datasheets: CT31031N002 | CT41001N020 | CT31021N000 | CT37031N022 | CT33001N000 | CT37031N002 | 44256 | 4816P-T01-824 | 240-075 | XR16M2650IL32TR-F

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Datasheet ID: XR16M2650IM48TR-F 512918