ST16C1450CQ48-F

ST16C1450CQ48-F Datasheet


The ST16C1450 is a universal asynchronous receiver and transmitter UART . The 1450 is foot print compatible to the SSI 73M1550 and SSI 73M2550 UART with one byte FIFO and higher operating speed and lower access time. The 1450 provides enhanced UART functions with a modem control interface, independent programmable baud rate generators with clock rates to Mbps. On board status registers provide the user with error indications and operational status. System interrupts and modem control features may be tailored by external software to meet specific user requirements. An internal loop-back capability allows on board diagnostics. The 1450 is available in a 28-pin PLCC and 48-pin TQFP packages. The baud rate generator can be configured for either crystal or external clock input. The 48-pin TQFP package provides a buffered reset output that can be controlled through user software. The 1450 is fabricated in an advanced CMOS process to achieve low drain power and high speed requirements. The ST16C1450 is not compatible with the industry standard 16450 and will not work with the standard serial port driver in MS Windows see pages 12-13 for details . For a MS Windows compatible UART, see the ST16C450.

Part Datasheet
ST16C1450CQ48-F ST16C1450CQ48-F ST16C1450CQ48-F (pdf)
Related Parts Information
ST16C1450CJ28TR-F ST16C1450CJ28TR-F ST16C1450CJ28TR-F
ST16C1450IQ48-F ST16C1450IQ48-F ST16C1450IQ48-F
ST16C1450CJ28-F ST16C1450CJ28-F ST16C1450CJ28-F
ST16C1450IJ28-F ST16C1450IJ28-F ST16C1450IJ28-F
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AUGUST 2005

The ST16C1450 is a universal asynchronous receiver and transmitter UART . The 1450 is foot print compatible to the SSI 73M1550 and SSI 73M2550 UART with one byte FIFO and higher operating speed and lower access time. The 1450 provides enhanced UART functions with a modem control interface, independent programmable baud rate generators with clock rates to Mbps. On board status registers provide the user with error indications and operational status. System interrupts and modem control features may be tailored by external software to meet specific user requirements. An internal loop-back capability allows on board diagnostics. The 1450 is available in a 28-pin PLCC and 48-pin TQFP packages. The baud rate generator can be configured for either crystal or external clock input. The 48-pin TQFP package provides a buffered reset output that can be controlled through user software. The 1450 is fabricated in an advanced CMOS process to achieve low drain power and high speed requirements. The ST16C1450 is not compatible with the industry standard 16450 and will not work with the standard serial port driver in MS Windows see pages 12-13 for details . For a MS Windows compatible UART, see the ST16C450.

ST16C1450
2.97V TO 5.5V UART
• Pin and functionally compatible to SSI 73M1550/
2550
• 1 byte Transmit FIFO THR
• 1 byte Receive FIFO with error tags RHR
• Four levels of prioritized interrupts
• Modem Control Signals CTS#, RTS#, DSR#,

DTR#, RI#, CD#
• Programmable character lengths 5, 6, 7, 8 with
even, odd or no parity
• Crystal or external clock input
• Mbps Transmit/Receive operation 24 MHz
with programmable clock control
• Power Down Mode 50 uA at V, 200 uA at 5 V
• Software controllable reset output
• to Volt operation
• Battery Operated Electronics
• Internet Appliances
• Handheld Terminal
• Personal Digital Assistants
• Cellular Phones DataPort

FIGURE BLOCK DIAGRAM

A2:A0 D7:D0 IOR# IO W # CS#

RESET RST

Data Bus Interface

THR T ra n s m itte r

UART Configuration

Regs

M odem Control Signals

Receiver RHR

Baud Rate Generator Crystal Osc/Buffer

DTR#, RTS# DSR#, CTS#, CD#, RI# RX

X T A L 1 /C L K XTAL2

Exar Corporation 48720 Kato Road, Fremont CA, 94538
• 510 668-7000
• FAX 510 668-7017


ST16C1450 2.97V TO 5.5V UART FIGURE ST16C1450 PINOUTS
48-TQFP PACKAGE
48 N.C. 47 D3 46 D2 45 D1 44 N.C. 43 D0 42 N.C. 41 VCC 40 CD# 39 DSR# 38 N.C. 37 N.C.

N.C. 1 N.C. 2

D4 3 D5 4 D6 5 D7 6 RX 7 TX 8 CS# 9 N.C. 10 N.C. 11 N.C. 12

ST16C1450CQ48
36 N.C. 35 N.C. 34 CTS# 33 RESET 32 DTR# 31 RTS# 30 A0 29 N.C. 28 A1 27 A2 26 N.C. 25 N.C.

NOTE PINOUTS NOT TO SCALE.

ACTUAL SIZE OF TQFP PACKAGE

IS SMALLER THAN PLCC PACKAGE.
28-PLCC PACKAGES

N.C. 13 N.C. 14 XTAL1 15 XTAL2 16 IOW# 17 N.C. 18 GND 19 IOR# 20 RI# 21 RST 22 INT 23 N.C. 24
4 D3 3 D2 2 D1 1 D0 28 VCC 27 CD# 26 DSR#

D4 5 D5 6 D6 7 D7 8 RX 9 TX 10 CS# 11
ORDERING INFORMATION

PACKAGE

OPERATING TEMPERATURE

RANGE

ST16C1450CJ28 28-Lead PLCC 0°C to +70°C

ST16C1450CQ48 48-Lead TQFP 0°C to +70°C

ST16C1450IJ28 28-Lead PLCC -40°C to +85°C

ST16C1450IQ48 48-Lead TQFP -40°C to +85°C

DEVICE STATUS

Active

PIN DESCRIPTIONS

ST16C1450 2.97V TO 5.5V UART

NAME
28-PIN PLCC
48-PIN TQFP

TYPE

DATA BUS INTERFACE

I Address data lines A2:A0 selects internal UART’s configuration registers.
43 I/O Data bus lines [7:0] bidirectional . 45 46 47 3 4 5 6

IOR# 16

I Input/Output Read active low . The falling edge instigates an internal read cycle and
retrieves the data byte from an internal register pointed by the address lines [A2:A0],
places it on the data bus to allow the host processor to read it on the leading edge.

IOW# 14

I Input/Output Write active low . The falling edge instigates the internal write cycle and
the rising edge transfers the data byte on the data bus to an internal register pointed by
the address lines [A2:A0].

CS# 11

I Chip Select input active low . A logic 0 on this pin selects the ST16C1450 device.

O Interrupt Output three-state, active high . INT output defaults to three-state mode and
becomes active high when MCR bit-3 is set to a logic INT output becomes a logic
high level when interrupts are enabled in the interrupt enable register IER , and
whenever the transmitter, receiver, line and/or modem status register has an active
condition.

MODEM OR SERIAL I/O INTERFACE

O Transmit Data. This output is associated with individual serial transmit channel data
from the TX signal will be a logic 1 during reset, idle no data , or when the
transmitter is disabled. During the local loopback mode, the TX output pin is disabled
and TX data is internally connected to the UART RX input.

I Receive Data. This input is associated with individual serial channel data to the

Normal received data input idles at logic 1 condition. This input must be connected to
Updated Ordering Information.
Added Status Column to Ordering Information.

Clarified compatibility to industry standard 16450 and MS Windows standard serial port driver in General Description. Removed Auto RTS flow control from MCR bit-1 description since that feature is not available in this device.
Removed discontinued ST16C1451 and discontinued packages of ST16C1450 from Ordering Information.

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that a the risk of injury or damage has been minimized b the user assumes all such risks c potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2005 EXAR Corporation Datasheet August Send your UART technical inquiry with technical details to hotline Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

TABLE OF CONTENTS

ST16C1450/51 2.97V TO 5.5VUART

GENERAL 1

FEATURES 1 APPLICATIONS 1

FIGURE BLOCK DIAGRAM 1 FIGURE ST16C1450 PINOUTS 2
ORDERING INFORMATION 2

PIN DESCRIPTIONS 3

DATA BUS INTERFACE 3 MODEM OR SERIAL I/O INTERFACE 3 PRODUCT DESCRIPTION 4 ANCILLARY SIGNALS 4 FUNCTIONAL DESCRIPTIONS 5 INTERNAL REGISTERS 5 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK 5

FIGURE TYPICAL OSCILLATOR 5

PROGRAMMABLE BAUD RATE GENERATOR 5

TABLE 1 TYPICAL DATA RATES WITH A MHZ CRYSTAL OR EXTERNAL CLOCK 6

TRANSMITTER 6

TRANSMIT HOLDING REGISTER THR - WRITE 6 TRANSMITTER 6 FIGURE TRANSMITTER OPERATION 7

RECEIVER 7

RECEIVE HOLDING REGISTER RHR - READ-ONLY 7 FIGURE RECEIVER OPERATION IN NON-FIFO 8

SPECIAL ENHANCED FEATURE MODE 8

SOFT RESET 8 POWER DOWN MODE 8

INTERNAL LOOPBACK 8

FIGURE INTERNAL 9

UART INTERNAL REGISTERS 10

TABLE 2 ST16C1450 UART INTERNAL 10 TABLE 3 INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR 11

INTERNAL REGISTER DESCRIPTIONS 12 RECEIVE HOLDING REGISTER RHR - READ- ONLY 12 TRANSMIT HOLDING REGISTER THR - WRITE-ONLY 12 INTERRUPT ENABLE REGISTER IER - READ/WRITE 12 INTERRUPT STATUS REGISTER ISR - READ-ONLY 12

INTERRUPT GENERATION 13 INTERRUPT CLEARING 13 TABLE 4 INTERRUPT SOURCE AND PRIORITY LEVEL 13

LINE CONTROL REGISTER LCR - READ/WRITE 13

TABLE 5 PARITY SELECTION 14

MODEM CONTROL REGISTER MCR OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE 15 LINE STATUS REGISTER LSR - READ ONLY 16 MODEM STATUS REGISTER MSR - READ ONLY 16 SCRATCH PAD REGISTER SPR - READ/WRITE 17

TABLE 6 UART RESET CONDITIONS 18

ABSOLUTE MAXIMUM RATINGS 19

TYPICAL PACKAGE THERMAL RESISTANCE DATA MARGIN OF ERROR ± 15% 19

ELECTRICAL 19

DC ELECTRICAL 19 AC ELECTRICAL 20 TA=0O TO 70OC -40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE , VCC IS 2.97V TO 5.5V...................... 20

FIGURE CLOCK 21 FIGURE MODEM INPUT/OUTPUT TIMING 21 FIGURE DATA BUS READ 22 FIGURE DATA BUS WRITE TIMING 22 FIGURE RECEIVE READY & INTERRUPT TIMING 23

ST16C1450/51 2.97V TO 5.5VUART

FIGURE TRANSMIT READY & INTERRUPT TIMING 23

TABLE OF CONTENTS
More datasheets: 1.15116.0210000 | 1.15116.0310000 | 1.15116.0110000 | 76000824 | FS2009(AVR-JTAG) | M5432 SL002 | M5432 SL001 | M5432 SL005 | ST16C1450CJ28TR-F | ST16C1450IQ48-F


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Datasheet ID: ST16C1450CQ48-F 512917