CDK1308AILP40

CDK1308AILP40 Datasheet

CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit ADCs Rev 1B

Part	Datasheet
CDK1308AILP40	CDK1308AILP40 (pdf)

Related Parts	Information
CDK1308DILP40	CDK1308DILP40
CDK1308CILP40	CDK1308CILP40
CDK1308BILP40	CDK1308BILP40

PDF Datasheet Preview
Data Sheet CDK1308 Ultra Low Power, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters ADCs FEATURES n 10-bit resolution n 20/40/65/80MSPS max sampling rate n Ultra-Low Power Dissipation: 15/25/38/46mW n 61.6dB SNR at 80MSPS and 8MHz FIN n Internal reference circuitry n 1.8V core supply voltage n 3.6V I/O supply voltage n Parallel CMOS output n 40-pin QFN package n Pin compatible with CDK1307 APPLICATIONS n Medical Imaging n Portable Test Equipment n Digital Oscilloscopes n IF Communication n Video Conferencing n Video Distribution The CDK1308 is a high performance ultra low power analog-to-digital converter ADC . The ADC employs internal reference circuitry, a CMOS control interface and CMOS output data, and is based on a proprietary structure. Digital error correction is employed to ensure no missing codes in the complete full scale range. Two idle modes with fast startup times exist. The entire chip can either be put in Standby Mode or Power Down mode. The two modes are optimized to allow the user to select the mode resulting in the smallest possible energy consumption during idle mode and startup. The CDK1308 has a highly linear THA optimized for frequencies up to Nyquist. The differential clock interface is optimized for low jitter clock sources and supports LVDS, LVPECL, sine wave, and CMOS clock inputs. Functional Block Diagram Ordering Information Speed Package CDK1308AILP40 20MSPS QFN-40 CDK1308BILP40 40MSPS QFN-40 CDK1308CILP40 65MSPS QFN-40 CDK1308DILP40 80MSPS QFN-40 Moisture sensitivity level for all parts is MSL-2A. Pb-Free Yes RoHS Compliant Yes Operating Temperature Range -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C Packaging Method Tray Exar Corporation 48720 Kato Road, Fremont CA 94538, USA Tel. +1 510 668-7000 - Fax. +1 510 668-7001 40 SLP_N 39 CM_EXTBC_0 38 CM_EXTBC_1 37 OVDD 36 OVDD 35 D_9 34 D_8 33 D_7 32 D_6 31 D_5 Data Sheet Pin Configuration QFN-40 DVDD 1 CM_EXT 2 AVDD 3 AVDD 4 IP 5 IN 6 AVDD 7 DVDDCLK 8 CLKP 9 CLKN 10 CDK1308 QFN-40 30 D_4 29 D_3 28 D_2 27 CLK_EXT 26 OVDD 25 OVDD 24 ORNG 23 D_1 22 D_0 21 NC DVDD 11 CLK_EXT_EN 12 DFRMT 13 PD_N 14 OE_N 15 DVDD 16 OVDD 17 OVDD 18 NC 19 NC 20 Pin Assignments Pin No. 0 1, 11, 16 2 3, 4, 7 5, 6 8 9 10 12 13 14 15 17, 18, 25, 26, 36, 37 19 20 21 22 Pin Name VSS DVDD CM_EXT AVDD IP, IN DVDDCLK CLKP CLKN CLK_EXT_EN DFRMT PD_N OE_N OVDD Description Ground connection for all power domains. Exposed pad Digital and I/O-ring pre driver supply voltage, 1.8V Common Mode voltage output Analog supply voltage, 1.8V Analog input non-inverting, inverting Clock circuitry supply voltage, 1.8V Clock input, non-inverting format LVDS, LVPECL, CMOS/TTL, Sine Wave Clock input, inverting. For CMOS input on CLKP, connect CLKN to ground CLK_EXT signal enabled when low zero . Tristate when high. Data format selection. 0 Offset Binary, 1 Two's Complement Full chip Power Down mode when Low. All digital outputs reset to zero. After chip power up always apply Power Down mode before using Active Mode to reset chip. Output Enable. Tristate when high I/O ring post-driver supply voltage. Voltage range to 3.6V Output Data LSB

PDF Datasheet Preview

Data Sheet

CDK1308

Ultra Low Power, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters ADCs

FEATURES n 10-bit resolution n 20/40/65/80MSPS max sampling rate n Ultra-Low Power Dissipation:
15/25/38/46mW n 61.6dB SNR at 80MSPS and 8MHz FIN n Internal reference circuitry n 1.8V core supply voltage n 3.6V I/O supply voltage n Parallel CMOS output n 40-pin QFN package n Pin compatible with CDK1307

APPLICATIONS n Medical Imaging n Portable Test Equipment n Digital Oscilloscopes n IF Communication n Video Conferencing n Video Distribution

The CDK1308 is a high performance ultra low power analog-to-digital converter ADC . The ADC employs internal reference circuitry, a CMOS control interface and CMOS output data, and is based on a proprietary structure. Digital error correction is employed to ensure no missing codes in the complete full scale range.

Two idle modes with fast startup times exist. The entire chip can either be put in Standby Mode or Power Down mode. The two modes are optimized to allow the user to select the mode resulting in the smallest possible energy consumption during idle mode and startup.

The CDK1308 has a highly linear THA optimized for frequencies up to Nyquist. The differential clock interface is optimized for low jitter clock sources and supports LVDS, LVPECL, sine wave, and CMOS clock inputs.

Functional Block Diagram
Ordering Information

Speed Package

CDK1308AILP40
20MSPS QFN-40

CDK1308BILP40
40MSPS QFN-40

CDK1308CILP40
65MSPS QFN-40

CDK1308DILP40
80MSPS QFN-40

Moisture sensitivity level for all parts is MSL-2A.

Pb-Free Yes

RoHS Compliant Yes

Operating Temperature Range -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C

Packaging Method Tray

Exar Corporation 48720 Kato Road, Fremont CA 94538, USA

Tel. +1 510 668-7000 - Fax. +1 510 668-7001
40 SLP_N 39 CM_EXTBC_0 38 CM_EXTBC_1 37 OVDD 36 OVDD 35 D_9 34 D_8 33 D_7 32 D_6 31 D_5

Data Sheet

Pin Configuration QFN-40

DVDD 1 CM_EXT 2

AVDD 3 AVDD 4

IP 5 IN 6 AVDD 7 DVDDCLK 8 CLKP 9 CLKN 10

CDK1308

QFN-40
30 D_4 29 D_3 28 D_2 27 CLK_EXT 26 OVDD 25 OVDD 24 ORNG 23 D_1 22 D_0 21 NC

DVDD 11 CLK_EXT_EN 12

DFRMT 13 PD_N 14 OE_N 15 DVDD 16 OVDD 17 OVDD 18 NC 19 NC 20

Pin Assignments

Pin No. 0
1, 11, 16 2
3, 4, 7 5, 6 8 9 10 12 13 14
15 17, 18, 25, 26, 36, 37
19 20 21 22

Pin Name VSS DVDD

CM_EXT AVDD IP, IN

DVDDCLK CLKP CLKN

CLK_EXT_EN DFRMT PD_N

OE_N OVDD

Description Ground connection for all power domains. Exposed pad Digital and I/O-ring pre driver supply voltage, 1.8V Common Mode voltage output Analog supply voltage, 1.8V Analog input non-inverting, inverting Clock circuitry supply voltage, 1.8V Clock input, non-inverting format LVDS, LVPECL, CMOS/TTL, Sine Wave Clock input, inverting. For CMOS input on CLKP, connect CLKN to ground CLK_EXT signal enabled when low zero . Tristate when high. Data format selection. 0 Offset Binary, 1 Two's Complement Full chip Power Down mode when Low. All digital outputs reset to zero. After chip power up always apply Power Down mode before using Active Mode to reset chip. Output Enable. Tristate when high I/O ring post-driver supply voltage. Voltage range to 3.6V

Output Data LSB

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Datasheet ID: CDK1308AILP40 512891