S2D13515F00A100

S2D13515F00A100 Datasheet

S1D13515 / S2D13515 Display Controller

Part	Datasheet
S2D13515F00A100	S2D13515F00A100 (pdf)

Related Parts	Information
S1D13515F00A100	S1D13515F00A100
S1D13515B00B100	S1D13515B00B100
S2D13515B00B100	S2D13515B00B100

PDF Datasheet Preview
S1D13515 / S2D13515 Display Controller Hardware Functional Specification SEIKO EPSON CORPORATION NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. All other product names mentioned herein are trademarks and/or registered trademarks of their respective companies. SEIKO EPSON CORPORATION 2006 - 2011, All rights reserved. S1D13515/S2D13515 Table Of Contents Chapter 1 Introduction 11 Scope 11 Overview Description 11 Chapter 2 Features 12 Memory 12 CPU Interfaces 12 Panel Interface Support 13 Display Features 14 Embedded CPU 14 Sprite Engine 15 Video / Camera Input 15 Clock Source 15 Miscellaneous 16 Chapter 3 Typical Implementation Use Cases 17 Use Case 1 - Heads-Up Display HUD with LCD Panel 17 Use Case 2 - Dual-View Panel with Streaming Data and Camera Input 18 Chapter 4 Block Diagram 19 Chapter 5 Pins 20 Pinout Diagram QFP22 256-pin 20 Pinout Diagram PBGA 256-pin 21 Pin Descriptions 22 Host Interface 23 LCD Interface 26 SDRAM Interface 27 Camera / I2C Interface 28 SPI Flash Interface 28 I2S Interface 29 Miscellaneous 29 Power And Ground 31 Configuration Pins 32 Host Interface Pin Mapping 34 LCD / Camera2 Pin Mapping 39 Chapter 6 D.C. Characteristics 41 Chapter 7 A.C. Characteristics 44 Clock Timing 44 Input Clocks 44 EPSON S1D13515/S2D13515 Internal Clocks 45 PLL Clock 46 Power Supply Sequence Power Supply Structure 47 Power-On Sequence 48 Power-Off Sequence 48 RESET# Timing Parallel Host Bus Interface Timing Direct/Indirect Intel 80 Type 1 50 Direct/Indirect Intel 80 Type 2 54 Direct Marvell PXA3xx VLIO 58 Direct/Indirect Renesas SH4 62 Direct/Indirect Freescale MPC555 Non-burst Mode 66 Direct/Indirect Freescale MPC555 Burst Mode 70 Direct/Indirect TI TSM470 Non-burst Mode 74 Direct/Indirect TI TSM470 Burst Mode 78 Direct/Indirect NEC V850 Type 1 82 Direct/Indirect NEC V850 Type 2 86 Serial Host Bus Interface Timing SPI 90 I2C 92 Panel Interface Timing Generic TFT Panel Timing 93 ND-TFD 8-Bit Serial Interface Timing 98 ND-TFD 9-Bit Serial Interface Timing a-Si TFT Serial Interface Timing uWIRE Serial Interface Timing 24-Bit Serial Interface Timing Sharp DualView Panel Timing EID Double Screen Panel Timing TCON Enabled Camera Interface Timing 118 SDRAM Interface Timing 119 I2S Interface Timing 121 Keypad Interface Timing 123 Serial Flash SPI Interface Timing 126 Chapter 8 Memory Map 127 Chapter 9 Clocks 128 Chapter 10 Registers 129 Register Mapping 129 EPSON S1D13515/S2D13515 Register Set 130 Register Restrictions 140 Register Descriptions 140 System Control Registers 140 Host Interface Registers 159 Bit Per Pixel Converter Configuration Registers 164 I2S Control Registers 181 I2S DMA Registers 187 GPIO Registers 190 Keypad Registers 195 PWM Registers 202 SDRAM Read/Write Buffer Registers 207 Warp Logic Configuration Registers 217 Blending Engine Configuration Registers 233 Image Fetcher Configuration Registers 268 LCD Configuration Registers 275 Interrupt Configuration Registers 296 Timer Configuration Registers 317 SPI Flash Memory Interface Registers 321 Cache Control Register 325 Camera Interface Registers 326 DMA Controller Registers 354 SDRAM Controller Configuration Registers 366 LCD Panel Configuration Registers 369 Sprite Registers 414 Sprite Memory Based Registers 421 Chapter 11 Operating Configurations and States 432 Hard Reset State 433 C33PE Run State 438 C33PE Reset State 439 Power Save State 439 Soft Reset State 439 Chapter 12 Bit-Per-Pixel Converter Functional Description 440 System Level Connections 442 Chapter 13 Display Subsystem 443 Block Diagram 443 Hardware Blocks 446 LCD Panel Interface 446 Blending Engine 451 EPSON S1D13515/S2D13515 Warp Engine CH1OUT Writeback Warp Writeback Image Fetcher Input Selectors for LCD Panel Interface Memory Organization of Frames 465 “Line-by-Line” Image Storage “Tiled Frame” Image Storage Frame Double-Buffering Scheme 467 Overview Frame Producer Flowchart Frame Consumer Flowchart Registers for Frame Double-Buffering Control Gamma LUT 474 Chapter 14 I2S Audio Output Interface 476 Overview of Operation 476 Audio Data Formats and Organization in Memory 477 WS Polarity 477 Channel Data Blanking 477 WS Timing in Relation to SDO 477 PCM Data Bit Order 478 WS/SCK Signal Direction 478 Interrupts 478 I2S FIFO Interrupts I2S DMA Interrupt I2S Typical Operation Flow 479 Chapter 15 2D BitBLT 481 ROM Monitor BitBLT Functions 481 Loadable BitBLT Functions 482 Small Library Large Library Other Libraries Chapter 16 Sprite Engine 483 Sprite Data Path 484 8 Sprite Support with Z-ordering Transparency 485 8 Sprite Support with Z-ordering Alpha-Blending 486 Reference Point Based 90°, 180° and 270° Rotation + Mirror 488 Sprite Display Orientation and Positioning 489 Sprite Programming Flow 494 EPSON S1D13515/S2D13515 Chapter 17 SDRAM Interface 497 SDRAM Device Types 497 SDRAM Timing Options 499 tRP Timing Parameter 499 tRCD Timing Parameter 499 tRAS Timing Parameter 499 SDRAM Initialization 500 Self-Refresh Mode 501 Chapter 18 SDRAM Read/Write Buffer 502 Introduction 502 Operation 502 Write Operation 504 Read Operation 505 Interrupts 506 Chapter 19 Pulse Width Modulation PWM 507 Chapter 20 General-Purpose IO Pins 509 Chapter 21 Host Interface 512 Overview 512 Intel80 Type1 Interface 514 Intel80 Type2 Interface 515 NEC V850 Type1 Interface 516 NEC V850 Type2 Interface 517 Renesas SH4 Interface 518 Marvell PXA3xx Interface 519 TI TMS470 Interface 520 MPC555 Interface 521 SPI Host Interface 522 I2C Host Interface 526 Host Interface Access Methods 529 Direct Mode 529 Indirect Mode 531 Initialization Examples 533 Chapter 22 Camera Interface Subsystem 535 Overview 535 IO Pins for Camera Interfaces 536 8-bit Camera Interface 536 RGB Streaming Input Interface 536 Camera Input Interface 537 Resizer 538 EPSON S1D13515/S2D13515 YUV-to-RGB Converter 539 Camera Writer 540 Chapter 23 Keypad Interface 541 Keypad Pin Mapping 541 Scanning Operation 541 Input Glitch Filter 542 General-Purpose Input Function 542 Interrupts 542 Keypad Operation Flow 543 Chapter 24 Timers 545 Watchdog Timer 545 Timer 0 545 Timer 1 545 Timer Operation Flow 546 Chapter 25 SPI Flash Memory Interface 547 Overview 547 IO Pins for SPI Interface 548 SPI Interface Registers 548 SPI Flash Chip Select Control Register SPI Flash Control Register SPI Flash Data Control Register SPI Flash Write Data Register SPI Flash Read Data Register SPI Flash Status Register SPI Interface Operation Flow 550 SPI Flash Interface Timing 555 Chapter 26 JTAG Interface 556 JTAG Pins 556 TAP Controller 557 TAP Controller Paths TAP Controller Main State TAP Controller State Machine JTAG Instruction Codes 559 Boundary Scan Cell Definitions Example BSDL File for the S2D13515 Chapter 27 Design Considerations 572 Guidelines for PLL Power Layout 572 Chapter 28 Mechanical Data 574 EPSON S1D13515/S2D13515 Chapter 29 References 578 Chapter 30 Change Record 579 EPSON S1D13515/S2D13515 EPSON S1D13515/S2D13515 Chapter 1 Introduction Chapter 1 Introduction Scope This is the Hardware Functional Specification for the S1D13515/S2D13515 Display Controller. Included in this document are timing diagrams, AC and DC characteristics, register descriptions, and power management descriptions. This document is intended for two audiences Video Subsystem Designers and Software Developers. We appreciate your comments on our documentation. Please contact us via email at Overview Description The S1D13515/S2D13515 is a highly integrated color LCD graphics controller with external memory interface. The architecture is designed to meet the needs of automotive and embedded markets requiring a flexible LCD solution. For automotive applications, the S2D13515 has three primary target placements within a vehicle. Heads-Up Display Instrument Cluster Center Console The S1D13515/S2D13515 advances on the successes of other Epson LCD controllers by embedding a proprietary 32-bit RISC CPU and associated accelerator blocks to achieve an increase in flexibility and functionality over previous designs. Routines are provided allowing for audio playback, 2D BitBLT operations, warp and filtering before display operations, and the ability to offer OpenGL-ES support. In particular, the warp functions make this an ideal solution for the automotive Heads-Up Display HUD market, or pseudo 3D navigation displays. The S1D13515/S2D13515 is an affordable, low power device which uses a flexible external SDRAM memory interface to provide its frame buffer. It supports a wide variety of CPU interfaces and LCD panel types, including Double Display panels, which makes it an excellent choice for instrumentation or center cluster applications. While focusing on the automotive market, the S1D13515/S2D13515’s impartiality to CPU type or operating system makes it an ideal display solution for a wide variety of other markets. The S1D13515/S2D13515 design includes some of the following key features Warp engine for HUD projection correction Embedded 32-bit proprietary RISC CPU Support for two TFT Displays simultaneously Support for Double Display LCD panels from Epson and Sharp The ability to provide OpenGL-ES library functionality The ability to playback audio The ability to reset and display an image without the Host CPU involvement EPSON Chapter 2 Features S1D13515/S2D13515 Chapter 2 Features Memory • Uses external SDRAM which is • Accessible by both the internal and Host CPUs • Used for executable code, data, and the frame buffer • Addressable through direct or indirect access modes • Accessible linearly in configurable 4M byte paging windows direct access mode • SDRAM Interface • SDRAM Clock Frequency 100Mhz typical • Supports x16 and x32 SDRAM interfaces x32 is strongly recommended in most cases • Supports 8/16/32/64M bytes of 4 bank SDRAM • Low power design CPU Interfaces Note The S1D/S2D13515 supports Little Endian interface only. • Direct and indirect interface support for the following CPU interfaces • Intel 80 Types 1 and 2 8/16-bit • Renesas SH-4 8/16-bit • FreeScale MPC555 PowerPC bus interface with burst and non-burst modes 16-bit Little Endian configuration only • NEC V850 Types 1 and 2 8/16-bit • Texas Instruments TMS470 with burst mode 16-bit only • Marvell PXA3xx 16-bit Direct only • Serial Host Interface • SPI • I2C I2S Data Bit Ordering Read/Write IS2 Output Data Clock Source bit 7 I2S Blank Left Channel This bit is used to blank left channel data for the I2S interface. When this bit = 0b, the left channel data is normal. When this bit = 1b, the left channel data is blanked. bit 6 I2S Blank Right Channel This bit is used to blank right channel data for the I2S interface. When this bit = 0b, the right channel data is normal. When this bit = 1b, the right channel data is blanked. bit 5 I2S Left/Right Channel Data Order This bit determines the left/right channel data order relative to the state of the WSIO pin. When this bit = 0b, the left/right channel data order is left channel when WSIO = 1, right channel when WSIO = When this bit = 1b, the left/right channel data order is right channel when WSIO = 1, left channel when WSIO = Note If the channel data order must be changed while the I2S interface is running, the I2S FIFO must be cleared using the following sequence. Disable the I2S DAC Controller, REG[0104h] bit 0 = 0b Reset the I2S FIFO, REG[010Ch] bit 8 = 1b Change the I2S Left/Right Channel Data Order, REG[0100h] bit 5 Enable the I2S DAC Controller, REG[0104h] bit 0 = 1b bit 4 I2S Data Transition Clock Edge This bit determines when the serial output data on the SDO pin changes. When this bit = 0b, serial output data changes on the falling edge of the serial output source clock. When this bit = 1b, serial output data changes on the rising edge of the serial output source clock. bit 3 I2S WSIO Data Timing This bit determines when serial data output on the SDO pin occurs relative to the word sync signal edge WSIO . When this bit = 0b, serial output data starts one clock after the WSIO edge. When this bit = 1b, serial output data starts on the same clock edge as WSIO. EPSON Chapter 10 Registers S1D13515/S2D13515 bit 2 I2S Data Bit Ordering This bit determines the bit order for serial data output on the SDO pin. When this bit = 0b, the most significant bit msb is sent first. When this bit = 1b, the least significant bit lsb is sent first. bit 0 I2S Data Clock Source This bit selects the source of the data clock used for serial data output on the SDO pin. This bit must be set in combination with the WSIO and SCKIO Output Enable bit REG[0101h] bit 0 as shown in the following table. Table 10-26 I2S Data Clock WSIO/SCKIO Settings REG[0101h] bit 0 0b default 1b REG[0100h] bit 0 0b 1b default 0b 1b Reserved I2S data clock source is the internal clock. WSIO/SCKIO are outputs driven by the internal clocks. I2S data clock source is an external clock and WSIO/SCKIO are inputs high-impedance . Reserved REG[0101h] I2S Interface Control Register 1 Default = 40h Reserved Read/Write WSIO and SCKIO Output Enable bit 6 Reserved This bit must be set to 1b. bit 0 WSIO and SCKIO Output Enable This bit controls whether the serial word clock WSIO and the serial bit clock SCKIO are outputs for the I2S interface. This bit must be set in combination with the I2S Data Clock Source bit REG[0100h] bit 0 as shown in Table 10-26 “I2S Data Clock WSIO/SCKIO Settings” above. EPSON S1D13515/S2D13515 Chapter 10 Registers REG[0104h] I2S FIFO Register 0 Default = 00h I2S FIFO Mode I2S FIFO Threshold Level bits 3-0 Reserved 1 Read/Write I2S DAC Controller Enable bit 7 8 Sprite Support with Z-ordering Transparency Each sprite has an associated z-order which is used to determine which part of the sprite is displayed when the sprite overlaps the main image or other sprites. Note When configuring the Z-order and transparency settings, Sprite #0 must always be set to the lowest Zorder and must have transparency disabled. Figure 16-2 Z-order Example EPSON Chapter 16 Sprite Engine S1D13515/S2D13515 When RGB 5:6:5 format is selected, one programmable transparency color may be associated with it. Transparency allows an irregular shaped image to be displayed over the background. Figure 16-3 Z-order with Transparency Example 8 Sprite Support with Z-ordering Alpha-Blending The Sprite Engine supports Alpha-Blending which provides further visual enhancement for games and similar applications. Alpha-blending is used in computer graphics to create the effect of transparency. This technique is useful for graphics that feature glass or liquid objects and is done by combining a translucent foreground with a background color to create a blend. It can also be used for animation, where one image gradually fades into another image. Note When configuring the Z-order and alpha blending settings, Sprite #0 must always be set to the lowest Z-order and must not have an alpha value of 0 transparent . The Sprite Engine supports alpha-blending for 2 alpha formats. • ARGB 1:5:5:5 - one Alpha bit points to 2 programmable indexed 4-bit alpha values • ARGB 4:4:4:4 - the four bits represent the actual alpha value The following equation describes the alpha blending technique used. [r, g, b]blended = α[r, g, b]foreground + 1 α [r, g, b]background Where: [r,g,b] are the red, green, and blue color channels α is the weighting factor EPSON S1D13515/S2D13515 Chapter 16 Sprite Engine The weighting factor value can be from 0 to 1 represented as 0 to 15 for Sprite Engine . When set to 0, the foreground is completely transparent. When it is set to 1, the background is completely transparent. All values between specify a mixture of the foreground and the background. Figure 16-4 Alpha Blending with Alpha Value of 0, and 1 The Sprite Engine allows up to 8 sprites to be alpha blended together. Z-ordering determines which sprites are displayed in the foreground and background for each alpha-blending operation. Figure 16-5 Z-order with Alpha-Blending EPSON Chapter 16 Sprite Engine S1D13515/S2D13515 Reference Point Based 90°, 180° and 270° Rotation + Mirror Each sprite can be independently rotated 90°, 180°, 270° and/or mirrored. The resulting orientation of the sprite is independent of the main display orientation. Each sprite has a programmable rotation reference point. Unlike other designs where the rotation is always based on the center of the image, this design allows the user to program any point on the display as the rotation axis. This reference point can even be outside of the sprite area. Reference Point Figure 16-6 Sprite Reference Point No rotation Mirror 180° 180° + Mirror 90° 90° + Mirror 270° Figure 16-7 Sprite Rotation and Mirror Examples 270° + Mirror EPSON S1D13515/S2D13515 Chapter 16 Sprite Engine Sprite Display Orientation and Positioning The sprite frame rendered to the SDRAM frame buffer is determined by the dimensions of Sprite Therefore, Sprite #0 defines the resulting SDRAM memory size, and sprite #1 - #7 position is rendered with reference to the rectangle defined by the Sprite #0 frame width and height parameters. Note Rotation is not supported for Sprite The Main / AUX / OSD window dimensions and memory start address should match the sprite #0 dimensions and the sprite frame buffer start address, in order to display the rendered sprite frame to the Main / AUX / OSD Window of the display. The following figures demonstrate how to size and position a sprite for rendering to the frame buffer. Examples are shown for several combinations of rotation and mirroring. Sprite collision rectangle orientation and positioning is done in a similar manner. The figures assume the following values: A = X offset of the reference point relative to the upper left corner of the sprite B = Y offset of the reference point relative to the upper left corner of the sprite C = X offset of the sprite position reference point relative to the upper left corner of the display D = Y offset of the sprite position reference point relative to the upper left corner of the display E = New effective X-Start of the sprite on the display after rotation/mirroring F = New effective Y-Start of the sprite on the display after rotation/mirroring G = Width of the sprite - A H = Height of the sprite - B I = New effective X-End of the sprite on the display after rotation/mirroring J = New effective Y-End of the sprite on the display after rotation/mirroring EPSON Chapter 16 Sprite Engine 0° Rotation with Mirror Disabled S1D13515/S2D13515 Reference point Rendered Sprite Frame Figure 16-8 Sprite Display for Rotation 0° with Mirror Disabled E=C-A I=C+G F=D-B J=D+H 90° Rotation with Mirror Disabled Reference point • section 8 Sprite Support with Z-ordering Transparency - rewrite note • section 8 Sprite Support with Z-ordering Alpha-Blending - rewrite note • section Reference Point Based 90°, 180° and 270° Rotation + Mirror - correct the orientation of “180°” and “180° + Mirror” in figure 16-7 • section Sprite Display Orientation and Positioning - in figure 16-8, replace “Y position” with “F” • chapter 20 General-Purpose IO Pins - add note for GPIO7 “GPIO7 is not available...” • section I2C Host Interface - add table 21-12 I2C Slave Addresses and notes 1 and 2 following the table EPSON S1D13515/S2D13515 Chapter 30 Change Record • section Keypad Pin Mapping - add note “GPIO7 is not available...” • section SPIFlash Control Register - remove bulleted text “Bit 6 is the SPI Flash Read Command Select bit...” state after writes are completed and read data is ready • section and updated the NEC V850 Type 1 and Type 2 Read/Write Timing tables with new min/max values for fCLKOUT, t1, t2, and t3 • section and updated the NEC V850 Type 1 and Type 2 Read/Write Timing tables with a note regarding programmable wait states • section and updated the NEC V850 Type 1 and Type 2 Write and Read Timing figures and tables with new timing “t13” to clarify WAIT# state after writes are completed and read data is ready • section removed note 1 from the I2C Host Interface Timing table • section updated the Panel Interface Timing figures and tables • section added min/max values for the Camera Interface Timing table • section corrected typos for the PU/D conditions for NEC V850 Type 2 8-bit Direct and Renesas SH4 8-bit Direct in the Hard Reset Pin States table • section changed references from “PIP+” to “AUX / OSD” • section added note to step 3 regarding the SDRAM command sequence EPSON Chapter 30 Change Record S1D13515/S2D13515 • section removed the RESET# State column from the pin description tables this information is now included in section 11 • section moved IRQ pin description from the Miscellaneous pins section to the Host Interface pins section • section changed AB6 Cell Type from “BHSC4D2” to “BHSC4P2” DB9 Cell Type from “BHSC4D2” to “BHSC4P2” CS# Cell Type from “ICU1” to “ICD1” RD# Cell Type from “ICU1” to “ICD1” RD/WR# Cell Type from “ICU1” to “ICD1” BE0# Cell Type from “ICU1” to “ICD1” BE1# Cell Type from “BHSC4P2” to “BHSC4D2” BS# Cell Type from “BHSC4D2” to “BHSC4P2” BURST# Cell Type from “ICU1” to “IC” BDIP# Cell Type from “ICU1” to “IC” BUSCLK Cell Type from “ICU1” to “ICD1” CNF[2:1] Cell Type from “ICD2” to “IC” • section changed the FP2IO17 Cell Type to “BHSC4P2” • section changed MPC555 to use BE1# to determine Indirect/Direct • section changed MPC555 host pin mapping to show that BE1# is used to determine Indirect/Direct • tables 5-12 ~ 5-18 - changes to table formats and some signal names • section 6 D.C. Characteristics - for tables 6-2 and 6-3 change TOPR max to “105” • section added min/max values for Clock Requirements tables • section added max values for Internal Clock Requirements table • section added max values for the PLL Clock Requirements table • section added RESET# Timing min/max values and note 1 • section updated all Parallel Host Interface Timing figures/tables • section updated all Serial Host Timing figures/tables • section added Panel Interface Timing min/max values • section changed all Camera Interface Timing min values to TBD • section updated the SDRAM Interface Timing section • removed I2C Interface Timing section • section updated I2S Interface Timing section with new figures and tables • section 7-12 Keypad Interface Timing - changes to table 7-40 Keypad Interface Timing, replace figure 7-43 “Keypad Interface Input Timing” with “Keypad Glitch Filter Input Timing” • section added Serial Flash SPI Interface Timing section • section 9, added the Camera1/Camera2 Clock Output Disable bits EPSON S1D13515/S2D13515

PDF Datasheet Preview

S1D13515 / S2D13515 Display Controller

Hardware Functional Specification

SEIKO EPSON CORPORATION

NOTICE

No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency.

All other product names mentioned herein are trademarks and/or registered trademarks of their respective companies.

SEIKO EPSON CORPORATION 2006 - 2011, All rights reserved.

S1D13515/S2D13515

Table Of Contents

Chapter 1 Introduction 11 Scope 11 Overview Description 11

Chapter 2 Features 12 Memory 12 CPU Interfaces 12 Panel Interface Support 13 Display Features 14 Embedded CPU 14 Sprite Engine 15 Video / Camera Input 15 Clock Source 15 Miscellaneous 16

Chapter 3 Typical Implementation Use Cases 17 Use Case 1 - Heads-Up Display HUD with LCD Panel 17 Use Case 2 - Dual-View Panel with Streaming Data and Camera Input 18

Chapter 4 Block Diagram 19 Chapter 5 Pins 20

Pinout Diagram QFP22 256-pin 20 Pinout Diagram PBGA 256-pin 21 Pin Descriptions 22

Host Interface 23 LCD Interface 26 SDRAM Interface 27 Camera / I2C Interface 28 SPI Flash Interface 28 I2S Interface 29 Miscellaneous 29 Power And Ground 31 Configuration Pins 32 Host Interface Pin Mapping 34 LCD / Camera2 Pin Mapping 39 Chapter 6 D.C. Characteristics 41 Chapter 7 A.C. Characteristics 44 Clock Timing 44 Input Clocks 44

EPSON

S1D13515/S2D13515

Internal Clocks 45 PLL Clock 46 Power Supply Sequence Power Supply Structure 47 Power-On Sequence 48 Power-Off Sequence 48 RESET# Timing Parallel Host Bus Interface Timing Direct/Indirect Intel 80 Type 1 50 Direct/Indirect Intel 80 Type 2 54 Direct Marvell PXA3xx VLIO 58 Direct/Indirect Renesas SH4 62 Direct/Indirect Freescale MPC555 Non-burst Mode 66 Direct/Indirect Freescale MPC555 Burst Mode 70 Direct/Indirect TI TSM470 Non-burst Mode 74 Direct/Indirect TI TSM470 Burst Mode 78 Direct/Indirect NEC V850 Type 1 82 Direct/Indirect NEC V850 Type 2 86 Serial Host Bus Interface Timing SPI 90 I2C 92 Panel Interface Timing Generic TFT Panel Timing 93 ND-TFD 8-Bit Serial Interface Timing 98 ND-TFD 9-Bit Serial Interface Timing a-Si TFT Serial Interface Timing uWIRE Serial Interface Timing 24-Bit Serial Interface Timing Sharp DualView Panel Timing EID Double Screen Panel Timing TCON Enabled Camera Interface Timing 118 SDRAM Interface Timing 119 I2S Interface Timing 121 Keypad Interface Timing 123 Serial Flash SPI Interface Timing 126 Chapter 8 Memory Map 127 Chapter 9 Clocks 128 Chapter 10 Registers 129 Register Mapping 129

EPSON

S1D13515/S2D13515

Register Set 130 Register Restrictions 140 Register Descriptions 140

System Control Registers 140 Host Interface Registers 159 Bit Per Pixel Converter Configuration Registers 164 I2S Control Registers 181 I2S DMA Registers 187 GPIO Registers 190 Keypad Registers 195 PWM Registers 202 SDRAM Read/Write Buffer Registers 207 Warp Logic Configuration Registers 217 Blending Engine Configuration Registers 233 Image Fetcher Configuration Registers 268 LCD Configuration Registers 275 Interrupt Configuration Registers 296 Timer Configuration Registers 317 SPI Flash Memory Interface Registers 321 Cache Control Register 325 Camera Interface Registers 326 DMA Controller Registers 354 SDRAM Controller Configuration Registers 366 LCD Panel Configuration Registers 369 Sprite Registers 414 Sprite Memory Based Registers 421 Chapter 11 Operating Configurations and States 432 Hard Reset State 433 C33PE Run State 438 C33PE Reset State 439 Power Save State 439 Soft Reset State 439 Chapter 12 Bit-Per-Pixel Converter Functional Description 440 System Level Connections 442 Chapter 13 Display Subsystem 443 Block Diagram 443 Hardware Blocks 446 LCD Panel Interface 446 Blending Engine 451

EPSON

S1D13515/S2D13515
Warp Engine CH1OUT Writeback Warp Writeback Image Fetcher Input Selectors for LCD Panel Interface Memory Organization of Frames 465 “Line-by-Line” Image Storage “Tiled Frame” Image Storage Frame Double-Buffering Scheme 467 Overview Frame Producer Flowchart Frame Consumer Flowchart Registers for Frame Double-Buffering Control Gamma LUT 474 Chapter 14 I2S Audio Output Interface 476 Overview of Operation 476 Audio Data Formats and Organization in Memory 477 WS Polarity 477 Channel Data Blanking 477 WS Timing in Relation to SDO 477 PCM Data Bit Order 478 WS/SCK Signal Direction 478 Interrupts 478 I2S FIFO Interrupts I2S DMA Interrupt I2S Typical Operation Flow 479 Chapter 15 2D BitBLT 481 ROM Monitor BitBLT Functions 481 Loadable BitBLT Functions 482 Small Library Large Library Other Libraries Chapter 16 Sprite Engine 483 Sprite Data Path 484 8 Sprite Support with Z-ordering Transparency 485 8 Sprite Support with Z-ordering Alpha-Blending 486 Reference Point Based 90°, 180° and 270° Rotation + Mirror 488 Sprite Display Orientation and Positioning 489 Sprite Programming Flow 494

EPSON

S1D13515/S2D13515

Chapter 17 SDRAM Interface 497 SDRAM Device Types 497 SDRAM Timing Options 499 tRP Timing Parameter 499 tRCD Timing Parameter 499 tRAS Timing Parameter 499 SDRAM Initialization 500 Self-Refresh Mode 501

Chapter 18 SDRAM Read/Write Buffer 502 Introduction 502 Operation 502 Write Operation 504 Read Operation 505 Interrupts 506

Chapter 19 Pulse Width Modulation PWM 507

Chapter 20 General-Purpose IO Pins 509

Chapter 21 Host Interface 512 Overview 512 Intel80 Type1 Interface 514 Intel80 Type2 Interface 515 NEC V850 Type1 Interface 516 NEC V850 Type2 Interface 517 Renesas SH4 Interface 518 Marvell PXA3xx Interface 519 TI TMS470 Interface 520 MPC555 Interface 521 SPI Host Interface 522 I2C Host Interface 526 Host Interface Access Methods 529 Direct Mode 529 Indirect Mode 531 Initialization Examples 533

Chapter 22 Camera Interface Subsystem 535 Overview 535 IO Pins for Camera Interfaces 536 8-bit Camera Interface 536 RGB Streaming Input Interface 536 Camera Input Interface 537 Resizer 538

EPSON

S1D13515/S2D13515

YUV-to-RGB Converter 539 Camera Writer 540 Chapter 23 Keypad Interface 541 Keypad Pin Mapping 541 Scanning Operation 541 Input Glitch Filter 542 General-Purpose Input Function 542 Interrupts 542 Keypad Operation Flow 543 Chapter 24 Timers 545 Watchdog Timer 545 Timer 0 545 Timer 1 545 Timer Operation Flow 546 Chapter 25 SPI Flash Memory Interface 547 Overview 547 IO Pins for SPI Interface 548 SPI Interface Registers 548

SPI Flash Chip Select Control Register SPI Flash Control Register SPI Flash Data Control Register SPI Flash Write Data Register SPI Flash Read Data Register SPI Flash Status Register SPI Interface Operation Flow 550 SPI Flash Interface Timing 555 Chapter 26 JTAG Interface 556 JTAG Pins 556 TAP Controller 557 TAP Controller Paths TAP Controller Main State TAP Controller State Machine JTAG Instruction Codes 559 Boundary Scan Cell Definitions Example BSDL File for the S2D13515 Chapter 27 Design Considerations 572 Guidelines for PLL Power Layout 572 Chapter 28 Mechanical Data 574

EPSON

S1D13515/S2D13515

Chapter 29 References 578 Chapter 30 Change Record 579

EPSON

S1D13515/S2D13515

EPSON

S1D13515/S2D13515

Chapter 1 Introduction

Chapter 1 Introduction

Scope

This is the Hardware Functional Specification for the S1D13515/S2D13515 Display Controller. Included in this document are timing diagrams, AC and DC characteristics, register descriptions, and power management descriptions. This document is intended for two audiences Video Subsystem Designers and Software Developers.

We appreciate your comments on our documentation. Please contact us via email at

Overview Description

The S1D13515/S2D13515 is a highly integrated color LCD graphics controller with external memory interface. The architecture is designed to meet the needs of automotive and embedded markets requiring a flexible LCD solution. For automotive applications, the S2D13515 has three primary target placements within a vehicle. Heads-Up Display Instrument Cluster Center Console

The S1D13515/S2D13515 advances on the successes of other Epson LCD controllers by embedding a proprietary 32-bit RISC CPU and associated accelerator blocks to achieve an increase in flexibility and functionality over previous designs. Routines are provided allowing for audio playback, 2D BitBLT operations, warp and filtering before display operations, and the ability to offer OpenGL-ES support. In particular, the warp functions make this an ideal solution for the automotive Heads-Up Display HUD market, or pseudo 3D navigation displays.

The S1D13515/S2D13515 is an affordable, low power device which uses a flexible external SDRAM memory interface to provide its frame buffer. It supports a wide variety of CPU interfaces and LCD panel types, including Double Display panels, which makes it an excellent choice for instrumentation or center cluster applications. While focusing on the automotive market, the S1D13515/S2D13515’s impartiality to CPU type or operating system makes it an ideal display solution for a wide variety of other markets.

The S1D13515/S2D13515 design includes some of the following key features Warp engine for HUD projection correction Embedded 32-bit proprietary RISC CPU Support for two TFT Displays simultaneously Support for Double Display LCD panels from Epson and Sharp The ability to provide OpenGL-ES library functionality The ability to playback audio The ability to reset and display an image without the Host CPU involvement

EPSON

Chapter 2 Features

S1D13515/S2D13515

Chapter 2 Features

Memory
• Uses external SDRAM which is
• Accessible by both the internal and Host CPUs
• Used for executable code, data, and the frame buffer
• Addressable through direct or indirect access modes
• Accessible linearly in configurable 4M byte paging windows direct access mode
• SDRAM Interface
• SDRAM Clock Frequency 100Mhz typical
• Supports x16 and x32 SDRAM interfaces x32 is strongly recommended in most cases
• Supports 8/16/32/64M bytes of 4 bank SDRAM
• Low power design

CPU Interfaces

Note The S1D/S2D13515 supports Little Endian interface only.
• Direct and indirect interface support for the following CPU interfaces
• Intel 80 Types 1 and 2 8/16-bit
• Renesas SH-4 8/16-bit
• FreeScale MPC555 PowerPC bus interface with burst and non-burst modes 16-bit Little Endian configuration only
• NEC V850 Types 1 and 2 8/16-bit
• Texas Instruments TMS470 with burst mode 16-bit only
• Marvell PXA3xx 16-bit Direct only
• Serial Host Interface
• SPI
• I2C
I2S Data Bit Ordering

Read/Write

IS2 Output Data Clock Source
bit 7

I2S Blank Left Channel

This bit is used to blank left channel data for the I2S interface.

When this bit = 0b, the left channel data is normal.

When this bit = 1b, the left channel data is blanked.
bit 6

I2S Blank Right Channel

This bit is used to blank right channel data for the I2S interface.

When this bit = 0b, the right channel data is normal.

When this bit = 1b, the right channel data is blanked.
bit 5

I2S Left/Right Channel Data Order

This bit determines the left/right channel data order relative to the state of the WSIO pin.

When this bit = 0b, the left/right channel data order is left channel when WSIO = 1, right
channel when WSIO =

When this bit = 1b, the left/right channel data order is right channel when WSIO = 1, left
channel when WSIO =

Note If the channel data order must be changed while the I2S interface is running, the I2S FIFO must be cleared using the following sequence. Disable the I2S DAC Controller, REG[0104h] bit 0 = 0b Reset the I2S FIFO, REG[010Ch] bit 8 = 1b Change the I2S Left/Right Channel Data Order, REG[0100h] bit 5 Enable the I2S DAC Controller, REG[0104h] bit 0 = 1b
bit 4

I2S Data Transition Clock Edge

This bit determines when the serial output data on the SDO pin changes.

When this bit = 0b, serial output data changes on the falling edge of the serial output
source clock.

When this bit = 1b, serial output data changes on the rising edge of the serial output source
clock.
bit 3

I2S WSIO Data Timing

This bit determines when serial data output on the SDO pin occurs relative to the word
sync signal edge WSIO .

When this bit = 0b, serial output data starts one clock after the WSIO edge.

When this bit = 1b, serial output data starts on the same clock edge as WSIO.

EPSON

Chapter 10 Registers

S1D13515/S2D13515
bit 2
I2S Data Bit Ordering

This bit determines the bit order for serial data output on the SDO pin.

When this bit = 0b, the most significant bit msb is sent first.

When this bit = 1b, the least significant bit lsb is sent first.
bit 0

I2S Data Clock Source

This bit selects the source of the data clock used for serial data output on the SDO pin.

This bit must be set in combination with the WSIO and SCKIO Output Enable bit

REG[0101h] bit 0 as shown in the following table.

Table 10-26 I2S Data Clock WSIO/SCKIO Settings

REG[0101h] bit 0 0b default 1b

REG[0100h] bit 0 0b
1b default
0b 1b

Reserved

I2S data clock source is the internal clock. WSIO/SCKIO are outputs driven by the internal clocks.

I2S data clock source is an external clock and WSIO/SCKIO are inputs high-impedance .

Reserved

REG[0101h] I2S Interface Control Register 1 Default = 40h

Reserved

Read/Write

WSIO and SCKIO Output Enable
bit 6

Reserved

This bit must be set to 1b.
bit 0

WSIO and SCKIO Output Enable

This bit controls whether the serial word clock WSIO and the serial bit clock SCKIO
are outputs for the I2S interface. This bit must be set in combination with the I2S Data

Clock Source bit REG[0100h] bit 0 as shown in Table 10-26 “I2S Data Clock

WSIO/SCKIO Settings” above.

EPSON

S1D13515/S2D13515

Chapter 10 Registers

REG[0104h] I2S FIFO Register 0 Default = 00h

I2S FIFO Mode

I2S FIFO Threshold Level bits 3-0

Reserved 1

Read/Write

I2S DAC Controller Enable
bit 7
8 Sprite Support with Z-ordering Transparency

Each sprite has an associated z-order which is used to determine which part of the sprite is displayed when the sprite overlaps the main image or other sprites.

Note When configuring the Z-order and transparency settings, Sprite #0 must always be set to the lowest Zorder and must have transparency disabled.

Figure 16-2 Z-order Example

EPSON

Chapter 16 Sprite Engine

S1D13515/S2D13515

When RGB 5:6:5 format is selected, one programmable transparency color may be associated with it. Transparency allows an irregular shaped image to be displayed over the background.

Figure 16-3 Z-order with Transparency Example
8 Sprite Support with Z-ordering Alpha-Blending

The Sprite Engine supports Alpha-Blending which provides further visual enhancement for games and similar applications. Alpha-blending is used in computer graphics to create the effect of transparency. This technique is useful for graphics that feature glass or liquid objects and is done by combining a translucent foreground with a background color to create a blend. It can also be used for animation, where one image gradually fades into another image.

Note When configuring the Z-order and alpha blending settings, Sprite #0 must always be set to the lowest Z-order and must not have an alpha value of 0 transparent .

The Sprite Engine supports alpha-blending for 2 alpha formats.
• ARGB 1:5:5:5 - one Alpha bit points to 2 programmable indexed 4-bit alpha values
• ARGB 4:4:4:4 - the four bits represent the actual alpha value

The following equation describes the alpha blending technique used.
[r, g, b]blended = α[r, g, b]foreground + 1 α [r, g, b]background

Where:
[r,g,b] are the red, green, and blue color channels α is the weighting factor

EPSON

S1D13515/S2D13515

Chapter 16 Sprite Engine

The weighting factor value can be from 0 to 1 represented as 0 to 15 for Sprite Engine . When set to 0, the foreground is completely transparent. When it is set to 1, the background is completely transparent. All values between specify a mixture of the foreground and the background.

Figure 16-4 Alpha Blending with Alpha Value of 0, and 1
The Sprite Engine allows up to 8 sprites to be alpha blended together. Z-ordering determines which sprites are displayed in the foreground and background for each alpha-blending operation.

Figure 16-5 Z-order with Alpha-Blending

EPSON

Chapter 16 Sprite Engine

S1D13515/S2D13515

Reference Point Based 90°, 180° and 270° Rotation + Mirror

Each sprite can be independently rotated 90°, 180°, 270° and/or mirrored. The resulting orientation of the sprite is independent of the main display orientation.

Each sprite has a programmable rotation reference point. Unlike other designs where the rotation is always based on the center of the image, this design allows the user to program any point on the display as the rotation axis. This reference point can even be outside of the sprite area.

Reference Point

Figure 16-6 Sprite Reference Point

No rotation

Mirror
180°
180° + Mirror
90°
90° + Mirror
270°

Figure 16-7 Sprite Rotation and Mirror Examples
270° + Mirror

EPSON

S1D13515/S2D13515

Chapter 16 Sprite Engine

Sprite Display Orientation and Positioning

The sprite frame rendered to the SDRAM frame buffer is determined by the dimensions of Sprite Therefore, Sprite #0 defines the resulting SDRAM memory size, and sprite #1 - #7 position is rendered with reference to the rectangle defined by the Sprite #0 frame width and height parameters.

Note Rotation is not supported for Sprite

The Main / AUX / OSD window dimensions and memory start address should match the sprite #0 dimensions and the sprite frame buffer start address, in order to display the rendered sprite frame to the Main / AUX / OSD Window of the display.

The following figures demonstrate how to size and position a sprite for rendering to the frame buffer. Examples are shown for several combinations of rotation and mirroring. Sprite collision rectangle orientation and positioning is done in a similar manner. The figures assume the following values:

A = X offset of the reference point relative to the upper left corner of the sprite B = Y offset of the reference point relative to the upper left corner of the sprite C = X offset of the sprite position reference point relative to the upper left corner of
the display D = Y offset of the sprite position reference point relative to the upper left corner of
the display E = New effective X-Start of the sprite on the display after rotation/mirroring F = New effective Y-Start of the sprite on the display after rotation/mirroring G = Width of the sprite - A H = Height of the sprite - B I = New effective X-End of the sprite on the display after rotation/mirroring J = New effective Y-End of the sprite on the display after rotation/mirroring

EPSON

Chapter 16 Sprite Engine
0° Rotation with Mirror Disabled

S1D13515/S2D13515

Reference point

Rendered Sprite Frame

Figure 16-8 Sprite Display for Rotation 0° with Mirror Disabled

E=C-A I=C+G

F=D-B J=D+H
90° Rotation with Mirror Disabled

Reference point
• section 8 Sprite Support with Z-ordering Transparency - rewrite note
• section 8 Sprite Support with Z-ordering Alpha-Blending - rewrite note
• section Reference Point Based 90°, 180° and 270° Rotation + Mirror - correct the orientation of “180°” and “180° + Mirror” in figure 16-7
• section Sprite Display Orientation and Positioning - in figure 16-8, replace “Y position” with “F”
• chapter 20 General-Purpose IO Pins - add note for GPIO7 “GPIO7 is not available...”
• section I2C Host Interface - add table 21-12 I2C Slave Addresses and notes 1 and 2 following the table

EPSON

S1D13515/S2D13515

Chapter 30 Change Record
• section Keypad Pin Mapping - add note “GPIO7 is not available...”
• section SPIFlash Control Register - remove bulleted text “Bit 6 is the SPI Flash Read Command Select
bit...”
state after writes are completed and read data is ready
• section and updated the NEC V850 Type 1 and Type 2 Read/Write Timing tables with new
min/max values for fCLKOUT, t1, t2, and t3
• section and updated the NEC V850 Type 1 and Type 2 Read/Write Timing tables with a note
regarding programmable wait states
• section and updated the NEC V850 Type 1 and Type 2 Write and Read Timing figures and tables
with new timing “t13” to clarify WAIT# state after writes are completed and read data is ready
• section removed note 1 from the I2C Host Interface Timing table
• section updated the Panel Interface Timing figures and tables
• section added min/max values for the Camera Interface Timing table
• section corrected typos for the PU/D conditions for NEC V850 Type 2 8-bit Direct and Renesas SH4 8-bit

Direct in the Hard Reset Pin States table
• section changed references from “PIP+” to “AUX / OSD”
• section added note to step 3 regarding the SDRAM command sequence

EPSON

Chapter 30 Change Record

S1D13515/S2D13515
• section removed the RESET# State column from the pin description tables this information is now included in section 11
• section moved IRQ pin description from the Miscellaneous pins section to the Host Interface pins section
• section changed AB6 Cell Type from “BHSC4D2” to “BHSC4P2” DB9 Cell Type from “BHSC4D2” to “BHSC4P2” CS# Cell Type from “ICU1” to “ICD1” RD# Cell Type from “ICU1” to “ICD1” RD/WR# Cell Type from “ICU1” to “ICD1” BE0# Cell Type from “ICU1” to “ICD1” BE1# Cell Type from “BHSC4P2” to “BHSC4D2” BS# Cell Type from “BHSC4D2” to “BHSC4P2” BURST# Cell Type from “ICU1” to “IC” BDIP# Cell Type from “ICU1” to “IC” BUSCLK Cell Type from “ICU1” to “ICD1” CNF[2:1] Cell Type from “ICD2” to “IC”
• section changed the FP2IO17 Cell Type to “BHSC4P2”
• section changed MPC555 to use BE1# to determine Indirect/Direct
• section changed MPC555 host pin mapping to show that BE1# is used to determine Indirect/Direct
• tables 5-12 ~ 5-18 - changes to table formats and some signal names
• section 6 D.C. Characteristics - for tables 6-2 and 6-3 change TOPR max to “105”
• section added min/max values for Clock Requirements tables
• section added max values for Internal Clock Requirements table
• section added max values for the PLL Clock Requirements table
• section added RESET# Timing min/max values and note 1
• section updated all Parallel Host Interface Timing figures/tables
• section updated all Serial Host Timing figures/tables
• section added Panel Interface Timing min/max values
• section changed all Camera Interface Timing min values to TBD
• section updated the SDRAM Interface Timing section
• removed I2C Interface Timing section
• section updated I2S Interface Timing section with new figures and tables
• section 7-12 Keypad Interface Timing - changes to table 7-40 Keypad Interface Timing, replace figure 7-43 “Keypad Interface Input Timing” with “Keypad Glitch Filter Input Timing”
• section added Serial Flash SPI Interface Timing section
• section 9, added the Camera1/Camera2 Clock Output Disable bits

EPSON

S1D13515/S2D13515

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived S2D13515F00A100 Datasheet file may be downloaded here without warranties.

Datasheet ID: S2D13515F00A100 511864