PI90LVB16L

PI90LVB16L Datasheet

PI90LVB16

Part	Datasheet
PI90LVB16L	PI90LVB16L (pdf)

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PI90LVB16 3V Bus LVDS 1-to-6 Clock Buffer/Bus Transceiver Master/Slave clock selection in a backplane application 160 MHz operation typical 100ps duty cycle distortion typical 50ps channel to channel skew typical 3.3V power supply design Glitch-free power on at CLKI/O pins Low Power design 16mA 3.3V static Accepts small swing 300mV typical differential signal levels Industrial temperature operating range 40°C to +85°C Available in 24-pin TSSOP Packaging L PI90LVB16 is a six-channel LVTTL clock distribution driver with 50 picosecond channel-to-channel skew. It translates one BLVDS Bus Low-Voltage Differential Signaling input signal into six LVTTLcompatible output signals for distribution to adjacent chips on the same board. The PI90LVB16 accepts BLVDS 300mV typical differential input levels, and translates them to 3V CMOS output levels. The 160MHz PI90LVB16 can be the master clock, driving inputs of other clock I/O pins in a multipoint environment. It can also drive the BLVDS backplane with a separate channel acting as a return/ source LVTTL clock source. The master/slave clock selection of the driving source is controlled by the CrdCLKIN and the DE pins. An output enable pin OE, when high, forces all CLKOUT pins high. A backplane clock distribution network must be able to drive many transmission line stubs. The Bus LVDS feature of the PI90LVB16 is ideal for driving data transfers in large, high-performance backplane system applications. The device can be used as a source synchronous driver to distribute clock signals within data and telecommunications systems. Driver Mode Truth Table Input OE DE CrdCLKIN CLKI/O+ Output CLKI/O H L H L Z CLKOUT L H Receive Mode Truth Table Input Output OE DE CrdCLKIN CLKI/O+ CLKI/O CLKOUT VID 0.07V VID 0.07V L = Low Logic State H = High Logic State X = Irrelevant Z = High Impedance Function Diagram OE CLKI/0+ Delay CLKOUT0 CLKOUT1 CLKOUT5 DE CrdCLKIN PS8536A 05/21/01 PI90LVB16 3V Bus LVDS 1-to-6 Connection Diagram VCCA GNDA CLKI/0+ GNDA CrdCLKIN NC 10 DE 11 GND 12 24-Pin L CLKOUT0 22 GND CLKOUT1 CLKOUT2 Ordering Information Ordering Code Package Name PI90LVB16L Package Type 24-pin TSSOP Operating Range 40°C to 85°C Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax 408 435-1100 • PS8536A 05/21/01

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PI90LVB16
3V Bus LVDS 1-to-6 Clock Buffer/Bus Transceiver

Master/Slave clock selection in a backplane application 160 MHz operation typical 100ps duty cycle distortion typical 50ps channel to channel skew typical 3.3V power supply design Glitch-free power on at CLKI/O pins Low Power design 16mA 3.3V static Accepts small swing 300mV typical differential signal levels Industrial temperature operating range 40°C to +85°C Available in 24-pin TSSOP Packaging L

PI90LVB16 is a six-channel LVTTL clock distribution driver with 50 picosecond channel-to-channel skew. It translates one BLVDS Bus Low-Voltage Differential Signaling input signal into six LVTTLcompatible output signals for distribution to adjacent chips on the same board. The PI90LVB16 accepts BLVDS 300mV typical differential input levels, and translates them to 3V CMOS output levels.

The 160MHz PI90LVB16 can be the master clock, driving inputs of other clock I/O pins in a multipoint environment. It can also drive the BLVDS backplane with a separate channel acting as a return/ source LVTTL clock source. The master/slave clock selection of the driving source is controlled by the CrdCLKIN and the DE pins. An output enable pin OE, when high, forces all CLKOUT pins high.

A backplane clock distribution network must be able to drive many transmission line stubs. The Bus LVDS feature of the PI90LVB16 is ideal for driving data transfers in large, high-performance backplane system applications. The device can be used as a source synchronous driver to distribute clock signals within data and telecommunications systems.

Driver Mode Truth Table

Input

OE DE CrdCLKIN CLKI/O+

Output CLKI/O

H L H L Z

CLKOUT L H

Receive Mode Truth Table

Input

Output

OE DE CrdCLKIN CLKI/O+ CLKI/O CLKOUT

VID 0.07V

VID 0.07V

L = Low Logic State H = High Logic State X = Irrelevant Z = High Impedance

Function Diagram

OE CLKI/0+

Delay

CLKOUT0 CLKOUT1

CLKOUT5

DE CrdCLKIN

PS8536A 05/21/01

PI90LVB16 3V Bus LVDS 1-to-6

Connection Diagram

VCCA

GNDA

CLKI/0+

GNDA

CrdCLKIN

NC 10

DE 11

GND 12
24-Pin L

CLKOUT0
22 GND

CLKOUT1

CLKOUT2
Ordering Information Ordering Code Package Name

PI90LVB16L

Package Type 24-pin TSSOP

Operating Range 40°C to 85°C

Pericom Semiconductor Corporation 2380 Bering Drive
• San Jose, CA 95131
• 1-800-435-2336
• Fax 408 435-1100
•

PS8536A 05/21/01

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived PI90LVB16L Datasheet file may be downloaded here without warranties.

Datasheet ID: PI90LVB16L 510111