PI74SSTVF32852ANBE
PI74SSTVF32852ANBE Datasheet
PI74SSTVF32852A
| Part | Datasheet |
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PI74SSTVF32852ANBE |
PI74SSTVF32852ANBE (pdf) |
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| PI74SSTVF32852A 24-Bit to 48-Bit Registered Buffer Product Features • PI74 SSTVF32852A is designed for low-voltage operation, 2.5V for PC1600 ~ PC2700 2.6V for PC3200 • Supports SSTL_2 Class I specifications on outputs • All Inputs are SSTL_2 Compatible, except RESET which is LVCMOS. • Designed for DDR Memory • Packaging:114-BallLFBGA • Pb-free available Logic Block Diagram A3 CLK A4 CLK RESET R3 T2 D1 R4 VREF R CLK A2 Q1A A5 Q1B TO 23 OTHER CHANNELS Product Pin Description Pin Name RESET Reset Active Low LVCMOS Clock Input, Positive Differential Input Clock Input, Negative Differential Input Data Input Data Output Ground VDD VDDQ VREF Core Supply Voltage, 2.5V Nominal Output Supply Voltage, 2.5V Nominal Input Reference Voltage, 1.25V Nominal Product Description Pericom Semiconductor’s PI74SSTVF32852A logic circuit is produced using the Company’s advanced sub-micron CMOS technology, achieving industry leading speed. All inputs are compatible with the JEDEC standard for SSTL_2, except the LVCMOS reset input. All outputs are SSTL_2, Class II compatible. The device operates from a differential clock CK and CK . Data registered at the crossing of CK going HIGH, and CK going LOW. The PI74SSTVF32852A supports low-power standby operation. When RESET is LOW, the differential input receivers are disabled, and undriven floating data, clock and reference voltage VREF inputs are allowed. In addition, when RESET is LOW, all registers are reset, and all outputs are forced LOW. The LVCMOS RESET input must always be held at a valid logic HIGH or LOW level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the LOW state during power up. In the DDR DIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering RESET, the register will be cleared and the outputs will be driven LOW quickly, relative to the time to disable the differential input receivers, thus ensuring no glitches on the output. However, when coming out of RESET, the register will become active quickly, relative to the time to enable the differential input receivers. When the data inputs are LOW, and the clock is stable, during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the design must ensure that the outputs will remain LOW. Pericom’s PI74SSTVF32852A is characterized for operation from 0° to 70°C. Truth Table 1 Inputs Outputs RESET X or Floating X or Floating X or Floating Ordering Information Ordering Code Package Code Package Type PI74SSTVF32852ANB 114-Ball LFBGA Notes Thermal characteristics can be found on the company web site at Pericom Semiconductor Corporation 2380BeringDrive • SanJose,CA95131•1-800-435-2336 • Fax 408 435-1100• 08-0291 PS8682A 11/10/08 |
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