PI74SSTU32864ANBE

PI74SSTU32864ANBE Datasheet

PI74SSTU32864A

Part	Datasheet
PI74SSTU32864ANBE	PI74SSTU32864ANBE (pdf)

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PI74SSTU32864A 25-Bit 1:1 or 14-Bit 1:2 Configurable Registered Buffer • PI74SSTU32864A is designed for low-voltage operation, VDD = 1.8V • Supports Low Power Standby Operation • Enhanced Signal Integrity for 1 and 2 Rank Modules • All Inputs are SSTL_18 Compatible, except RST, C0, C1, which are LVCMOS. • Output drivers are optimized to drive DDR2 DIMM loads • Designed for DDR2 Memory • Packaging Pb-free & Green available : -96 Ball LFBGA NB Block Diagram 1:2 Mode Positive Logic VREF DCKE DODT 1D C1 1D C1 1D C1 QCKEA QCKEB* QODTA QODTB* QCSA QCSB* Q1B* TO OTHER CHANNELS Note Disabled in 1:1 configuration Pericom Semiconductor’s PI74SSTU32864A logic circuit is produced using advanced CMOS technology. This 25-Bit 1:1 or 14-Bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8V LVCMOS drivers that have been optimized to drive the DDR2 DIMM load. The SSTU32864A operates from a differential clock CK and CK . Data is registered at the crossing of CK going high, and CK going low. The C0 input controls the pinout configuration of the 1:2 pinout from A configuration when LOW to B configuration when HIGH . The C1 input controls the pinout configuration for 25-Bit 1:1 when LOW to 14-Bit 1:2 when HIGH . The device supports low-power standby operation. When the reset input RST is low, the differential input receivers are disabled and undriven floating data, clock and reference voltage VREF inputs are allowed. In addition , when RST is low, all registers are reset, and all outputs are forced low. The LVCMOS RST and Cn inputs must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RST must be held in the low state during power up. In the DDR-II RDIMM application, RST is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RST until the input receivers are fully enabled, the design of the SSTU32864A must ensure that the outputs remain low, thus ensuring no glitches on the output. The device monitors both DCS and CSR inputs and will gate the Qn outputs from changing states when both DCS and CSR inputs are high. If either DCS or CSR input is low, the Qn outputs will function normally. The RST input has priority over the DCS and CSR control will force the outputs low. If the DCS control functionality is not desired, then the CSR input can be hardwired to ground, in which case, the set-up time requirement for DCS would be the same as for the other D data inputs. PS8743 08/02/04 Pin Configuration 1:1 Register C0 = 0, C1 = 0 A DCKE NC VREF VDD QCKE NC D15 GND D DODT NC GND QODT NC D18 GND RST VDD CK DCS GND QCS CSR VDD ZOH D19 GND D10 D21 GND Q10 D12 D23 GND Q12 D25 VREF VDD Pin Configuration 1:2 Register C0 = 0, C1 = 1 Ordering Information Ordering Code Package Code Package Type PI74SSTU32864ANB 96-Ball LFBGA PI74SSTU32864ANBE Pb-free & Green, 96-Ball LFBGA Notes Thermal characteristics can be found on the company web site at Number of Transistors = TBD Pericom Semiconductor Corporation • 1-800-435-2336 • 10 PS8743 08/02/04

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PI74SSTU32864A
25-Bit 1:1 or 14-Bit 1:2 Configurable Registered Buffer
• PI74SSTU32864A is designed for low-voltage operation, VDD = 1.8V
• Supports Low Power Standby Operation
• Enhanced Signal Integrity for 1 and 2 Rank Modules
• All Inputs are SSTL_18 Compatible, except RST, C0, C1,
which are LVCMOS.
• Output drivers are optimized to drive DDR2 DIMM loads
• Designed for DDR2 Memory
• Packaging Pb-free & Green available :
-96 Ball LFBGA NB

Block Diagram 1:2 Mode Positive Logic

VREF

DCKE

DODT
1D C1
1D C1
1D C1

QCKEA QCKEB* QODTA QODTB* QCSA QCSB*

Q1B*

TO OTHER CHANNELS

Note Disabled in 1:1 configuration

Pericom Semiconductor’s PI74SSTU32864A logic circuit is produced using advanced CMOS technology. This 25-Bit 1:1 or 14-Bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation.

All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8V LVCMOS drivers that have been optimized to drive the DDR2 DIMM load.

The SSTU32864A operates from a differential clock CK and CK . Data is registered at the crossing of CK going high, and CK going low.

The C0 input controls the pinout configuration of the 1:2 pinout from A configuration when LOW to B configuration when HIGH . The C1 input controls the pinout configuration for 25-Bit 1:1 when LOW to 14-Bit 1:2 when HIGH .

The device supports low-power standby operation. When the reset input RST is low, the differential input receivers are disabled and undriven floating data, clock and reference voltage VREF inputs are allowed. In addition , when RST is low, all registers are reset, and all outputs are forced low. The LVCMOS RST and Cn inputs must always be held at a valid logic high or low level.

To ensure defined outputs from the register before a stable clock has been supplied, RST must be held in the low state during power up.

In the DDR-II RDIMM application, RST is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers.

As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RST until the input receivers are fully enabled, the design of the SSTU32864A must ensure that the outputs remain low, thus ensuring no glitches on the output.

The device monitors both DCS and CSR inputs and will gate the Qn outputs from changing states when both DCS and CSR inputs are high. If either DCS or CSR input is low, the Qn outputs will function normally. The RST input has priority over the DCS and CSR control will force the outputs low. If the DCS control functionality is not desired, then the CSR input can be hardwired to ground, in which case, the set-up time requirement for DCS would be the same as for the other D data inputs.

PS8743
08/02/04

Pin Configuration 1:1 Register C0 = 0, C1 = 0

A DCKE NC VREF VDD QCKE NC

D15 GND

D DODT NC GND QODT NC

D18 GND

RST VDD

CK DCS GND QCS

CSR VDD ZOH

D19 GND

D10 D21 GND Q10

D12 D23 GND Q12

D25 VREF VDD

Pin Configuration 1:2 Register C0 = 0, C1 = 1
Ordering Information
Ordering Code

Package Code

Package Type

PI74SSTU32864ANB
96-Ball LFBGA

PI74SSTU32864ANBE

Pb-free & Green, 96-Ball LFBGA

Notes Thermal characteristics can be found on the company web site at Number of Transistors = TBD

Pericom Semiconductor Corporation
• 1-800-435-2336
• 10

PS8743
08/02/04

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Datasheet ID: PI74SSTU32864ANBE 510100