PI74ALVCH16646A

PI74ALVCH16646A Datasheet

PI74ALVCH16646

Part	Datasheet
PI74ALVCH16646A	PI74ALVCH16646A (pdf)

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PI74ALVCH16646 Product Features 16-Bit Bus Transceiver and Register with 3-STATE Outputs Product Description • PI74ALVCH16646 is designed for low voltage operation • VCC = 2.3V to 3.6V • Hysteresis on all inputs • Typical VOLP Output Ground Bounce < 0.8V at VCC = 3.3V, TA = 25°C • Typical VOHV Output VOH Undershoot < 2.0V at VCC = 3.3V, TA = 25°C • Bus Hold retains last active bus state during 3-STATE, eliminating the need for external pullup resistors • Industrial operation at 40°C to +85°C • Packages available: 56-pin 240 mil wide plastic TSSOP A 56-pin 300 mil wide plastic SSOP V Pericom Semiconductors PI74ALVCH series of logic circuits are produced in the Companys advanced micron CMOS technology, achieving industry leading speed. The PI74ALVCH16646 is a 16-bit bus transceiver and register designed for 2.3V to 3.6V VCC operation. It can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate Clock CLKAB or CLKBA input. Four fundamental bus-management functions can be performed. Output Enable OE and Direction Control DIR inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The Select Control SAB and SBA inputs can multiplex stored and real-time transparent mode data. Circuitry used for Select Control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. DIR determines which bus receives data when OE is LOW. In the isolation mode OE HIGH , A data may be stored in one register and/or B data may be stored in the other register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, can be driven at a time. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor the minimum value of the resistor is determined by the current-sinking capability of the driver. Logic Block Diagram Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. PS8102A 10/07/98 PI74ALVCH16646 16-Bit Bus Transceiver and Register with 3-STATE Outputs Product Pin Configuration 1DIR 1CLKAB 1SAB GND 1A1 1A2 VCC 1A3 1A4 1A5 GND 1A6 1A7 1A8 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2SAB 2CLKAB 2DIR 6 56-PIN 51 7 V56 50 8 A56 49 1OE 1CLKBA 1SBA GND 1B1 1B2 VCC 1B3 1B4 1B5 GND 1B6 1B7 1B8 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2SBA 2CLKBA 2OE Product Pin Description Pin Name Output Enable Inputs Active LOW xDIR Direction Control xCLKAB, xCLKBA Clock Pulse Inputs xSAB, xSBA Select Control Inputs Data Register A Inputs Data Register B Outputs Data Register B Inputs Data Register A Outputs Ground Power Truth Table 2 Function Store A, B Unspecified 1 Store B, A Unspecified 1 Isolation Store A and B Data Real Time A Data to B Bus Stored A Data to B Bus Real Time B Data to A Bus Stored B Data to A Bus Inputs Data I/O

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PI74ALVCH16646

Product Features
16-Bit Bus Transceiver and Register with 3-STATE Outputs

Product Description
• PI74ALVCH16646 is designed for low voltage operation
• VCC = 2.3V to 3.6V
• Hysteresis on all inputs
• Typical VOLP Output Ground Bounce
< 0.8V at VCC = 3.3V, TA = 25°C
• Typical VOHV Output VOH Undershoot
< 2.0V at VCC = 3.3V, TA = 25°C
• Bus Hold retains last active bus state during 3-STATE,
eliminating the need for external pullup resistors
• Industrial operation at 40°C to +85°C
• Packages available:
56-pin 240 mil wide plastic TSSOP A 56-pin 300 mil wide plastic SSOP V

Pericom Semiconductors PI74ALVCH series of logic circuits are produced in the Companys advanced micron CMOS technology, achieving industry leading speed.

The PI74ALVCH16646 is a 16-bit bus transceiver and register designed for 2.3V to 3.6V VCC operation. It can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate Clock CLKAB or CLKBA input. Four fundamental bus-management functions can be performed.

Output Enable OE and Direction Control DIR inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The Select Control SAB and SBA inputs can multiplex stored and real-time transparent mode data. Circuitry used for Select Control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. DIR determines which bus receives data when OE is LOW. In the isolation mode OE HIGH , A data may be stored in one register and/or B data may be stored in the other register.

When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, can be driven at a time.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor the minimum value of the resistor is determined by the current-sinking capability of the driver.

Logic Block Diagram

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

PS8102A 10/07/98

PI74ALVCH16646 16-Bit Bus Transceiver and Register with 3-STATE Outputs

Product Pin Configuration
1DIR 1CLKAB
1SAB GND
1A1 1A2 VCC 1A3 1A4 1A5 GND 1A6 1A7 1A8 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2SAB 2CLKAB 2DIR
6 56-PIN 51 7 V56 50
8 A56 49
1OE 1CLKBA 1SBA GND 1B1 1B2 VCC 1B3 1B4 1B5 GND 1B6 1B7 1B8 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2SBA 2CLKBA 2OE

Product Pin Description

Pin Name

Output Enable Inputs Active LOW
xDIR

Direction Control
xCLKAB, xCLKBA Clock Pulse Inputs
xSAB, xSBA

Select Control Inputs

Data Register A Inputs Data Register B Outputs

Data Register B Inputs Data Register A Outputs

Ground

Power

Truth Table 2

Function Store A, B Unspecified 1 Store B, A Unspecified 1 Isolation Store A and B Data Real Time A Data to B Bus Stored A Data to B Bus Real Time B Data to A Bus Stored B Data to A Bus

Inputs

Data I/O

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Datasheet ID: PI74ALVCH16646A 510092