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6003-210-012P (pdf) |
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FMC-CE Hardware User Guide UG-FMC-CE v1.1 August 23, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification the "Documentation" to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information. THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION. Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. Date 2/26/10 3/10/10 8/23/10 Version v0.9.0 v1.0 v1.1 Contents About This Guide FMC-CE Features Appendix A UCF for SP605 10 Appendix B UCF for ML605 13 Appendix C VITA FMC LPC J63 and HPC J64 Connector Pinout 18 Table of Tables Table Slide Switch FMC connections Table Linear LED Connections Table Button FMC Table FMC Connections for LEDs Adjacent to Push Table Rotary Switch FMC Table LCD FMC Table Audio FMC Table SMA FMC Table Leftmost PMOD FMC Connections Table Center PMOD FMC Connection Table Rightmost PMD FMC Table of Figures Figure FMC-CE Card with Features Figure Slide Switch Figure Schematic of LEDs for Both the Linear Array and Rosetta Figure Schematic for Buttons Figure Rotary Switch Schematic Figure SMA Schematics About This Guide The purpose is of this document is to convey the necessary information to the designer to successfully use the capabilities of the FMC-CE I/O expansion card. Each feature is independently described and contains a connection table. This table includes the name of the signal, its location on the FMC, the voltage at which it must be programmed by the FPGA, and a brief description of its function. Where the term “any” is provided, the FPGA may provide use voltage as the FPGAs signals are passed directly to the device and not through any level shifter. FMC-CE Card Overview The FMC-CE card is meant to be used with a Xilinx demonstration/evaluation board equipped with an FMC connector. This board extends the I/O capabilities of the base platform and provides an I/O consistency among various platforms. Figure FMC-CE Card with Features Annotated The FMC-CE card provides the following features 1 Linear array of 8 slide switches 2 Linear array of 8 LEDs co-located with the 8 slide switches 3 Rosetta pattern of 5 push button switches 4 Rosetta pattern of 5 LEDs, co-located with the push button switches 5 A Rotary/push-button switch 6 An LCD display 2x16 . 7 Headphone jack 7a , speaker jack 7b with a volume control 7c . 8 4 SMA connectors 9 2 Digilent dual PMOD connectors 9a , 1 Digilent single PMOD connector 9b Detailed Description 8 Slide switches One side of each of the eight slide switches is tied to GND, while the other side is pulled up to 2.5V. There is a 10K series resistor for each switch which enables these signals to be used at lower voltages without damaging the FPGA. These switches are silkscreened SW0-SW7. SW0 is on the right most side. Figure Slide Switch Schematics Signal Name Switch 0 Switch 1 Switch 2 Switch 3 Switch 4 Switch 5 Switch 6 Switch 7 Pin Voltage Table Slide Switch FMC connections There are 8 LED's in a linear fashion, co-located with the slide switches. Each is tied to GND through a 300 Ohm resistor. LD0 is on the right most side. The LEDs illuminate with voltages as low as LVCMOS12. Figure Schematic of LEDs for Both the Linear Array and Rosetta Array Signal Name LED linear 0 LED linear 1 LED linear 2 LED linear 3 LED linear 4 LED linear 5 LED linear 6 LED linear 7 Pin Voltage any Voltage must be sufficient to |
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