W40S11-02H

W40S11-02H Datasheet

W40S11-02

Part	Datasheet
W40S11-02H	W40S11-02H (pdf)

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W40S11-02 SDRAM Buffer - 2 DIMM Mobile • Ten skew-controlled CMOS outputs SDRAM0:9 • Supports two SDRAM DIMMs • Ideal for high-performance systems designed around latest Mobile chip set • I2C Serial configuration interface • Skew between any two outputs is less than 250 ps • 1 to 5 ns propagation delay • DC to 133-MHz operation • Single 3.3V supply voltage • Low power CMOS design packaged in a 28-pin, 209-mil SSOP Shrink Small Outline Package Overview The Cypress W40S11-02 is a low-voltage, ten-output clock buffer. Output buffer impedance is approximately which is ideal for driving SDRAM DIMMs. Key Specifications Supply VDD = 3.3V±5% Operating 0°C to +70°C Input Threshold 1.5V typical Maximum Input Voltage + 0.5V Input 0 to 133 MHz BUF_IN to SDRAM0:9 Propagation Delay to ns Output Edge V/ns Output Skew ±250 ps Output Duty Cycle 45/55% worst case Output Impedance ohms typical Output Type CMOS rail-to-rail Block Diagram Pin Configuration SDATA SCLOCK Serial Port Device Control BUF_IN OE SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8 SDRAM9 VDD 1 SDRAM0 2 SDRAM1 3 GND 4 VDD 5 SDRAM2 6 SDRAM3 7 GND 8 BUF_IN 9 VDD 10 SDRAM8 11 GND 12 VDD 13 SDATA [1] 14 28 VDD 27 SDRAM7 26 SDRAM6 25 GND 24 VDD 23 SDRAM5 22 SDRAM4 21 GND 20 OE [1] 19 VDD 18 SDRAM9 17 GND 16 GND 15 SCLOCK[1] Note: Internal pull-up resistor of 250K on SDATA, SCLOCK, and OE inputs should not be relied upon for pulling up to VDD . Intel is a registered trademark of Intel Corporation. W40S11-02 Pin Definitions Pin Name SDRAM0:9 BUF_IN SDATA Pin No. 2, 3, 6, 7, 22, 23, 26, 27, 11, 18 SCLOCK VDD GND OE 1, 5, 10, 13, 19, 24, 28 4, 8, 12, 16, 17, 21, 25 Pin Type I P G I Pin Description SDRAM Outputs Provides buffered copy of BUF_IN. The propagation delay from a rising input edge to a rising output edge is 1 to 5 ns. All outputs are skew controlled to within ± 250 ps of each other. Clock Input This clock input has an input threshold voltage of 1.5V typ . I2C Data Input Data should be presented to this input as described in the I2C section of this data sheet. Internal pull-up resistor. I2C Clock Input The I2C Data clock should be presented to this input as described in the I2C section of this data sheet. Internal pull-up resistor. Power Connection Power supply for core logic and output buffers. Connected to 3.3V supply. Ground Connection Connect all ground pins to the common system ground plane. Output Enable Internal pull-up resistor. Three-states outputs when LOW. W40S11-02 Functional Description Ordering Information Ordering Code Freq. Mask Code W40S11 Document # 38-00805 Package Name Package Type 28-pin SSOP 209-mil 28-pin TSSOP 173-mil Package Diagrams 28-Pin Shrink Small Outline Package TSSOP, 173-mil W40S11-02 Package Diagrams continued 28-Pin Small Shrink Outline Package SSOP, 209 mils W40S11-02 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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W40S11-02

SDRAM Buffer - 2 DIMM Mobile
• Ten skew-controlled CMOS outputs SDRAM0:9
• Supports two SDRAM DIMMs
• Ideal for high-performance systems designed around
latest Mobile chip set
• I2C Serial configuration interface
• Skew between any two outputs is less than 250 ps
• 1 to 5 ns propagation delay
• DC to 133-MHz operation
• Single 3.3V supply voltage
• Low power CMOS design packaged in a 28-pin, 209-mil

SSOP Shrink Small Outline Package

Overview

The Cypress W40S11-02 is a low-voltage, ten-output clock buffer. Output buffer impedance is approximately which is ideal for driving SDRAM DIMMs.

Key Specifications

Supply VDD = 3.3V±5% Operating 0°C to +70°C Input Threshold 1.5V typical Maximum Input Voltage + 0.5V Input 0 to 133 MHz BUF_IN to SDRAM0:9 Propagation Delay to ns Output Edge V/ns Output Skew ±250 ps Output Duty Cycle 45/55% worst case Output Impedance ohms typical Output Type CMOS rail-to-rail

Block Diagram

Pin Configuration

SDATA SCLOCK

Serial Port

Device Control

BUF_IN

OE SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8 SDRAM9

VDD 1 SDRAM0 2 SDRAM1 3

GND 4 VDD 5 SDRAM2 6 SDRAM3 7 GND 8 BUF_IN 9 VDD 10 SDRAM8 11 GND 12 VDD 13 SDATA [1] 14
28 VDD 27 SDRAM7 26 SDRAM6 25 GND 24 VDD 23 SDRAM5 22 SDRAM4 21 GND 20 OE [1] 19 VDD 18 SDRAM9 17 GND 16 GND 15 SCLOCK[1]

Note:

Internal pull-up resistor of 250K on SDATA, SCLOCK, and OE inputs should not be relied upon for pulling up to VDD .

Intel is a registered trademark of Intel Corporation.

W40S11-02

Pin Definitions

Pin Name SDRAM0:9

BUF_IN SDATA

Pin No.
2, 3, 6, 7, 22, 23, 26, 27, 11, 18

SCLOCK

VDD GND OE
1, 5, 10, 13, 19, 24, 28
4, 8, 12, 16, 17, 21, 25

Pin Type

I P G I

Pin Description

SDRAM Outputs Provides buffered copy of BUF_IN. The propagation delay from a rising input edge to a rising output edge is 1 to 5 ns. All outputs are skew controlled to within ± 250 ps of each other.

Clock Input This clock input has an input threshold voltage of 1.5V typ . I2C Data Input Data should be presented to this input as described in the I2C section of this data sheet. Internal pull-up resistor. I2C Clock Input The I2C Data clock should be presented to this input as described in the I2C section of this data sheet. Internal pull-up resistor. Power Connection Power supply for core logic and output buffers. Connected to 3.3V supply.

Ground Connection Connect all ground pins to the common system ground plane.

Output Enable Internal pull-up resistor. Three-states outputs when LOW.

W40S11-02

Functional Description
Ordering Information
Ordering Code

Freq. Mask Code

W40S11

Document # 38-00805

Package Name

Package Type
28-pin SSOP 209-mil 28-pin TSSOP 173-mil

Package Diagrams
28-Pin Shrink Small Outline Package TSSOP, 173-mil

W40S11-02

Package Diagrams continued
28-Pin Small Shrink Outline Package SSOP, 209 mils

W40S11-02

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived W40S11-02H Datasheet file may be downloaded here without warranties.

Datasheet ID: W40S11-02H 508355