STK12C68-5K35M
STK12C68-5K35M Datasheet
STK12C68-5 SMD5962-94599
| Part | Datasheet |
|---|---|
STK12C68-5K35M |
STK12C68-5K35M (pdf) |
| Related Parts | Information |
|---|---|
STK12C68-5K55M |
STK12C68-5K55M |
| PDF Datasheet Preview |
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| STK12C68-5 SMD5962-94599 64 Kbit 8K x 8 AutoStore nvSRAM • 35 ns and 55 ns access times • Hands off automatic STORE on power down with external 68 µF capacitor • STORE to QuantumTrap nonvolatile elements is initiated by software, hardware, or AutoStore on power down • RECALL to SRAM initiated by software or power up • Unlimited Read, Write, and Recall cycles • 1,000,000 STORE cycles to QuantumTrap • 100 year data retention to QuantumTrap • Single 5V+10% operation • Military temperature • 28-pin 300mil CDIP and 28-pad LCC packages Functional Description The Cypress STK12C68-5 is a fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world’s most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements the STORE operation takes place automatically at power down. On power up, data is restored to the SRAM the RECALL operation from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control. A hardware STORE is initiated with the HSB pin. Logic Block Diagram A5 A6 A7 A8 A9 A 11 A 12 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 INPUT BUFFERS ROW DECODER Quantum Trap 128 X 512 STORE STATIC RAM ARRAY 128 X 512 RECALL COLUMN I/O COLUMN DEC A0 A1 A2 A3 A4 A10 VCAP POWER CONTROL STORE/ RECALL CONTROL SOFTWARE DETECT - A0 A12 CE WE • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Pinouts Figure Pin Diagram - 28-Pin DIP STK12C68-5 SMD5962-94599 Figure Pin Diagram - 28-Pin LLC Pin Definitions Pin Name Alt IO Type DQ0-DQ7 Input Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM. Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation. Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO pins is written to the specific address location. Input Ordering Information Speed ns Ordering Code Package Diagram Package Type STK12C68-5C35M STK12C68-5K35M 001-51695 001-51695 28-pin CDIP 300 mil 28-pin CDIP 300 mil STK12C68-5L35M 001-51696 28-pin LCC 350 mil STK12C68-5C55M 001-51695 28-pin CDIP 300 mil STK12C68-5K55M 001-51695 28-pin CDIP 300 mil STK12C68-5L55M 001-51696 28-pin LCC 350 mil The above table contains Final information. Contact your local Cypress sales representative for availability of these parts Operating Range Military Page 15 of 18 [+] Feedback Package Diagrams STK12C68-5 SMD5962-94599 Figure 28-Pin 300-Mil Side Braze DIL 001-51695 001-51695 ** Page 16 of 18 [+] Feedback STK12C68-5 SMD5962-94599 Package Diagrams continued Figure 28-Pad 350-Mil LCC 001-51696 ALL DIMENSION ARE IN INCHES AND MILLIMETERS [MIN/MAX] JEDEC 95 OUTLINE# MO-041 PACKAGE WEIGHT TBD 001-51696 ** Page 17 of 18 [+] Feedback STK12C68-5 SMD5962-94599 Document History Page Document Title STK12C68-5 SMD5962-94599 , 64 Kbit 8K x 8 AutoStore nvSRAM Document Number 001-51026 Orig. of Change Submission Date Description of Change 2666844 GVCH/PYRS 03/02/09 New data sheet Sales, Solutions, and Legal Information |
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