5962-9232404MYA

5962-9232404MYA Datasheet

STK11C68-5 SMD5962-92324

Part	Datasheet
5962-9232404MYA	5962-9232404MYA (pdf)

Related Parts	Information
5962-9232406MYA	5962-9232406MYA
5962-9232404MXA	5962-9232404MXA

PDF Datasheet Preview
STK11C68-5 SMD5962-92324 64 Kbit 8 K x 8 SoftStore nvSRAM • 35 ns, 45 ns, and 55 ns access times • Pin compatible with industry standard SRAMs • Software initiated nonvolatile STORE • Unlimited Read and Write endurance • Automatic RECALL to SRAM on power-up • Unlimited RECALL cycles • 1,000,000 STORE cycles • 100 year data retention • Single 5 V ± 10% operation • Military temperature • 28-pin 300 mil CDIP and 28-pad LCC packages Functional Description The Cypress STK11C68-5 is a 64 Kb fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap technology to produce the world’s most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers under software control from SRAM to the nonvolatile elements the STORE operation . On power-up, data is automatically restored to the SRAM the RECALL operation from the nonvolatile memory. RECALL operations are also available under software control. For a complete list of related documentation, click here. Logic Block Diagram A5 A6 A7 A8 A9 A 11 A 12 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 INPUT BUFFERS ROW DECODER Quantum Trap 128 X 512 STORE STATIC RAM ARRAY 128 X 512 RECALL COLUMN I/O COLUMN DEC A0 A1 A2 A3 A4 A10 VCAP POWER CONTROL STORE/ RECALL CONTROL SOFTWARE DETECT - A0 A12 CE WE • San Jose, CA 95134-1709 • 408-943-2600 STK11C68-5 SMD5962-92324 Contents Pinouts 3 Pin Definitions 3 Device Operation 4 SRAM Read 4 SRAM Write 4 Software STORE 4 Software 4 Hardware RECALL Power 4 Hardware 4 Noise 4 Low Average Active 5 Best 5 Maximum 6 Operating Range 6 DC Electrical Characteristics 6 Data Retention and Endurance 6 Capacitance 6 Thermal 7 AC Test Conditions 7 SRAM Read Cycle 8 SRAM Write 9 AutoStore INHIBIT or Power Up RECALL 10 Software Controlled STORE/RECALL Cycle................ 11 Part Numbering 12 Ordering 13 Acronyms 16 Document Conventions 16 Units of Measure 16 Document History Page 17 Sales, Solutions, and Legal Information 18 Worldwide Sales and Design Support....................... 18 Products 18 PSoC Solutions 18 Page 2 of 18 Pinouts Figure Pin Diagram - 28-Pin CDIP NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VCC WE NC A8 A9 A 11 OE A 10 CE DQ 7 DQ 6 DQ 5 DQ4 DQ3 STK11C68-5 SMD5962-92324 Figure Pin Diagram - 28-Pin LCC Pin Definitions Pin Name Alt DQ0-DQ7 VSS VCC I/O Type Input Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM. Input/Output Bidirectional Data I/O Lines. Used as input or output lines depending on operation. Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written to the specific address location. Input Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. Deasserting OE HIGH causes the I/O pins to tristate. Ground for the Device. The device is connected to ground of the system. Power Supply Power Supply Inputs to the Device. Page 3 of 18 STK11C68-5 SMD5962-92324 Device Operation The STK11C68-5 SMD5962-92324 is a versatile memory chip that provides several modes of operation. The STK11C68-5 SMD5962-92324 can operate as a standard 8K x 8 SRAM. It has an 8K x 8 Nonvolatile Elements shadow to which the SRAM information can be copied or from which the SRAM can be updated in nonvolatile mode. SRAM Read The STK11C68-5 SMD5962-92324 performs a Read cycle whenever CE and OE are LOW while WE is HIGH. The address specified on pins determines the 8,192 data bytes accessed. When the Read is initiated by an address transition, the outputs are valid after a delay of tAA Read cycle If the Read is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later Read cycle The data outputs repeatedly respond to address changes within the tAA access time without the need for transitions on any control input pins. They remain valid until another address change or until CE or OE is brought HIGH, or WE is brought LOW. SRAM Write A Write cycle is performed whenever CE and WE are LOW. The address inputs must be stable before entering the Write cycle and must remain stable until either CE or WE goes HIGH at the end of the cycle. The data on the common I/O pins are written into the memory if it has valid tSD. This is done before the end of a WE controlled Write or before the end of an CE controlled Write. Keep OE HIGH during the entire Write cycle to avoid data bus contention on common I/O lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW. Software STORE Data is transferred from the SRAM to the nonvolatile memory by a software address sequence. The STK11C68-5 SMD5962-92324 software STORE cycle is initiated by executing sequential CE controlled Read cycles from six specific address locations in exact order. During the STORE cycle, an erase of the previous nonvolatile data is first performed followed by a program of the nonvolatile elements. When a STORE cycle is initiated, input and output are disabled until the cycle is completed. Because a sequence of Reads from specific addresses is used for STORE initiation, it is important that no other Read or Write accesses intervene in the sequence. If they intervene, the sequence is aborted and no STORE or RECALL takes place. To initiate the software STORE cycle, the following Read sequence is performed Read address 0x0000, Valid READ address 0x1555, Valid READ address 0x0AAA, Valid READ address 0x1FFF, Valid READ address 0x10F0, Valid READ address 0x0F0F, Initiate STORE cycle The software sequence is clocked with CE controlled Reads. When the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. It is important that Read cycles and not Write cycles are used in the sequence. It is not necessary that OE is LOW for a valid sequence. After the tSTORE cycle time is fulfilled, the SRAM is again activated for Read and Write operation. Ordering Information Speed ns Ordering Code Package Diagram Package Type STK11C68-5L35M 001-51696 28-Pin LCC 350 mil STK11C68-5C55M 001-51695 28-Pin CDIP 300 mil This table contains Final information. Contact your local Cypress sales representative for availability of these parts. Operating Range Military Page 13 of 18 STK11C68-5 SMD5962-92324 Package Diagrams Figure 28-Pin 300-Mil Side Braze DIP 001-51695 001-51695 C Page 14 of 18 STK11C68-5 SMD5962-92324 Package Diagrams continued Figure 28-Pad 350-Mil LCC 001-51696 001-51696 C Page 15 of 18 STK11C68-5 SMD5962-92324 Acronyms Acronym CE CMOS I/O I/O nvSRAM OE SRAM TTL WE Description chip enable complementary metal oxide semiconductor input/output input/output nonvolatile static random access memory output enable static random access memory transistor-transistor logic write enable Document Conventions Units of Measure Symbol °C mA ms ns pF V Unit of Measure degrees Celsius kilohm microampere milliampere microfarad microsecond millisecond nanosecond picofarad volt ohm watt Page 16 of 18 STK11C68-5 SMD5962-92324 Document History Page Document Title STK11C68-5 SMD5962-92324 64 Kbit 8 K x 8 SoftStore nvSRAM Document Number 001-51001 ECN No. Orig. of Change Submission Date Description of Change 2666844 GVCH/PYRS 03/02/2009 New data sheet 2685053 GVCH Ordering Code Information table. Updated Package diagrams. 3527665 GVCH 4568935 GVCH 11/14/2014 Added documentation related hyperlink in page 1 Removed 02pruned parts - STK11C68-5K55M, STK11C68-5L55M Updated package diagrams from 001-51695A to 001-51695B and 001-51696A to 001-51696B 4706588 GVCH 04/02/2015 Updated package diagrams from 001-51695B to 001-51695C and 001-51696B to 001-51696C Page 17 of 18 STK11C68-5 SMD5962-92324 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 18 of 18 AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.

PDF Datasheet Preview

STK11C68-5 SMD5962-92324
64 Kbit 8 K x 8 SoftStore nvSRAM
• 35 ns, 45 ns, and 55 ns access times
• Pin compatible with industry standard SRAMs
• Software initiated nonvolatile STORE
• Unlimited Read and Write endurance
• Automatic RECALL to SRAM on power-up
• Unlimited RECALL cycles
• 1,000,000 STORE cycles
• 100 year data retention
• Single 5 V ± 10% operation
• Military temperature
• 28-pin 300 mil CDIP and 28-pad LCC packages

Functional Description

The Cypress STK11C68-5 is a 64 Kb fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap technology to produce the world’s most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers under software control from SRAM to the nonvolatile elements the STORE operation . On power-up, data is automatically restored to the SRAM the RECALL operation from the nonvolatile memory. RECALL operations are also available under software control. For a complete list of related documentation, click here.

Logic Block Diagram

A5 A6 A7 A8 A9 A 11 A 12

DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7

INPUT BUFFERS

ROW DECODER

Quantum Trap 128 X 512

STORE

STATIC RAM ARRAY 128 X 512

RECALL

COLUMN I/O COLUMN DEC

A0 A1 A2 A3 A4 A10

VCAP

POWER CONTROL

STORE/ RECALL CONTROL

SOFTWARE DETECT
- A0 A12

CE WE
• San Jose, CA 95134-1709
• 408-943-2600

STK11C68-5 SMD5962-92324

Contents

Pinouts 3 Pin Definitions 3 Device Operation 4 SRAM Read 4 SRAM Write 4 Software STORE 4 Software 4 Hardware RECALL Power 4 Hardware 4 Noise 4 Low Average Active 5 Best 5 Maximum 6 Operating Range 6 DC Electrical Characteristics 6 Data Retention and Endurance 6 Capacitance 6

Thermal 7 AC Test Conditions 7
SRAM Read Cycle 8 SRAM Write 9 AutoStore INHIBIT or Power Up RECALL 10 Software Controlled STORE/RECALL Cycle................ 11 Part Numbering 12 Ordering 13 Acronyms 16 Document Conventions 16 Units of Measure 16 Document History Page 17 Sales, Solutions, and Legal Information 18 Worldwide Sales and Design Support....................... 18 Products 18 PSoC Solutions 18

Page 2 of 18

Pinouts

Figure Pin Diagram - 28-Pin CDIP

NC A12 A7 A6 A5 A4

A3 A2

A1 A0 DQ0 DQ1 DQ2

VCC WE NC

A8 A9 A 11

OE A 10

CE DQ 7

DQ 6 DQ 5 DQ4 DQ3

STK11C68-5 SMD5962-92324

Figure Pin Diagram - 28-Pin LCC

Pin Definitions

Pin Name Alt

DQ0-DQ7

VSS VCC

I/O Type

Input

Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM.

Input/Output Bidirectional Data I/O Lines. Used as input or output lines depending on operation.

Input

Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written to the specific address location.

Input

Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.

Input

Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. Deasserting OE HIGH causes the I/O pins to tristate.

Ground for the Device. The device is connected to ground of the system.

Power Supply Power Supply Inputs to the Device.

Page 3 of 18

STK11C68-5 SMD5962-92324

Device Operation

The STK11C68-5 SMD5962-92324 is a versatile memory chip that provides several modes of operation. The STK11C68-5 SMD5962-92324 can operate as a standard 8K x 8 SRAM. It has an 8K x 8 Nonvolatile Elements shadow to which the SRAM information can be copied or from which the SRAM can be updated in nonvolatile mode.

SRAM Read

The STK11C68-5 SMD5962-92324 performs a Read cycle whenever CE and OE are LOW while WE is HIGH. The address specified on pins determines the 8,192 data bytes accessed. When the Read is initiated by an address transition, the outputs are valid after a delay of tAA Read cycle If the Read is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later Read cycle The data outputs repeatedly respond to address changes within the tAA access time without the need for transitions on any control input pins. They remain valid until another address change or until CE or OE is brought HIGH, or WE is brought LOW.

SRAM Write

A Write cycle is performed whenever CE and WE are LOW. The address inputs must be stable before entering the Write cycle and must remain stable until either CE or WE goes HIGH at the end of the cycle. The data on the common I/O pins are written into the memory if it has valid tSD. This is done before the end of a WE controlled Write or before the end of an CE controlled Write. Keep OE HIGH during the entire Write cycle to avoid data bus contention on common I/O lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW.

Software STORE

Data is transferred from the SRAM to the nonvolatile memory by a software address sequence. The STK11C68-5 SMD5962-92324 software STORE cycle is initiated by executing sequential CE controlled Read cycles from six specific address locations in exact order. During the STORE cycle, an erase of the previous nonvolatile data is first performed followed by a program of the nonvolatile elements. When a STORE cycle is initiated, input and output are disabled until the cycle is completed. Because a sequence of Reads from specific addresses is used for STORE initiation, it is important that no other Read or Write accesses intervene in the sequence. If they intervene, the sequence is aborted and no STORE or RECALL takes place. To initiate the software STORE cycle, the following Read sequence is performed Read address 0x0000, Valid READ address 0x1555, Valid READ address 0x0AAA, Valid READ address 0x1FFF, Valid READ address 0x10F0, Valid READ address 0x0F0F, Initiate STORE cycle

The software sequence is clocked with CE controlled Reads. When the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. It is important that Read cycles and not Write cycles are used in the sequence. It is not necessary that OE is LOW for a valid sequence. After the tSTORE cycle time is fulfilled, the SRAM is again activated for Read and Write operation.
Ordering Information

Speed ns
Ordering Code

Package Diagram

Package Type

STK11C68-5L35M
001-51696
28-Pin LCC 350 mil

STK11C68-5C55M
001-51695
28-Pin CDIP 300 mil

This table contains Final information. Contact your local Cypress sales representative for availability of these parts.

Operating Range Military

Page 13 of 18

STK11C68-5 SMD5962-92324

Package Diagrams

Figure 28-Pin 300-Mil Side Braze DIP 001-51695
001-51695 *C

Page 14 of 18

STK11C68-5 SMD5962-92324

Package Diagrams continued

Figure 28-Pad 350-Mil LCC 001-51696
001-51696 *C

Page 15 of 18

STK11C68-5 SMD5962-92324

Acronyms

Acronym CE CMOS I/O I/O nvSRAM OE SRAM TTL WE

Description chip enable complementary metal oxide semiconductor input/output input/output nonvolatile static random access memory output enable static random access memory transistor-transistor logic write enable

Document Conventions

Units of Measure

Symbol °C mA ms ns pF V

Unit of Measure degrees Celsius kilohm microampere milliampere microfarad microsecond millisecond nanosecond picofarad volt ohm watt

Page 16 of 18

STK11C68-5 SMD5962-92324

Document History Page

Document Title STK11C68-5 SMD5962-92324 64 Kbit 8 K x 8 SoftStore nvSRAM Document Number 001-51001

ECN No.

Orig. of Change

Submission Date

Description of Change
2666844 GVCH/PYRS 03/02/2009 New data sheet
2685053

GVCH
Ordering Code Information table.

Updated Package diagrams.
3527665

GVCH
4568935

GVCH
11/14/2014

Added documentation related hyperlink in page 1 Removed 02pruned parts - STK11C68-5K55M, STK11C68-5L55M Updated package diagrams from 001-51695*A to 001-51695*B and 001-51696*A to 001-51696*B
4706588

GVCH
04/02/2015 Updated package diagrams from 001-51695*B to 001-51695*C and 001-51696*B to 001-51696*C

Page 17 of 18

STK11C68-5 SMD5962-92324

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 18 of 18

AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.

More datasheets: 88827115 | 88827105 | 88827155 | 88827103 | 88827145 | 88827125 | 88827054 | PI3EQXDP1201ZBE | 5962-9232406MYA | 5962-9232404MXA

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 5962-9232404MYA Datasheet file may be downloaded here without warranties.

Datasheet ID: 5962-9232404MYA 508333