S72XS256RE0AHBH10

S72XS256RE0AHBH10 Datasheet


S72XS-R MCP

Part Datasheet
S72XS256RE0AHBH10 S72XS256RE0AHBH10 S72XS256RE0AHBH10 (pdf)
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S72XS-R MCP
256 Mb 16M x 16 bit , 1.8V Flash and DDR DRAM
• Power supply voltage 1.7V to 1.95V
• Burst speed Flash = 83 MHz, 104 MHz or 108 MHz DDR DRAM = 166 MHz
• Packages mm, 133-ball MCP
• Temperature range Wireless °C to +85 °C Industrial °C to +85 °C

Table Memory Density

Flash Density 256 Mb

This datasheet contains information on the S72XS-R Multi-Chip Product MCP stacked products. Refer to the S29VS256R, S29VS128R, S29XS256R, S29XS128R datasheet 002-00833 for full electrical specifications of the Flash memory component. The S72XS series is a product line of stacked products MCPs , and consists of
• S29XS family Address-High, Address-Low, Data Multiplexed

Flash memory die
• DDR DRAM Table 1 and Table 2 lists the products covered in this datasheet.

DRAM Density S72XS256RE0

Table DDR DRAM Specification Reference

Density 256 Mb

Reference Name 256 Mb 16M 16-bit DDR DRAM

Document Identification Number SDM256D166D1R/D3R

Block Diagram

F-RS T#

F-V P

F-CE # F-OE # F-W E # F-A V D#

RST#

CE# O E# W E# A V D#

A DQ15-A DQ0

A max-A 16 No Connect

FLASH

XS-R

AADM V CC

V CCQ

V SSQ

A DQ15-A DQ0 F -C L K F -R D Y

F-V CC F-V CCQ VSS

D-RA S # D-CA S # D-B A 0 D-B A 1 D-CK E D-W E # D-CE # D-A m ax - D-A 0 D-V CC D-V CCQ

RA S# CA S# BA 0 BA 1 CKE W E# CS# A max-A 0 V DD V DDQ

DDR DRAM MEMORY

CK# LDQS UDQS LDM UDM

DQ15-DQ0 V SS

V SSQ

D-CLK D-CLK # D -LD Q S D -U D Q S D -LD Q M D -U D Q M

D-DQ15 - D-DQ0 VSS

Notes Amax indicates highest address bit for memory component Amax = A12 for 256 Mb DDR DRAM. For Flash, A15 - A0 is tied to DQ15 - DQ0.
• San Jose, CA 95134-1709
• 408-943-2600

S72XS-R MCP
Ordering Information

The order number Valid Combination is formed by the following:

S72XS
256 R E0 AH
3 Packing Type 0 = Tray 3 = 13-inch Tape and Reel

Model Number See Valid Combinations Table 5

Package Modifier B = 133-ball, 8x8 mm, FBGA MCP

Package and Material Type AH = Thin profile Fine-pitch BGA Pb-free Low-Halogen MCP mm pitch

DDR DRAM and Data Flash Density E0 = 256 Mb DDR, No Data Flash

Process Technology R = 65 nm, MirrorBit Technology

Code Flash Density 256 = 256 Mb

Product Family

S72XS Multi-Chip Product MCP 1.8V Address-High, Address-Low, Data Multiplexed, SRW, Burst Mode Flash and DDR DRAM on Split Bus

Valid Combinations Valid combinations in Table 5 list the configurations planned to be supported in volume for this device. Contact your local sales office to confirm the availability of specific valid combinations and to check on newly released combinations.

Table Valid Combinations

Base OPN[4] S72XS256RE0

Package

Model Packing Flash Number Type[3, 4] Boot

Bottom

Bottom

Bottom

Temperature Range Wireless

Industrial

Electronic Serial

Number

Flash Density

DDR DRAM Density

Flash Speed MHz
256 Mb 256 Mb 108

DRAM Speed MHz

DRAM Specification SDM256D166 D1R

SDM256D166 D3R

Package
mm 133-ball MCP

RSC133

Electronic Serial Number

For applicable devices, the Factory Secured Silicon Area contains a random, 128-bit ESN, stored in the address range
Notes Packing Type 0 is standard. Specify other options as required. BGA package marking omits leading “S” and packing type designator from ordering part number.

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S72XS-R MCP

Package Diagram Figure RSC133 Fine-Pitch Ball Grid Array FBGA mm

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S72XS-R MCP

Document History Page

Document Title S72XS-R MCP, 256 Mb 16M x 16 bit , 1.8V Flash and DDR DRAM Document Number 002-00772
** *A

Orig. of Change

BWHA

BWHA

Submission Date

Description of Change
10/07/2008 Initial release
01/13/2009 Global Added section Electronic Serial Number

Global Added SDM128D166D1K OPN

BWHA
12/18/2009

Product Block Diagram Figure Updated D-VSS and D-VSSQ connections. Removed D-TEST signal

Physical Dimensions Updated with RSC133

BWHA 02/01/2010 Connection Diagrams Updated figure changed Ball A2 with DNU

Global Updated references for Low Power DDR SDRAM to SDM128D166D1R

DDR Specification Reference Added reference for 256 Mb DDR DRAM

Product Selector Guide:

Added “not recommended for new designs” note to OPN S72XS128RD0AHBH60

Added OPN S72XS256RE0AHBH1

Removed OPN S72XS256RD0AHBHE

Product Block Diagram Updated block diagram to show common Ground. Updated Note 1b.

BWHA

Connection Diagrams 08/19/2010 Updated connection diagram to show common Ground

Updated to show D-A12

Added table to show D-Amax value for related MCP
Balls F1, M2 and M12 changed from NC to RFU Input/Output Descriptions Replaced F-VSS, D-VSS, D-VSSQ with VSS Corrected F-ACC to F-VPP Refreshed descriptions for DNU, NC, RFU Ordering Information/Valid Combinations Updated for new OPN S72XS256RE0AHBH1

BWHA 12/10/2010 Global Updated 256 Mb DRAM specification reference

BWHA

Global 03/17/2011 Removed SDM128D166D1K references

Removed OPN S72XS128RD0AHBH60, Added OPN S72XS256RE0AHBJ1
Ordering Information Replaced Product Selector Guide section

BWHA
10/05/2011

Valid Combinations Made a separate section

Added OPNs S72XS128RD0AHBHD, S72XS256RE0AHBHH/JH
BWHA 04/17/2012 Ordering Information Added ESN support for S72XS256RE0AHBH1
4960467 BWHA 10/13/2015 Updated to new template.
5181007
03/18/2016 Removed S72XS128RD0 as it is EOL’d.

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S72XS-R MCP

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Datasheet ID: S72XS256RE0AHBH10 508324