S29NS512P0PBJW003

S29NS512P0PBJW003 Datasheet

S29NS512P, S29NS256P, S29NS128P

Part	Datasheet
S29NS512P0PBJW003	S29NS512P0PBJW003 (pdf)

Related Parts	Information
S29NS512P0PBJW000	S29NS512P0PBJW000

PDF Datasheet Preview
"Spansion, Inc." and "Cypress Semiconductor Corp." have merged together to deliver high-performance, high-quality solutions at the heart of today's most advanced embedded systems, from automotive, industrial and networking platforms to highly interactive consumer and mobile devices. The new company "Cypress Semiconductor Corp." will continue to offer "Spansion, Inc." products to new and existing customers. Continuity of Ordering Part Numbers Cypress continues to support existing part numbers. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local sales office for additional information about Cypress products and solutions. S29NS512P, S29NS256P, S29NS128P 512/256/128 Mb 32/16/8 M x 16 bit V MirrorBit Flash Memory Single 1.8V read/program/erase 90 nm MirrorBit Technology Multiplexed Data and Address for reduced I/O count Simultaneous Read/Write operation Full/Half drive output slew rate control 32-word Write Buffer Sixteen-bank architecture consisting of 64/32/16 MB for NS512/256/128P, respectively Four 32 kB sectors at the top of memory array NS256/128P 512 128 kB sectors NS512P , 255/127 128 kB sectors NS256/128P Programmable linear 8/16/32 with or without wrap around and continuous burst read modes Secured Silicon Sector region consisting of 128 words each for factory and customer 20-year data retention typical Cycling Endurance 100,000 cycles per sector typical RDY output indicates data available to system Performance Characteristics Read Access Times Speed Option MHz Max. Synch. Burst Access, ns tBACC Max. Asynch. Access Time, ns tACC Max OE# Access Time, ns tOE 83 MHz ns 80 ns Current Consumption typical values Continuous Burst Read 83 MHz Simultaneous Operation 83 MHz Program Standby Mode 42 mA 60 mA 30 mA 20 µA Command set compatible with JEDEC standard Hardware WP# protection of highest two sectors Top Boot sector configuration NS256/128P Handshaking by monitoring RDY Offered Packages NS512P 64-ball FBGA 8 mm x mm NS256P/NS128P 44-ball FBGA mm x mm Low VCC write inhibit Persistent and Password methods of Advanced Sector Protection Write operation status bits indicate program and erase operation completion Suspend and Resume commands for Program and Erase operations Unlock Bypass program command to reduce programming time Synchronous or Asynchronous program operation, independent of burst control register settings VPP input pin to reduce factory programming time Support for Common Flash Interface CFI Typical Program & Erase Times Single Word Programming Effective Write Buffer Programming VCC Per Word Effective Write Buffer Programming VPP Per Word Sector Erase 16 Kword Sector Erase 64 Kword Sector 40 µs µs 6 µs 450 ms 900 ms • San Jose, CA 95134-1709 • 408-943-2600 S29NS512P S29NS256P, S29NS128P Contents Performance 2 General 4 Ordering Information 4 Input/Output Descriptions and Logic Symbol........... 5 Block 6 Physical Dimensions/Connection Diagrams............. 7 Related Documents 7 Special Handling Instructions for FBGA Package.......... 7 Product Overview 11 Memory Map 11 Device Operations 26 Device Operation Table 26 Asynchronous 26 Synchronous Burst Read Operation.......................... 27 Autoselect 33 Program/Erase Operations 35 Simultaneous Read/Write 50 Writing Commands/Command Sequences.................. 50 Handshaking 51 Hardware Reset 51 Software Reset 51 Programmable Output Slew Rate Control.................... 52 Advanced Sector Protection/Unprotection 53 Lock Register 54 Persistent Protection 54 Dynamic Protection 56 Persistent Protection Bit Lock Bit................................. 57 Password Protection Method 58 Advanced Sector Protection Software Examples 59 Hardware Data Protection Methods............................. 60 Power Conservation 61 Standby 61 Automatic Sleep 61 Hardware RESET# Input Operation............................. 61 Output Disable 61 Secured Silicon Sector Flash Memory Region 62 Factory Secured Silicon Sector 62 Customer Secured Silicon Sector 62 Secured Silicon Sector Entry and Exit Command Sequences 63 Electrical 65 Absolute Maximum Ratings 65 Operating 65 DC Characteristics 66 Capacitance 67 Test Conditions 67 Key to Switching Waveforms 67 Switching Waveforms 68 CLK 68 AC Characteristics 69 11.10Erase and Programming Performance 80 Appendix 81 Common Flash Memory 85 Page 3 of 106 S29NS512P S29NS256P, S29NS128P The Spansion S29NS512/256/128P are MirrorBit Flash products fabricated on 90 nm process technology. These burst mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using multiplexed data and address pins. These products can operate up to 83 MHz and use a single VCC of V to V that makes them ideal for the demanding wireless applications of today that require higher density, better performance, and lowered power consumption.Ordering Information Ordering Information The ordering part number is formed by a valid combination of the following: S29NS 512 P xx BJ W 00 0 Packing Type 0 = Tray standard Note 1 3 = 13-inch Tape and Reel Model Number 00 = Standard Temperature Range W = Wireless to +85°C Package Type & Material Set BJ = Very Thin Fine-Pitch BGA,Lead Pb -free LF35 Package Speed Option Burst Frequency 0P = 66 MHz 0S = 83 MHz Process Technology P = 90 nm MirrorBit Technology Flash Density 512 =512 Mb 256 =256 Mb 128 =128 Mb Product Family S29NS Volt-Only Simultaneous Read/Write, Burst Mode Multiplexed Flash Memory Valid Combinations Base Ordering Part Number Speed Option Package Type, Material, & Temperature Range Packing Type Model Number S29NS512P S29NS256P 0P, 0S BJW Lead Pb -free, LF35 0, 3 1 S29NS128P Notes Type 0 is standard. Specify other options as required. BGA package marking omits leading S29 and packing type designator from ordering part number. Package Type mm x mm, 64-ball mm x mm, 44-ball Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. Page 4 of 93 S29NS512P S29NS256P, S29NS128P Input/Output Descriptions and Logic Symbol Table identifies the input and output package connections provided on the device. Table Input/Output Descriptions Symbol A24 A16 A23 A16 A22 A16 A/DQ15 A/DQ0 CE# OE# WE# VCC VCCQ VSS VSSQ NC RDY CLK AVD# RESET# WP# Type Input Address inputs, S29NS512P. Input Address inputs, S29NS256P. Input Address inputs, S29NS128P. Multiplexed Address/Data input/output. Input Chip Enable. Asynchronous relative to CLK for the Burst mode. Input Output Enable. Asynchronous relative to CLK for the Burst mode. Input Write Enable. Supply Device Power Supply. Supply I/O Input/Output Power Supply must be ramped simultaneously with VCC . Ground. Input/Output Ground. Not Connected No device internal signal is connected to the package connector nor is there any future plan to use the connector for a signal. The connection may safely be used for routing space for a signal on a Printed Circuit Board PCB . Output Ready. Indicates when valid burst data is ready to be read. Input The first rising edge of CLK in conjunction with AVD# low latches address input and activates burst mode operation. After the initial word is output, subsequent rising edges of CLK increment the internal address counter. CLK should remain low during asynchronous access. Input Address Valid input. Indicates to device that the valid address is present on the address inputs address bits A15 A0 are multiplexed, address bits Amax A16 are address only . VIL = for asynchronous mode, indicates valid address for burst mode, cause staring address to be latched on rising edge of CLK. VIH = device ignores address inputs. Hardware Reset. Low = device resets and returns to reading array data. Input Write Protect. At VIL, disables program and erase functions in the four top sectors. Should be at VIH for all other conditions. Input Reserved

PDF Datasheet Preview

"Spansion, Inc." and "Cypress Semiconductor Corp." have merged together to deliver high-performance, high-quality solutions at the heart of today's most advanced embedded systems, from automotive, industrial and networking platforms to highly interactive consumer and mobile devices. The new company "Cypress Semiconductor Corp." will continue to offer "Spansion, Inc." products to new and existing customers.
Continuity of Ordering Part Numbers Cypress continues to support existing part numbers. To order these products, please use only the Ordering Part Numbers listed in this document.

For More Information Please contact your local sales office for additional information about Cypress products and solutions.

S29NS512P, S29NS256P, S29NS128P
512/256/128 Mb 32/16/8 M x 16 bit V MirrorBit Flash Memory

Single 1.8V read/program/erase 90 nm MirrorBit Technology Multiplexed Data and Address for reduced I/O count Simultaneous Read/Write operation Full/Half drive output slew rate control 32-word Write Buffer Sixteen-bank architecture consisting of
64/32/16 MB for NS512/256/128P, respectively Four 32 kB sectors at the top of memory array NS256/128P 512 128 kB sectors NS512P , 255/127 128 kB sectors

NS256/128P Programmable linear 8/16/32 with or without wrap around and
continuous burst read modes Secured Silicon Sector region consisting of 128 words each for
factory and customer 20-year data retention typical Cycling Endurance 100,000 cycles per sector typical RDY output indicates data available to system

Performance Characteristics

Read Access Times Speed Option MHz Max. Synch. Burst Access, ns tBACC Max. Asynch. Access Time, ns tACC Max OE# Access Time, ns tOE
83 MHz ns 80 ns

Current Consumption typical values Continuous Burst Read 83 MHz Simultaneous Operation 83 MHz Program Standby Mode
42 mA 60 mA 30 mA 20 µA

Command set compatible with JEDEC standard Hardware WP# protection of highest two sectors Top Boot sector configuration NS256/128P Handshaking by monitoring RDY Offered Packages

NS512P 64-ball FBGA 8 mm x mm NS256P/NS128P 44-ball FBGA mm x mm Low VCC write inhibit Persistent and Password methods of Advanced Sector Protection Write operation status bits indicate program and erase operation completion Suspend and Resume commands for Program and Erase operations Unlock Bypass program command to reduce programming time Synchronous or Asynchronous program operation, independent of burst control register settings VPP input pin to reduce factory programming time Support for Common Flash Interface CFI

Typical Program & Erase Times Single Word Programming Effective Write Buffer Programming VCC Per Word Effective Write Buffer Programming VPP Per Word Sector Erase 16 Kword Sector Erase 64 Kword Sector
40 µs µs 6 µs 450 ms 900 ms
• San Jose, CA 95134-1709
• 408-943-2600

S29NS512P S29NS256P, S29NS128P

Contents

Performance 2

General 4
Ordering Information 4

Input/Output Descriptions and Logic Symbol........... 5

Block 6

Physical Dimensions/Connection Diagrams............. 7 Related Documents 7 Special Handling Instructions for FBGA Package.......... 7

Product Overview 11 Memory Map 11

Device Operations 26 Device Operation Table 26 Asynchronous 26 Synchronous Burst Read Operation.......................... 27 Autoselect 33 Program/Erase Operations 35 Simultaneous Read/Write 50 Writing Commands/Command Sequences.................. 50 Handshaking 51 Hardware Reset 51 Software Reset 51 Programmable Output Slew Rate Control.................... 52

Advanced Sector Protection/Unprotection 53 Lock Register 54 Persistent Protection 54 Dynamic Protection 56 Persistent Protection Bit Lock Bit................................. 57 Password Protection Method 58 Advanced Sector Protection Software Examples 59 Hardware Data Protection Methods............................. 60

Power Conservation 61 Standby 61 Automatic Sleep 61 Hardware RESET# Input Operation............................. 61 Output Disable 61

Secured Silicon Sector Flash Memory Region 62 Factory Secured Silicon Sector 62 Customer Secured Silicon Sector 62 Secured Silicon Sector Entry and Exit

Command Sequences 63

Electrical 65 Absolute Maximum Ratings 65 Operating 65 DC Characteristics 66 Capacitance 67 Test Conditions 67 Key to Switching Waveforms 67 Switching Waveforms 68 CLK 68 AC Characteristics 69 11.10Erase and Programming Performance 80

Appendix 81 Common Flash Memory 85

Page 3 of 106

S29NS512P S29NS256P, S29NS128P
The Spansion S29NS512/256/128P are MirrorBit Flash products fabricated on 90 nm process technology. These burst mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using multiplexed data and address pins. These products can operate up to 83 MHz and use a single VCC of V to V that makes them ideal for the demanding wireless applications of today that require higher density, better performance, and lowered power consumption.Ordering Information
Ordering Information
The ordering part number is formed by a valid combination of the following:

S29NS 512 P xx BJ W 00 0 Packing Type 0 = Tray standard Note 1 3 = 13-inch Tape and Reel Model Number 00 = Standard Temperature Range W = Wireless to +85°C Package Type & Material Set BJ = Very Thin Fine-Pitch BGA,Lead Pb -free LF35 Package Speed Option Burst Frequency 0P = 66 MHz 0S = 83 MHz Process Technology P = 90 nm MirrorBit Technology Flash Density 512 =512 Mb 256 =256 Mb 128 =128 Mb Product Family S29NS Volt-Only Simultaneous Read/Write, Burst Mode Multiplexed Flash Memory

Valid Combinations
Base Ordering Part Number

Speed Option

Package Type, Material, & Temperature Range

Packing Type

Model Number

S29NS512P

S29NS256P
0P, 0S

BJW Lead Pb -free, LF35 0, 3 1

S29NS128P

Notes Type 0 is standard. Specify other options as required.
BGA package marking omits leading S29 and packing type designator from ordering part number.

Package Type
mm x mm, 64-ball mm x mm, 44-ball

Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.

Page 4 of 93

S29NS512P S29NS256P, S29NS128P

Input/Output Descriptions and Logic Symbol

Table identifies the input and output package connections provided on the device.

Table Input/Output Descriptions

Symbol A24 A16 A23 A16 A22 A16 A/DQ15 A/DQ0 CE# OE# WE# VCC VCCQ VSS VSSQ NC RDY CLK

AVD#

RESET# WP#

Type

Input

Address inputs, S29NS512P.

Input

Address inputs, S29NS256P.

Input

Address inputs, S29NS128P.

Multiplexed Address/Data input/output.

Input

Chip Enable. Asynchronous relative to CLK for the Burst mode.

Input

Output Enable. Asynchronous relative to CLK for the Burst mode.

Input

Write Enable.

Supply Device Power Supply.

Supply I/O

Input/Output Power Supply must be ramped simultaneously with VCC . Ground.

Input/Output Ground.

Not Connected

No device internal signal is connected to the package connector nor is there any future plan to use the connector for a signal. The connection may safely be used for routing space for a signal on a Printed Circuit Board PCB .

Output Ready. Indicates when valid burst data is ready to be read.

Input

The first rising edge of CLK in conjunction with AVD# low latches address input and activates burst mode operation. After the initial word is output, subsequent rising edges of CLK increment the internal address counter. CLK should remain low during asynchronous access.

Input

Address Valid input. Indicates to device that the valid address is present on the address inputs address bits A15 A0 are multiplexed, address bits Amax A16 are address only . VIL = for asynchronous mode, indicates valid address for burst mode, cause staring address to be latched on rising edge of CLK. VIH = device ignores address inputs.

Hardware Reset. Low = device resets and returns to reading array data.

Input

Write Protect. At VIL, disables program and erase functions in the four top sectors. Should be at VIH for all other conditions.

Input Reserved

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived S29NS512P0PBJW003 Datasheet file may be downloaded here without warranties.

Datasheet ID: S29NS512P0PBJW003 508318