S29GL01GP12FAI010

S29GL01GP12FAI010 Datasheet

S29GL01GP S29GL512P S29GL256P S29GL128P

Part	Datasheet
S29GL01GP12FAI010	S29GL01GP12FAI010 (pdf)

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S29GL01GP S29GL512P S29GL256P S29GL128P 1 Gbit, 512, 256, 128 Mbit, 3 V, Page Flash with 90 nm MirrorBit Process Technology The Spansion S29GL01G/512/256/128P are Flash products fabricated on 90 nm process technology. These devices offer a fast page access time of 25 ns with a corresponding random access time as fast as 90 ns. They feature a Write Buffer that allows a maximum of 32 words/64 bytes to be programmed in one operation, resulting in faster effective programming time than standard programming algorithms. This makes these devices ideal for today’s embedded applications that require higher density, better performance and lower power consumption. Distinctive Characteristics Single 3V read/program/erase V Enhanced VersatileI/O control All input levels address, control, and DQ input levels and outputs are determined by voltage on VIO input. VIO range is to VCC 90 nm MirrorBit process technology 8-word/16-byte page read buffer 32-word/64-byte write buffer reduces overall programming time for multiple-word updates Secured Silicon Sector region 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random Electronic Serial Number Can be programmed and locked at the factory or by the customer Uniform 64 Kword/128 Kbyte Sector Architecture S29GL01GP One thousand twenty-four sectors S29GL512P Five hundred twelve sectors S29GL256P Two hundred fifty-six sectors S29GL128P One hundred twenty-eight sectors 100,000 erase cycles per sector typical 20-year data retention typical Offered Packages 56-pin TSOP 64-ball Fortified BGA Suspend and Resume commands for Program and Erase operations Write operation status bits indicate program and erase operation completion Unlock Bypass Program command to reduce programming time Support for CFI Common Flash Interface Persistent and Password methods of Advanced Sector Protection WP#/ACC input Accelerates programming time when VHH is applied for greater throughput during system production Protects first or last sector regardless of sector protection settings Hardware reset input RESET# resets device Ready/Busy# output RY/BY# detects program or erase cycle completion • San Jose, CA 95134-1709 • 408-943-2600 S29GL01GP S29GL512P S29GL256P S29GL128P Performance Characteristics Maximum Read Access Times ns Density 128 & 256 Mb 512 Mb 1 Gb Voltage Range 1 Regulated VCC Full VCC VersatileIO VIO Regulated VCC Full VCC VersatileIO VIO Regulated VCC Full VCC VersatileIO VIO Random Access Time tACC 90 100/110 100 110 120 110 120 130 Page Access Time tPACC 25 Notes Access times are dependent on VCC and VIO operating ranges. See Ordering Information page for further details. Regulated VCC = V. Full VCC = VIO = V. VersatileIO VIO = VCC = V. Contact a sales representative for availability. CE# Access Time tCE 90 100/110 100 110 120 110 120 130 OE# Access Time tOE 25 Current Consumption typical values Random Access Read f = 5 MHz 8-Word Page Read f = 10 MHz Program/Erase Standby 30 mA 1 mA 50 mA 1 µA Program & Erase Times typical values Single Word Programming Effective Write Buffer Programming VCC Per Word Effective Write Buffer Programming VHH Per Word Sector Erase Time 64 Kword Sector 60 µs 15 µs µs Page 2 of 82 S29GL01GP S29GL512P S29GL256P S29GL128P Contents Ordering Information 4 Input/Output Descriptions & Logic Symbol 6 Block 7 Physical Dimensions/Connection Diagrams............. 7 Related Documents 7 Special Handling Instructions for BGA Package............ 7 ball Fortified Ball Grid Array, 11 x 13 mm. 9 Standard Thin Small Outline Package Additional Resources 12 Application Notes 12 Specification Bulletins 12 Hardware and Software 12 Contacting 12 Product Overview 13 Memory Map 13 Device Operations 14 Device Operation Table 14 Word/Byte 15 VersatileIOTM VIO Control 15 Read 15 Page Read Mode 15 Autoselect 16 Program/Erase Operations 19 Write Operation 31 Writing Commands/Command Sequences.................. 35 Advanced Sector Protection/Unprotection 37 Lock Register 38 Persistent Protection 38 Persistent Protection Bit Lock Bit................................. 40 Password Protection Method 40 Advanced Sector Protection Software Examples 43 Hardware Data Protection Methods............................. 43 Power Conservation 44 Standby 44 Automatic Sleep 44 Hardware RESET# Input Operation............................. 44 Output Disable 44 Secured Silicon Sector Flash Memory Region 45 Factory Locked Secured Silicon Sector 45 Customer Lockable Secured Silicon Sector................. 46 Secured Silicon Sector Entry/Exit Command Sequences 46 Electrical 48 Absolute Maximum Ratings 48 Operating 49 Test Conditions 49 Key to Switching Waveforms 49 Switching Waveforms 50 DC Characteristics 51 AC Characteristics 52 Appendix 63 Command 63 Common Flash Memory 69 Advance Information on S29GL-S Eclipse 65 nm Mirror Bit Power-On and Warm Reset Timing 73 Page 3 of 82 S29GL01GP S29GL512P S29GL256P S29GL128P Ordering Information The ordering part number is formed by a valid combination of the following: S29GL01GP F I 01 0 PACKING TYPE 0 = Tray standard Note 5 2 = 7” Tape and Reel 3 = 13” Tape and Reel MODEL NUMBER VIO range, protection when WP# =VIL 01 = VIO = VCC = to V, highest address sector protected 02 = VIO = VCC = to V, lowest address sector protected V1 = VIO = to VCC, VCC = to V, highest address sector protected V2 = VIO = to VCC, VCC = to V, lowest address sector protected R1 = VIO = VCC = to V, highest address sector protected R2 = VIO = VCC = to V, lowest address sector protected TEMPERATURE RANGE I = Industrial to +85°C C = Commercial 0°C to +85°C PACKAGE MATERIALS SET A = Pb Note 1 F = Pb-free PACKAGE TYPE T = 56-pin Thin Small Outline Package TSOP Standard Pinout TSO56 F = 64-ball Fortified Ball Grid Array, mm pitch package LAA064 SPEED OPTION 90 = 90 ns 10 = 100 ns 11 = 110 ns 12 = 120 ns 13 = 130 ns DEVICE NUMBER/DESCRIPTION S29GL01GP, S29GL512P, S29GL256P, S29GL128P Volt-only, 1024, 512, 256 and 128 Megabit Page-Mode Flash Memory, manufactured on 90 nm process technology Page 4 of 82 S29GL01GP S29GL512P S29GL256P S29GL128P Recommended Combinations Recommended Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific recommended combinations and to check on newly released combinations. S29GL-P Valid Combinations Base Part Number S29GL01GP S29GL512P S29GL128P, S29GL256P Speed 11 12 13 11 12 13 10 11 12 10 11 12 90 10, 11 90 10, 11 Package 2 3 TA 1 , TF FA 1 , FF TA 1 , TF FA 1 , FF TA 1 , TF FA 1 , FF Temperature 4 I, C I, C I, C I, C I, C I, C I Model Number R1, R2 01, 02 V1, V2 R1, R2 01, 02 V1, V2 R1, R2 01, 02 V1, V2 R1, R2 01, 02 V1, V2 R1, R2 01, 02 V1, V2 R1, R2 01, 02 V1, V2 Notes Contact a local sales representative for availability. TSOP package marking omits packing type designator from ordering part number. BGA package marking omits leading “S29” and packing type designator from ordering part number. Operating Temperature range I = Industrial to +85°C C = Commercial 0°C to +85°C Type 0 is standard. Specify other options as required. Packing Type 5 0, 3 0, 2, 3 0, 3 0, 2, 3 0, 3 0, 2, 3 Page 5 of 82 S29GL01GP S29GL512P S29GL256P S29GL128P Input/Output Descriptions & Logic Symbol Table identifies the input and output package connections provided on the device. Input/Output Descriptions DQ15/A-1 CE# OE# WE# VCC VIO VSS NC RY/BY# BYTE# RESET# WP#/ACC Type Input I/O I/O Input Supply No Connect Output Input Input Input Address lines for GL01GP for GL512P for GL256P, for GL128P. Data input/output. DQ15 Data input/output in word mode. A-1 LSB address input in byte mode. Chip Enable. Output Enable. Write Enable. Device Power Supply. Versatile IO Input. Ground. Not connected internally. Ready/Busy. Indicates whether an Embedded Algorithm is in progress or complete. At VIL, the device is actively erasing or programming. At High Z, the device is in ready. Selects data bus width. At VIL, the device is in byte configuration and data I/O pins DQ0DQ7 are active and DQ15/A-1 becomes the LSB address input. At VIH, the device is in word configuration and data I/O pins DQ0-DQ15 are active. Hardware Reset. Low = device resets and returns to reading array data. Write Protect/Acceleration Input. At VIL, disables program and erase functions in the outermost sectors. At VHH, accelerates programming automatically places device in unlock bypass mode. Should be at VIH for all other conditions. WP# has an internal pullup when unconnected, WP# is at VIH. Page 6 of 82 Block Diagram VCC VSS VIO RESET# WE# WP#/ACC BYTE# The VersatileIOTM VIO control allows the host system to set the voltage levels that the device generates and tolerates on all inputs and outputs address, control, and DQ signals . VIO range is to VCC. See Ordering Information on page 4 for VIO options on this device. For example, a VIO of volts allows for I/O at the or 3 volt levels, driving and receiving signals to and from other or 3 V devices on the same data bus. Read All memories require access time to output array data. In a read operation, data is read from one memory location at a time. Addresses are presented to the device in random order, and the propagation delay through the device causes the data on its outputs to arrive with the address on its inputs. The device defaults to reading array data after device power-up or hardware reset. To read data from the memory array, the system must first assert a valid address on Amax-A0, while driving OE# and CE# to VIL. WE# must remain at VIH. All addresses are latched on the falling edge of CE#. Data will appear on DQ15-DQ0 after address access time tACC , which is equal to the delay from stable addresses to valid output data. The OE# signal must be driven to VIL. Data is output on DQ15-DQ0 pins after the access time tOE has elapsed from the falling edge of OE#, assuming the tACC access time has been meet. Page Read Mode The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. The page size of the device is 8 words/16 bytes. The appropriate page is selected by the higher address bits A max -A3. Address bits A2-A0 in word mode A2 to A-1 in byte mode determine the specific word within a page. The microprocessor supplies the specific word location. The random or initial page access is equal to tACC or tCE and subsequent page read accesses as long as the locations specified by the microprocessor falls within that page is equivalent to tPACC. When CE# is de-asserted and reasserted for a subsequent access, the access time is tACC or tCE. Fast page mode accesses are obtained by keeping the “read-page addresses” constant and changing the “intra-read page” addresses. Page 15 of 82 S29GL01GP S29GL512P S29GL256P S29GL128P Autoselect The Autoselect mode provides manufacturer ID, Device identification, and sector protection information, through identifier codes output from the internal register separate from the memory array on DQ7-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm see Table The Autoselect codes can also be accessed in-system. There are two methods to access autoselect codes. One uses the autoselect command, the other applies VID on address pin A9. When using programming equipment, the autoselect mode requires VID V to V on address pin A9. Address pins must be as shown in Table To access Autoselect mode without using high voltage on A9, the host system must issue the Autoselect command. The Autoselect command sequence may be written to an address within a sector that is either in the read or erase-suspend-read mode. The Autoselect command may not be written while the device is actively programming or erasing. The system must write the reset command to return to the read mode or erase-suspend-read mode if the sector was previously in Erase Suspend . It is recommended that A9 apply VID after power-up sequence is completed. In addition, it is recommended that A9 apply from VID to VIH/VIL before power-down the VCC/VIO. See Table on page 64 for command sequence details. When verifying sector protection, the sector address must appear on the appropriate highest order address bits see Table to Table The remaining address bits are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ15-DQ0. The Autoselect codes can also be accessed in-system through the command register. Page 16 of 82 S29GL01GP S29GL512P S29GL256P S29GL128P Autoselect Codes, High Voltage Method Description Manufacturer ID Spansion Product Cycle 1 Cycle 2 Cycle 3 Amax A14 A5 A3 DQ8 to DQ15 BYTE# BYTE# CE# OE# WE# A16 A10 A9 A7 A6 A4 A2 A1 A0 = VIH = VIL X VID X L X L L H 22 X VID X DQ7 to DQ0 01h 7Eh 28h 01h Device ID Device ID Device ID Device ID S29GL128P S29GL256P S29GL512P S29GL01GP Cycle 1 L H 22 Cycle 2 X VID X Cycle 3 Cycle 1 Cycle 2 Cycle 3 L H 22 X VID X Cycle 1 Cycle 2 Cycle 3 Volatile Bits defaults to user choice upon power-up see ordering options . Page 37 of 82 S29GL01GP S29GL512P S29GL256P S29GL128P Lock Register As shipped from the factory, all devices default to the persistent mode when power is applied, and all sectors are unprotected, unless otherwise chosen through the DYB ordering option see Ordering Information on page The device programmer or host system must then choose which sector protection method to use. Programming setting to “0” any one of the following two one-time programmable, non-volatile bits locks the part permanently in that mode: Lock Register Persistent Protection Mode Lock Bit DQ1 Lock Register Password Protection Mode Lock Bit DQ2 Lock Register DQ15-3 Don’t Care Password Protection Mode Lock Bit Persistent Protection Mode Lock Bit Secured Silicon Sector Protection Bit For programming lock register bits refer to Table on page 66 and Table on page Notes If the password mode is chosen, the password must be programmed before setting the corresponding lock register bit. After the Lock Register Bits Command Set Entry command sequence is written, reads and writes for Sector 0 are disabled, while reads from other sectors are allowed until exiting this mode. If both lock bits are selected to be programmed to zeros at the same time, the operation aborts. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently disabled, and no changes to the protection scheme are allowed. Similarly, if the Persistent Mode Lock Bit is programmed, the Password Mode is permanently disabled. After selecting a sector protection method, each sector can operate in any of the following three states: Constantly locked. The selected sectors are protected and can not be reprogrammed unless PPB lock bit is cleared via a password, hardware reset, or power cycle. Dynamically locked. The selected sectors are protected and can be altered via software commands. Unlocked. The sectors are unprotected and can be erased and/or programmed. These states are controlled by the bit types described in Section Persistent Protection Bits The Persistent Protection Bits are unique and nonvolatile for each sector and have the same endurances as the Flash memory. Preprogramming and verification prior to erasure are handled by the device, and therefore do not require system monitoring. Notes Each PPB is individually programmed and all are erased in parallel. While programming PPB for a sector, array data can be read from any other sector, except Sector 0 used for Data# Polling and the sector in which sector PPB is being programmed. Entry command disables reads and writes for the sector selected. Reads within that sector return the PPB status for that sector. All Reads must be performed using the read mode. The specific sector address A25-A16 GL01GP, A24-A16 GL512P, A23-A16 GL256P, A22-A16 GL128P are written at the same time as the program command. If the PPB Lock Bit is set, the PPB Program or erase command does not execute and times-out without programming or erasing the PPB. There are no means for individually erasing a specific PPB and no specific sector address is required for this operation. Page 38 of 82 S29GL01GP S29GL512P S29GL256P S29GL128P Exit command must be issued after the execution which resets the device to read mode and re-enables reads and writes for Sector The programming state of the PPB for a given sector can be verified by writing a PPB Status Read Command to the device as described by the flow chart shown in Figure Figure PPB Program Algorithm Enter PPB Command Set. Addr = BA Program PPB Bit. Addr = SA Read Byte Twice Addr = SA0 DQ6 = Toggle? No DQ5 = 1? Read Byte Twice Addr = SA0 Notes The DYBs can be set programmed to “0” or cleared erased to “1” as often as needed. When the parts are first shipped, the PPBs are cleared erased to “1” and upon power up or reset, the DYBs can be set or cleared depending upon the ordering option chosen. If the option to clear the DYBs after power up is chosen, erased to “1” , then the sectorsmay be modified depending upon the PPB state of that sector see Table The sectors would be in the protected state If the option to set the DYBs after power up is chosen programmed to It is possible to have sectors that are persistently locked with sectors that are left in the dynamic state. The DYB Set or Clear commands for the dynamic sectors signify protected or unprotectedstate of the sectors respectively. However, if there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock Bit must be cleared by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB Lock Bit once again locks the PPBs, and the device operates normally again. To achieve the best protection, it is recommended to execute the PPB Lock Bit Set command early in the boot code and protect the boot code by holding WP#/ACC = VIL. Note that the PPB and DYB bits have the same function when WP#/ ACC = VHH as they do when ACC =VIH. Persistent Protection Bit Lock Bit The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors. When set programmed to “0” , it locks all PPBs and when cleared programmed to “1” , allows the PPBs to be changed. There is only one PPB Lock Bit per device. Notes No software command sequence unlocks this bit unless the device is in the password protection mode only a hardware reset or a power-up clears this bit. The PPB Lock Bit must be set programmed to “0” only after all PPBs are configured to the desired settings. Password Protection Method The Password Protection Method allows an even higher level of security than the Persistent Sector Protection Mode by requiring a 64-bit password for unlocking the device PPB Lock Bit. In addition to this password requirement, after power up and reset, the PPB Lock Bit is set “0” to maintain the password mode of operation. Successful execution of the Password Unlock command by entering the entire password clears the PPB Lock Bit, allowing for sector PPBs modifications. Notes There is no special addressing order required for programming the password. Once the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent access. The Password Program Command is only capable of programming “0”s. Programming a “1” after a cell is programmed as a “0” results in a time-out with the cell as a The password is all “1”s when shipped from the factory. All 64-bit password combinations are valid as a password. There is no means to verify what the password is after it is set. The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the data bus and further password programming. Page 40 of 82 S29GL01GP S29GL512P S29GL256P S29GL128P The Password Mode Lock Bit is not erasable. The lower two address bits are valid during the Password Read, Password Program, and Password Unlock. The exact password must be entered in order for the unlocking function to occur. The Password Unlock command cannot be issued any faster than 1 µs at a time to prevent a hacker from running through all the 64-bit combinations in an attempt to correctly match a password. Approximately 1 µs is required for unlocking the device after the valid 64-bit password is given to the device. Password verification is only allowed during the password programming operation. All further commands to the password region are disabled and all operations are ignored. If the password is lost after setting the Password Mode Lock Bit, there is no way to clear the PPB Lock Bit. Entry command sequence must be issued prior to any of any operation and it disables reads and writes for Sector Reads and writes for other sectors excluding Sector 0 are allowed. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program or erase command to a protected sector enables status polling and returns to read mode without having modified the contents of the protected sector. The programming of the DYB, PPB, and PPB Lock for a given sector can be verified by writing individual status read commands DYB Status, PPB Status, and PPB Lock Status to the device. Page 41 of 82 S29GL01GP S29GL512P S29GL256P S29GL128P Figure Lock Register Program Algorithm Write Unlock Cycles Address 555h, Data AAh Address 2AAh, Data 55h Unlock Cycle 1 Unlock Cycle 2 Write Enter Lock Register Command: Address 555h, Data 40h Program Lock Register Data Address XXXh, Data A0h Address XXXh*, Data PD XXXh = Address don’t care Program Data PD See text for Lock Register definitions Caution Lock register can only be progammed once. Perform Polling Algorithm see Write Operation Status flowchart Yes Done? DQ5 = 1? Error condition Exceeded Timing Limits PASS. Write Lock Register Exit Command: Address XXXh, Data 90h Address XXXh, Data 00h Device returns to reading array. Notes Operating ranges define those limits between which the functionality of the device is guaranteed. See also Ordering Information on page For valid VCC/VIO range combinations, see Ordering Information on page The I/Os do not operate at 3 V when VIO = V. Test Conditions Figure Test Setup Device Under Test Test Specifications Test Condition Output Load Capacitance, CL including jig capacitance Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels See Note Output timing measurement reference levels Note If VIO < VCC, the reference level is VIO. All Speeds 5 0.5VIO VIO Unit Key to Switching Waveforms Waveform Inputs Steady Changing from H to L Outputs Page 49 of 82 S29GL01GP S29GL512P S29GL256P S29GL128P Waveform Inputs Changing from L to H Outputs Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State High Z Switching Waveforms Figure Input Waveforms and Measurement Levels VIO V Input Note If VIO < VCC, the input measurement reference level is VIO. Measurement Level VIO Output Page 50 of 82 S29GL01GP S29GL512P S29GL256P S29GL128P DC Characteristics S29GL-P DC Characteristics CMOS Compatible Parameter Symbol Parameter Description Notes Test Conditions Input Load Current Secured Silicon Sector Initial Release. Erase and Program Operations table Changed tBUSY to a maximum specification. Changed tACC, tCE specifications on 128 Mb, 256 Mb, and 512 Mb devices. Added 90 and 100 ns speed options. Write Buffer Programming Operation, Sector Erase Operation figures Deleted “Wait 4 ms” box from flowcharts. Lock Register Program Algorithm figure Deleted “Wait 4 ms” box from flowchart. Modified tRC, tACC, tCE, tOE specifications. Changed tDS specification, deleted write cycle time note. Changed all specifications in table. Changed data sheet status to Preliminary. Deleted references to requirement for external WP# pull-up. Max. Read Access Times table Added note. Deleted note from section. Reset Timings figure Deleted note. S29GL-P Sector Protection Command Definitions tables Changed “Global Non-Volatile Freeze” to “Global Volatile Freeze”. CMOS Compatible table Changed ICC1 maximum current for 5 MHz and MHz test conditions. Corrected address range for top waveform. Changed speed options for S29GL512P Corrected samples OPN valid combinations changed speed options for S29GL512P Clarified ball “D1” connection Clarified pin “30” connection Added recommendation statement Added recommendation statement Removed “Erase” from title and flow chart Sections “Factory Locked Secured Silicon Sector” & “Customer Lockable Secured Silicon Sector” clarified shipping options Changed tRH from “Max” to “Min” value Added section Fixed cross-references that were not live hyperlinks. Changed timing specs and waveforms Page 75 of 82 S29GL01GP S29GL512P S29GL256P S29GL128P Section New commercial operating temperature option Operating Ranges New operating temperature range Modified Test Conditions Erase and Programming Performance Chip Program Time removed comment Sector Protection Command Definition, x16 Table Corrected Lock Register “Read” address Advance Information on S29GL-R 65 nm MirrorBit Hardware Reset# and Power-up Sequence Power-Up Sequence Timings Table modified Note 2 - reduced timing from 500 µs to 300 µs Changed document status to Full Production. DC Characteristics Sector Protection Command Definitions x16 & x8 tables Changed Max values for Input Load Current ILI Changed Lock Register Read command from “DATA” to “RD” Figure Write Operation Status Flowchart Updated flowchart Removed RFU description Changed all RFU pins to NC pins Figure 56-pin Standard TSOP Top View Changed all RFU pins to NC pins Table Autoselect Exit Table Chip Erase Changed cycle description to Auto Select Exit Command Changed address of last C source code command from 0x000h to 0x555h Erase Suspend/Erase Resume Changed first paragraph, second sentence to sector address is “don't care” for Erase Suspend Changed sixth paragraph, second sentence to sector address is “don't care” for Erase Suspend Tables Program Suspend Program Resume Unlock Bypass Entry Unlock Bypass Program Unlock Bypass Reset Unlock Bypass Writing Commands/Command Sequence WP#/ACC Method Added Byte Address to tables Third paragraph, first sentence added unlock bypass Sector Erase and unlock bypass Chip Erase as valid commands Changed paragraph, third sentence to sector address of exit command is “don't care”. Changed tables listed in fourth sentence to Table Changed table listed in Note section to Secured Silicon Sector Entry/Exit Command Sequence Added source code for program under Table Table Secured Silicon Sector Exit Changed Byte and Word addresses of Exit Cycle to “XXXh” Figure Test Setup Changed test setup to show only a load of CL Table Test Specification Removed Output Load Test Condition Table S29GL-P Erase and Program Operations Table S29GL-P Alternate CE# Controlled Erase and Program Operations Removed tGHWL Changed description of tGHEL to OE# High to CE# Low Change Note 2 to “DC Characteristics” TSOP Pin and BGA Package Capacitance Changed RESET# values. Page 76 of 82 S29GL01GP S29GL512P S29GL256P S29GL128P Section Table S29GL-P Memory Array Command Definitions, x16 Table S29GL-P Memory Array Command Definitions, x8 Table System Interface String Description Changed number of cycles for Device ID to 6 Changed number of cycles for Write Buffer to 6 Added note regarding the number of cycles in a Write Buffer command Changed number of cycles for Device ID to 6 Changed number of cycles for Write Buffer to 6 Added note regarding the number of cycles in a Write Buffer command Changed value of address 20h x16 to 0009h and description to “Typical timeout for buffer write 2n µs” Added values of 128 Mb-512 Mb densities to address 22h x16 For address 31h x16 corrected x8 address Updated access time options for S29GL512P Updated speed options for S29GL512P Added note Clarified tSEA Clarified tSEA Sub-section RY/BY# Clarified last sentence Corrected Note numbering Corrected Address for 3rd Cycle of Write-To-Buffer-Abort Reset command Changed value of address 20h x16 to 0006h Updated section title to Advance Information on S29GL-S Eclipse 65 nm MirrorBit Power-On and Warm Reset Timing Updated section to cover GL-S Power-On and Warm Reset Timing Document History Page Document Title:S29GL01GP, S29GL512P, S29GL256P, S29GL128P 1 Gbit, 512, 256, 128 Mbit, 3 V, Page Flash with 90 nm MirrorBit Process Technology Document Number 002-00886 ECN No. - Orig. of Submission Change RYSU 10/29/2004 A0:Initial release Description of Change RYSU 10/19/2006 A2:Global Changed speed options for S29GL01GP RYSU 11/21/2006 A3:AC Characteristics Erase and Program Operations table Changed tBUSY to a maximum specification. Page 77 of 82 S29GL01GP S29GL512P S29GL256P S29GL128P Document History Page Continued Document Title:S29GL01GP, S29GL512P, S29GL256P, S29GL128P 1 Gbit, 512, 256, 128 Mbit, 3 V, Page Flash with 90 nm MirrorBit Process Technology Document Number 002-00886 ECN No. - Orig. of Change RYSU Submission Date Description of Change 12/18/2006 A4:Global Changed tACC, tCE specifications on 128 Mb, 256 Mb, and 512 Mb devices. Added 90 and 100 ns speed options. Write Buffer Programming, Sector Erase Write Buffer Programming Operation, Sector Erase Operation figures: Deleted “Wait 4 ms” box from flowcharts. Password Protection Method Lock Register Program Algorithm figure Deleted “Wait 4 ms” box from flowchart. Read-only Operations table Modified tRC, tACC, tCE, tOE specifications. Program and Erase Operations tables Changed tDS specification, deleted write cycle time note. TSOP Pin and BGA Capacitance table Changed all specifications in table. RYSU 05/18/2007 A5:Global Changed data sheet status to Preliminary. Deleted references to requirement for external WP# pull-up. Performance Characteristics Max. Read Access Times table Added note. Hardware Reset Deleted note from section. AC Characteristics Reset Timings figure Deleted note. Command Definitions tables S29GL-P Sector Protection Command Definitions tables Changed “Global Ordering Information Corrected samples OPN valid combinations changed speed options for S29GL512P 64-Ball Fortified BGA Clarified ball “D1” connection 56-Pin TSOP Clarified pin “30” connection Autoselect Added recommendation statement Accelerated Program Added recommendation statement Persistent Protection Bits Removed “Erase” from title and flow chart Secured Silicon Sector Sections “Factory Locked Secured Silicon Sector” & “Customer Lockable Secured Silicon Sector”: clarified shipping options Power-up Sequence Timing Changed tRH from “Max” to “Min” value Advance Information on S29GL-R 65 nm MirrorBit Hardware Reset RESET# and Power-up Sequence Added section Global Fixed cross-references that were not live hyperlinks Page 78 of 82 S29GL01GP S29GL512P S29GL256P S29GL128P Document History Page Continued Document Title:S29GL01GP, S29GL512P, S29GL256P, S29GL128P 1 Gbit, 512, 256, 128 Mbit, 3 V, Page Flash with 90 nm MirrorBit Process Technology Document Number 002-00886 ECN No. - Orig. of Change RYSU Submission Date Description of Change 11/08/2007 A7:Advance Information on S29GL-R 65 nm MirrorBit Hardware Reset RESET# and Power-up Sequence Changed timing specs and waveforms RYSU 11/28/2007 A8:Ordering Information New commercial operating temperature option Operating Ranges New operating temperature range RYSU 02/15/2008 A9:Electrical Specification Modified Test Conditions Erase and Programming Performance Chip Program Time removed comment Sector Protection Command Definition,x16 Table Corrected Lock Register “Read” address Advance Information on S29GL-R 65 nm MirrorBit Hardware Reset RESET# and Power-up Sequence Power-Up Sequence Timings Table modified Note 2 - reduced timing from 500 us to 300 us RYSU 03/19/2008 A10:Global Changed document status to Full Production. DC Characteristics Changed Max values for Input Load Current ILI Sector Protection Command Definitions x16 & x8 tables Changed Lock Register Read command from “DATA” to “RD” Figure Write Operation Status Flowchart Updated flowchart Page 79 of 82 S29GL01GP S29GL512P S29GL256P S29GL128P Document History Page Continued Document Title:S29GL01GP, S29GL512P, S29GL256P, S29GL128P 1 Gbit, 512, 256, 128 Mbit, 3 V, Page Flash with 90 nm MirrorBit Process Technology Document Number 002-00886 ECN No. - Orig. of Change RYSU Submission Date Description of Change 11/20/2009 A12:Table Input/Output Descriptions Removed RFU description Figure 64-ball Fortified Ball Grid Array Changed all RFU pins to NC pins Figure 56-pin Standard TSOP Top View Changed all RFU pins to NC pins Table Autoselect Exit Changed cycle description to Auto Select Exit Command Table Chip Erase Changed address of last C source code command from 0x000h to 0x555h Erase Suspend/Erase Resume Changed first paragraph, second sentence to sector address is “don't care” for Erase Suspend Changed sixth paragraph, second sentence to sector address is “don't care” for Erase Suspend Tables Program Suspend Program Resume Unlock Bypass Entry Unlock Bypass Program Unlock Bypass Reset Added Byte Address to tables Unlock Bypass Third paragraph, first sentence added unlock bypass Sector Erase and unlock bypass Chip Erase as valid commands Changed paragraph, third sentence to sector address of exit command is “don't care”. Writing Commands/Command Sequence Changed tables listed in fourth sentence to Table WP#/ACC Method Changed table listed in Note section to Secured Silicon Sector Entry/Exit Command Sequence Added source code for program under Table Secured Silicon Sector Exit Changed Byte and Word addresses of Exit Cycle to “XXXh” Figure Test Setup Changed test setup to show only a load of CL Table Test Specification Removed Output Load Test Condition Table S29GL-P Erase and Program Operations Removed tGHWL Table S29GL-P Alternate CE# Controlled Erase and Program Operations Changed description of tGHEL to OE# High to CE# Low Change Note 2 to “DC Characteristics TSOP Pin and BGA Package Capacitance Changed RESET# values. Page 80 of 82 S29GL01GP S29GL512P S29GL256P S29GL128P Document History Page Continued Document Title:S29GL01GP, S29GL512P, S29GL256P, S29GL128P 1 Gbit, 512, 256, 128 Mbit, 3 V, Page Flash with 90 nm MirrorBit Process Technology Document Number 002-00886 ECN No. - Orig. of Change RYSU Submission Date Description of Change 11/20/2008 Table S29GL-P Memory Array Command Definitions, x16 Changed number of cycles for Device ID to 6 Changed number of cycles for Write Buffer to 6 Added note regarding the number of cycles in a Write Buffer command Table S29GL-P Memory Array Command Definitions, x8 Changed number of cycles for Device ID to 6 Changed number of cycles for Write Buffer to 6 Added note regarding the number of cycles in a Write Buffer command Table System Interface String Changed value of address 20h x16 to 0009h and description to “Typical timeout for buffer write 2n us” Added values of 128 Mb-512 Mb densities to address 22h x16 Table Device Geometry Definition For address 31h x16 corrected x8 address RYSU 11/17/2010 A13:Performance Characteristics Updated access time options for S29GL512P Ordering Information Updated speed options for S29GL512P Read Operation Timing Figure Added note RYSU 10/22/2012 A14:Sector Erase Clarified tSEA Erase Suspend Clarified tSEA Writing Commands/Command Sequences Sub-section RY/BY# Clarified last sentence Figure Advanced Sector Protection/Unprotection Corrected Note numbering Table S29GL-P Memory Array Command Definitions, x8 Corrected Address for 3rd Cycle of Write-To-Buffer-Abort Reset command Table System Interface String Changed value of address 20h x16 to 0006h Advance Information on S29GL-R 65 nm MirrorBit Hardware Reset RESET# and Power-up Sequence Updated section title to Advance Information on S29GL-S Eclipse 65 nm MirrorBit Power-On and Warm Reset Timing Updated section to cover GL-S Power-On and Warm Reset Timing 5051914 RYSU 12/16/2015 Updated to Cypress template Page 81 of 82 S29GL01GP S29GL512P S29GL256P S29GL128P Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Clocks & Buffers cypress.com/go/clocks cypress.com/go/interface Lighting & Power Control............ cypress.com/go/powerpsoc cypress.com/go/memory PSoC Touch Sensing cypress.com/go/touch USB Wireless/RF cypress.com/go/wireless Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 4 \| PSoC 5LP Cypress Developer Community \| Forums \| Blogs \| Video \| Training Technical Support cypress.com/go/support Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 82 of 82 Eclipse , ORNAND , EcoRAM , HyperBus , HyperFlash , and combinations thereof, are trademarks and registered trademarks of Cypress Semiconductor Corp. All products and company names mentioned in this document may be the trademarks of their respective holders.

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S29GL01GP S29GL512P S29GL256P S29GL128P
1 Gbit, 512, 256, 128 Mbit, 3 V, Page Flash with 90 nm MirrorBit Process Technology

The Spansion S29GL01G/512/256/128P are Flash products fabricated on 90 nm process technology. These devices offer a fast page access time of 25 ns with a corresponding random access time as fast as 90 ns. They feature a Write Buffer that allows a maximum of 32 words/64 bytes to be programmed in one operation, resulting in faster effective programming time than standard programming algorithms. This makes these devices ideal for today’s embedded applications that require higher density, better performance and lower power consumption.

Distinctive Characteristics

Single 3V read/program/erase V

Enhanced VersatileI/O control All input levels address, control, and DQ input levels and outputs are determined by voltage on VIO input. VIO range is to VCC
90 nm MirrorBit process technology
8-word/16-byte page read buffer
32-word/64-byte write buffer reduces overall programming time for multiple-word updates

Secured Silicon Sector region 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random Electronic Serial Number Can be programmed and locked at the factory or by the customer

Uniform 64 Kword/128 Kbyte Sector Architecture S29GL01GP One thousand twenty-four sectors S29GL512P Five hundred twelve sectors S29GL256P Two hundred fifty-six sectors S29GL128P One hundred twenty-eight sectors
100,000 erase cycles per sector typical
20-year data retention typical

Offered Packages 56-pin TSOP 64-ball Fortified BGA

Suspend and Resume commands for Program and Erase operations

Write operation status bits indicate program and erase operation completion

Unlock Bypass Program command to reduce programming time

Support for CFI Common Flash Interface

Persistent and Password methods of Advanced Sector Protection

WP#/ACC input Accelerates programming time when VHH is applied for greater throughput during system production Protects first or last sector regardless of sector protection settings

Hardware reset input RESET# resets device

Ready/Busy# output RY/BY# detects program or erase cycle completion
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S29GL01GP S29GL512P S29GL256P S29GL128P

Performance Characteristics

Maximum Read Access Times ns

Density 128 & 256 Mb
512 Mb 1 Gb

Voltage Range 1

Regulated VCC Full VCC

VersatileIO VIO Regulated VCC

Full VCC VersatileIO VIO Regulated VCC

Full VCC VersatileIO VIO

Random Access Time tACC 90 100/110 100 110 120 110 120 130

Page Access Time tPACC 25

Notes
Access times are dependent on VCC and VIO operating ranges. See Ordering Information page for further details. Regulated VCC = V. Full VCC = VIO = V. VersatileIO VIO = VCC = V.

Contact a sales representative for availability.

CE# Access Time tCE 90
100/110 100 110 120 110 120 130

OE# Access Time tOE 25

Current Consumption typical values Random Access Read f = 5 MHz 8-Word Page Read f = 10 MHz Program/Erase Standby
30 mA 1 mA 50 mA 1 µA

Program & Erase Times typical values Single Word Programming Effective Write Buffer Programming VCC Per Word Effective Write Buffer Programming VHH Per Word Sector Erase Time 64 Kword Sector
60 µs 15 µs µs

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S29GL01GP S29GL512P S29GL256P S29GL128P

Contents
Ordering Information 4

Input/Output Descriptions & Logic Symbol 6

Block 7

Physical Dimensions/Connection Diagrams............. 7 Related Documents 7 Special Handling Instructions for BGA Package............ 7 ball Fortified Ball Grid Array, 11 x 13 mm. 9 Standard Thin Small Outline Package

Additional Resources 12 Application Notes 12 Specification Bulletins 12 Hardware and Software 12 Contacting 12

Product Overview 13 Memory Map 13

Device Operations 14 Device Operation Table 14 Word/Byte 15 VersatileIOTM VIO Control 15 Read 15 Page Read Mode 15 Autoselect 16 Program/Erase Operations 19 Write Operation 31 Writing Commands/Command Sequences.................. 35

Advanced Sector Protection/Unprotection 37 Lock Register 38 Persistent Protection 38 Persistent Protection Bit Lock Bit................................. 40 Password Protection Method 40 Advanced Sector Protection Software Examples 43 Hardware Data Protection Methods............................. 43

Power Conservation 44 Standby 44 Automatic Sleep 44 Hardware RESET# Input Operation............................. 44 Output Disable 44

Secured Silicon Sector Flash Memory Region 45 Factory Locked Secured Silicon Sector 45 Customer Lockable Secured Silicon Sector................. 46 Secured Silicon Sector Entry/Exit Command

Sequences 46

Electrical 48 Absolute Maximum Ratings 48 Operating 49 Test Conditions 49 Key to Switching Waveforms 49 Switching Waveforms 50 DC Characteristics 51

AC Characteristics 52

Appendix 63 Command 63 Common Flash Memory 69

Advance Information on S29GL-S Eclipse 65 nm Mirror Bit Power-On and Warm Reset Timing 73

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S29GL01GP S29GL512P S29GL256P S29GL128P
Ordering Information
The ordering part number is formed by a valid combination of the following:

S29GL01GP

F I 01 0

PACKING TYPE 0 = Tray standard Note 5 2 = 7” Tape and Reel 3 = 13” Tape and Reel

MODEL NUMBER VIO range, protection when WP# =VIL 01 = VIO = VCC = to V, highest address sector protected 02 = VIO = VCC = to V, lowest address sector protected V1 = VIO = to VCC, VCC = to V, highest address sector protected V2 = VIO = to VCC, VCC = to V, lowest address sector protected R1 = VIO = VCC = to V, highest address sector protected R2 = VIO = VCC = to V, lowest address sector protected

TEMPERATURE RANGE I = Industrial to +85°C

C = Commercial 0°C to +85°C

PACKAGE MATERIALS SET A = Pb Note 1 F = Pb-free

PACKAGE TYPE T = 56-pin Thin Small Outline Package TSOP Standard Pinout TSO56 F = 64-ball Fortified Ball Grid Array, mm pitch package LAA064

SPEED OPTION 90 = 90 ns 10 = 100 ns 11 = 110 ns 12 = 120 ns 13 = 130 ns

DEVICE NUMBER/DESCRIPTION S29GL01GP, S29GL512P, S29GL256P, S29GL128P Volt-only, 1024, 512, 256 and 128 Megabit Page-Mode Flash Memory, manufactured on 90 nm process technology

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S29GL01GP S29GL512P S29GL256P S29GL128P

Recommended Combinations Recommended Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific recommended combinations and to check on newly released combinations.

S29GL-P Valid Combinations

Base Part Number S29GL01GP

S29GL512P

S29GL128P, S29GL256P

Speed
11 12 13 11 12 13 10 11 12 10 11 12 90 10, 11 90 10, 11

Package 2 3 TA 1 , TF FA 1 , FF TA 1 , TF FA 1 , FF TA 1 , TF FA 1 , FF

Temperature 4 I, C I, C I, C I, C I, C I, C I

Model Number

R1, R2 01, 02 V1, V2 R1, R2 01, 02 V1, V2 R1, R2 01, 02 V1, V2 R1, R2 01, 02 V1, V2 R1, R2 01, 02 V1, V2 R1, R2 01, 02 V1, V2
Notes Contact a local sales representative for availability. TSOP package marking omits packing type designator from ordering part number. BGA package marking omits leading “S29” and packing type designator from ordering part number. Operating Temperature range I = Industrial to +85°C

C = Commercial 0°C to +85°C Type 0 is standard. Specify other options as required.

Packing Type 5 0, 3
0, 2, 3 0, 3
0, 2, 3 0, 3
0, 2, 3

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S29GL01GP S29GL512P S29GL256P S29GL128P

Input/Output Descriptions & Logic Symbol

Table identifies the input and output package connections provided on the device.

Input/Output Descriptions

DQ15/A-1

CE# OE# WE# VCC VIO VSS NC RY/BY#

BYTE#

RESET#

WP#/ACC

Type

Input

I/O I/O Input Supply No Connect Output

Input

Input

Input

Address lines for GL01GP for GL512P for GL256P, for GL128P.

Data input/output.

DQ15 Data input/output in word mode. A-1 LSB address input in byte mode.

Chip Enable.

Output Enable.

Write Enable.

Device Power Supply.

Versatile IO Input.

Ground.

Not connected internally.

Ready/Busy. Indicates whether an Embedded Algorithm is in progress or complete. At VIL, the device is actively erasing or programming. At High Z, the device is in ready. Selects data bus width. At VIL, the device is in byte configuration and data I/O pins DQ0DQ7 are active and DQ15/A-1 becomes the LSB address input. At VIH, the device is in word configuration and data I/O pins DQ0-DQ15 are active.

Hardware Reset. Low = device resets and returns to reading array data.

Write Protect/Acceleration Input. At VIL, disables program and erase functions in the outermost sectors. At VHH, accelerates programming automatically places device in unlock bypass mode. Should be at VIH for all other conditions. WP# has an internal pullup when unconnected, WP# is at VIH.

Page 6 of 82

Block Diagram

VCC VSS VIO

RESET#

WE# WP#/ACC

BYTE#
The VersatileIOTM VIO control allows the host system to set the voltage levels that the device generates and tolerates on all inputs and outputs address, control, and DQ signals . VIO range is to VCC. See Ordering Information on page 4 for VIO options on this device. For example, a VIO of volts allows for I/O at the or 3 volt levels, driving and receiving signals to and from other or 3 V devices on the same data bus.

Read

All memories require access time to output array data. In a read operation, data is read from one memory location at a time. Addresses are presented to the device in random order, and the propagation delay through the device causes the data on its outputs to arrive with the address on its inputs. The device defaults to reading array data after device power-up or hardware reset. To read data from the memory array, the system must first assert a valid address on Amax-A0, while driving OE# and CE# to VIL. WE# must remain at VIH. All addresses are latched on the falling edge of CE#. Data will appear on DQ15-DQ0 after address access time tACC , which is equal to the delay from stable addresses to valid output data. The OE# signal must be driven to VIL. Data is output on DQ15-DQ0 pins after the access time tOE has elapsed from the falling edge of OE#, assuming the tACC access time has been meet.

Page Read Mode

The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. The page size of the device is 8 words/16 bytes. The appropriate page is selected by the higher address bits A max -A3. Address bits A2-A0 in word mode A2 to A-1 in byte mode determine the specific word within a page. The microprocessor supplies the specific word location. The random or initial page access is equal to tACC or tCE and subsequent page read accesses as long as the locations specified by the microprocessor falls within that page is equivalent to tPACC. When CE# is de-asserted and reasserted for a subsequent access, the access time is tACC or tCE. Fast page mode accesses are obtained by keeping the “read-page addresses” constant and changing the “intra-read page” addresses.

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S29GL01GP S29GL512P S29GL256P S29GL128P

Autoselect

The Autoselect mode provides manufacturer ID, Device identification, and sector protection information, through identifier codes output from the internal register separate from the memory array on DQ7-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm see Table The Autoselect codes can also be accessed in-system.

There are two methods to access autoselect codes. One uses the autoselect command, the other applies VID on address pin A9. When using programming equipment, the autoselect mode requires VID V to V on address pin A9. Address pins must be as shown in Table

To access Autoselect mode without using high voltage on A9, the host system must issue the Autoselect command. The Autoselect command sequence may be written to an address within a sector that is either in the read or erase-suspend-read mode. The Autoselect command may not be written while the device is actively programming or erasing.

The system must write the reset command to return to the read mode or erase-suspend-read mode if the sector was previously in Erase Suspend .

It is recommended that A9 apply VID after power-up sequence is completed. In addition, it is recommended that A9 apply from VID to VIH/VIL before power-down the VCC/VIO. See Table on page 64 for command sequence details.

When verifying sector protection, the sector address must appear on the appropriate highest order address bits see Table to Table The remaining address bits are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ15-DQ0. The Autoselect codes can also be accessed in-system through the command register.

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S29GL01GP S29GL512P S29GL256P S29GL128P

Autoselect Codes, High Voltage Method

Description Manufacturer ID Spansion Product

Cycle 1 Cycle 2

Cycle 3

Amax A14

A5 A3

DQ8 to DQ15

BYTE# BYTE#

CE# OE# WE# A16 A10 A9 A7 A6 A4 A2 A1 A0 = VIH = VIL

X VID X L X L

L H 22

X VID X

DQ7 to DQ0 01h 7Eh 28h 01h

Device ID Device ID Device ID Device ID S29GL128P S29GL256P S29GL512P S29GL01GP

Cycle 1

L H 22

Cycle 2

X VID X

Cycle 3

Cycle 1 Cycle 2

Cycle 3

L H 22

X VID X

Cycle 1 Cycle 2

Cycle 3
Volatile Bits defaults to user choice upon power-up see ordering options .

Page 37 of 82

S29GL01GP S29GL512P S29GL256P S29GL128P

Lock Register
As shipped from the factory, all devices default to the persistent mode when power is applied, and all sectors are unprotected, unless otherwise chosen through the DYB ordering option see Ordering Information on page The device programmer or host system must then choose which sector protection method to use. Programming setting to “0” any one of the following two one-time programmable, non-volatile bits locks the part permanently in that mode:

Lock Register Persistent Protection Mode Lock Bit DQ1

Lock Register Password Protection Mode Lock Bit DQ2

Lock Register

DQ15-3 Don’t Care

Password Protection Mode Lock Bit

Persistent Protection Mode Lock Bit

Secured Silicon Sector Protection Bit

For programming lock register bits refer to Table on page 66 and Table on page

Notes If the password mode is chosen, the password must be programmed before setting the corresponding lock register bit.

After the Lock Register Bits Command Set Entry command sequence is written, reads and writes for Sector 0 are disabled, while reads from other sectors are allowed until exiting this mode.

If both lock bits are selected to be programmed to zeros at the same time, the operation aborts.

Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently disabled, and no changes to the protection scheme are allowed. Similarly, if the Persistent Mode Lock Bit is programmed, the Password Mode is permanently disabled.

After selecting a sector protection method, each sector can operate in any of the following three states:

Constantly locked. The selected sectors are protected and can not be reprogrammed unless PPB lock bit is cleared via a password, hardware reset, or power cycle.

Dynamically locked. The selected sectors are protected and can be altered via software commands.

Unlocked. The sectors are unprotected and can be erased and/or programmed.

These states are controlled by the bit types described in Section

Persistent Protection Bits

The Persistent Protection Bits are unique and nonvolatile for each sector and have the same endurances as the Flash memory. Preprogramming and verification prior to erasure are handled by the device, and therefore do not require system monitoring.

Notes Each PPB is individually programmed and all are erased in parallel.

While programming PPB for a sector, array data can be read from any other sector, except Sector 0 used for Data# Polling and the sector in which sector PPB is being programmed.

Entry command disables reads and writes for the sector selected.

Reads within that sector return the PPB status for that sector.

All Reads must be performed using the read mode.

The specific sector address A25-A16 GL01GP, A24-A16 GL512P, A23-A16 GL256P, A22-A16 GL128P are written at the same time as the program command.

If the PPB Lock Bit is set, the PPB Program or erase command does not execute and times-out without programming or erasing the PPB.

There are no means for individually erasing a specific PPB and no specific sector address is required for this operation.

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S29GL01GP S29GL512P S29GL256P S29GL128P

Exit command must be issued after the execution which resets the device to read mode and re-enables reads and writes for Sector

The programming state of the PPB for a given sector can be verified by writing a PPB Status Read Command to the device as described by the flow chart shown in Figure

Figure PPB Program Algorithm

Enter PPB Command Set.

Addr = BA

Program PPB Bit. Addr = SA

Read Byte Twice Addr = SA0

DQ6 =

Toggle?

No DQ5 = 1?

Read Byte Twice Addr = SA0
Notes The DYBs can be set programmed to “0” or cleared erased to “1” as often as needed. When the parts are first shipped, the PPBs are cleared erased to “1” and upon power up or reset, the DYBs can be set or cleared depending upon the ordering option chosen.

If the option to clear the DYBs after power up is chosen, erased to “1” , then the sectorsmay be modified depending upon the PPB state of that sector see Table

The sectors would be in the protected state If the option to set the DYBs after power up is chosen programmed to

It is possible to have sectors that are persistently locked with sectors that are left in the dynamic state.

The DYB Set or Clear commands for the dynamic sectors signify protected or unprotectedstate of the sectors respectively. However, if there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock Bit must be cleared by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB Lock Bit once again locks the PPBs, and the device operates normally again.

To achieve the best protection, it is recommended to execute the PPB Lock Bit Set command early in the boot code and protect the boot code by holding WP#/ACC = VIL. Note that the PPB and DYB bits have the same function when WP#/ ACC = VHH as they do when ACC =VIH.

Persistent Protection Bit Lock Bit

The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors. When set programmed to “0” , it locks all PPBs and when cleared programmed to “1” , allows the PPBs to be changed. There is only one PPB Lock Bit per device.

Notes No software command sequence unlocks this bit unless the device is in the password protection mode only a hardware reset or a power-up clears this bit.

The PPB Lock Bit must be set programmed to “0” only after all PPBs are configured to the desired settings.

Password Protection Method

The Password Protection Method allows an even higher level of security than the Persistent Sector Protection Mode by requiring a 64-bit password for unlocking the device PPB Lock Bit. In addition to this password requirement, after power up and reset, the PPB Lock Bit is set “0” to maintain the password mode of operation. Successful execution of the Password Unlock command by entering the entire password clears the PPB Lock Bit, allowing for sector PPBs modifications.

Notes There is no special addressing order required for programming the password. Once the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent access.

The Password Program Command is only capable of programming “0”s. Programming a “1” after a cell is programmed as a “0” results in a time-out with the cell as a

The password is all “1”s when shipped from the factory.

All 64-bit password combinations are valid as a password.

There is no means to verify what the password is after it is set.

The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the data bus and further password programming.

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S29GL01GP S29GL512P S29GL256P S29GL128P

The Password Mode Lock Bit is not erasable. The lower two address bits are valid during the Password Read, Password Program, and Password Unlock. The exact password must be entered in order for the unlocking function to occur. The Password Unlock command cannot be issued any faster than 1 µs at a time to prevent a hacker from running through
all the 64-bit combinations in an attempt to correctly match a password. Approximately 1 µs is required for unlocking the device after the valid 64-bit password is given to the device. Password verification is only allowed during the password programming operation. All further commands to the password region are disabled and all operations are ignored. If the password is lost after setting the Password Mode Lock Bit, there is no way to clear the PPB Lock Bit. Entry command sequence must be issued prior to any of any operation and it disables reads and writes for Sector

Reads and writes for other sectors excluding Sector 0 are allowed. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program or erase command to a protected sector enables status polling and returns to read mode without having
modified the contents of the protected sector. The programming of the DYB, PPB, and PPB Lock for a given sector can be verified by writing individual status read
commands DYB Status, PPB Status, and PPB Lock Status to the device.

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S29GL01GP S29GL512P S29GL256P S29GL128P

Figure Lock Register Program Algorithm

Write Unlock Cycles Address 555h, Data AAh Address 2AAh, Data 55h

Unlock Cycle 1 Unlock Cycle 2

Write Enter Lock Register Command:

Address 555h, Data 40h

Program Lock Register Data Address XXXh, Data A0h Address XXXh*, Data PD

XXXh = Address don’t care Program Data PD See text for Lock Register definitions Caution Lock register can only be progammed once.

Perform Polling Algorithm see Write Operation Status
flowchart

Yes Done?

DQ5 = 1?

Error condition Exceeded Timing Limits

PASS. Write Lock Register Exit Command:

Address XXXh, Data 90h Address XXXh, Data 00h Device returns to reading array.
Notes Operating ranges define those limits between which the functionality of the device is guaranteed. See also Ordering Information on page For valid VCC/VIO range combinations, see Ordering Information on page The I/Os do not operate at 3 V when VIO = V.

Test Conditions

Figure Test Setup

Device Under Test

Test Specifications

Test Condition Output Load Capacitance, CL including jig capacitance Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels See Note Output timing measurement reference levels

Note If VIO < VCC, the reference level is VIO.

All Speeds
5 0.5VIO VIO

Unit

Key to Switching Waveforms

Waveform

Inputs

Steady

Changing from H to L

Outputs

Page 49 of 82

S29GL01GP S29GL512P S29GL256P S29GL128P

Waveform

Inputs

Changing from L to H

Outputs

Don’t Care, Any Change Permitted

Changing, State Unknown

Does Not Apply

Center Line is High Impedance State High Z

Switching Waveforms

Figure Input Waveforms and Measurement Levels

VIO V

Input

Note If VIO < VCC, the input measurement reference level is VIO.

Measurement Level

VIO Output

Page 50 of 82

S29GL01GP S29GL512P S29GL256P S29GL128P

DC Characteristics

S29GL-P DC Characteristics CMOS Compatible

Parameter Symbol

Parameter Description Notes

Test Conditions

Input Load Current
Secured Silicon Sector

Initial Release.

Erase and Program Operations table Changed tBUSY to a maximum specification.

Changed tACC, tCE specifications on 128 Mb, 256 Mb, and 512 Mb devices. Added 90 and 100 ns speed options. Write Buffer Programming Operation, Sector Erase Operation figures Deleted “Wait 4 ms” box from flowcharts. Lock Register Program Algorithm figure Deleted “Wait 4 ms” box from flowchart. Modified tRC, tACC, tCE, tOE specifications. Changed tDS specification, deleted write cycle time note. Changed all specifications in table.

Changed data sheet status to Preliminary. Deleted references to requirement for external WP# pull-up. Max. Read Access Times table Added note. Deleted note from section. Reset Timings figure Deleted note. S29GL-P Sector Protection Command Definitions tables Changed “Global Non-Volatile Freeze” to “Global Volatile Freeze”. CMOS Compatible table Changed ICC1 maximum current for 5 MHz and MHz test conditions. Corrected address range for top waveform.

Changed speed options for S29GL512P Corrected samples OPN valid combinations changed speed options for S29GL512P Clarified ball “D1” connection Clarified pin “30” connection Added recommendation statement Added recommendation statement Removed “Erase” from title and flow chart Sections “Factory Locked Secured Silicon Sector” & “Customer Lockable Secured Silicon Sector” clarified shipping options Changed tRH from “Max” to “Min” value

Added section

Fixed cross-references that were not live hyperlinks.

Changed timing specs and waveforms

Page 75 of 82

S29GL01GP S29GL512P S29GL256P S29GL128P

Section
New commercial operating temperature option

Operating Ranges

New operating temperature range

Modified Test Conditions

Erase and Programming Performance

Chip Program Time removed comment

Sector Protection Command Definition, x16 Table

Corrected Lock Register “Read” address

Advance Information on S29GL-R 65 nm MirrorBit Hardware Reset# and Power-up Sequence

Power-Up Sequence Timings Table modified Note 2 - reduced timing from 500 µs to 300 µs

Changed document status to Full Production.

DC Characteristics

Sector Protection Command Definitions x16 & x8 tables

Changed Max values for Input Load Current ILI Changed Lock Register Read command from “DATA” to “RD”
Figure Write Operation Status Flowchart Updated flowchart

Removed RFU description Changed all RFU pins to NC pins

Figure 56-pin Standard TSOP Top View Changed all RFU pins to NC pins

Table Autoselect Exit Table Chip Erase

Changed cycle description to Auto Select Exit Command Changed address of last C source code command from 0x000h to 0x555h

Erase Suspend/Erase Resume

Changed first paragraph, second sentence to sector address is “don't care” for Erase Suspend Changed sixth paragraph, second sentence to sector address is “don't care” for Erase Suspend

Tables Program Suspend Program Resume Unlock Bypass Entry Unlock Bypass Program Unlock Bypass Reset

Unlock Bypass

Writing Commands/Command Sequence WP#/ACC Method

Added Byte Address to tables

Third paragraph, first sentence added unlock bypass Sector Erase and unlock bypass Chip Erase as valid commands Changed paragraph, third sentence to sector address of exit command is “don't care”. Changed tables listed in fourth sentence to Table Changed table listed in Note section to

Secured Silicon Sector Entry/Exit Command Sequence

Added source code for program under Table

Table Secured Silicon Sector Exit

Changed Byte and Word addresses of Exit Cycle to “XXXh”

Figure Test Setup

Changed test setup to show only a load of CL

Table Test Specification

Removed Output Load Test Condition

Table S29GL-P Erase and Program Operations

Table S29GL-P Alternate CE# Controlled Erase and Program Operations

Removed tGHWL

Changed description of tGHEL to OE# High to CE# Low Change Note 2 to “DC Characteristics”

TSOP Pin and BGA Package Capacitance Changed RESET# values.

Page 76 of 82

S29GL01GP S29GL512P S29GL256P S29GL128P

Section

Table S29GL-P Memory Array Command Definitions, x16

Table S29GL-P Memory Array Command Definitions, x8

Table System Interface String
Description Changed number of cycles for Device ID to 6 Changed number of cycles for Write Buffer to 6 Added note regarding the number of cycles in a Write Buffer command Changed number of cycles for Device ID to 6 Changed number of cycles for Write Buffer to 6 Added note regarding the number of cycles in a Write Buffer command Changed value of address 20h x16 to 0009h and description to “Typical timeout for buffer write 2n µs” Added values of 128 Mb-512 Mb densities to address 22h x16 For address 31h x16 corrected x8 address

Updated access time options for S29GL512P Updated speed options for S29GL512P Added note

Clarified tSEA Clarified tSEA Sub-section RY/BY# Clarified last sentence

Corrected Note numbering

Corrected Address for 3rd Cycle of Write-To-Buffer-Abort Reset command

Changed value of address 20h x16 to 0006h Updated section title to Advance Information on S29GL-S Eclipse 65 nm MirrorBit Power-On and Warm Reset Timing Updated section to cover GL-S Power-On and Warm Reset Timing

Document History Page

Document Title:S29GL01GP, S29GL512P, S29GL256P, S29GL128P 1 Gbit, 512, 256, 128 Mbit, 3 V, Page Flash with 90 nm MirrorBit Process Technology Document Number 002-00886

ECN No. -

Orig. of Submission

Change

RYSU 10/29/2004 A0:Initial release

Description of Change

RYSU 10/19/2006 A2:Global

Changed speed options for S29GL01GP

RYSU 11/21/2006 A3:AC Characteristics Erase and Program Operations table Changed tBUSY
to a maximum specification.

Page 77 of 82

S29GL01GP S29GL512P S29GL256P S29GL128P

Document History Page Continued

Document Title:S29GL01GP, S29GL512P, S29GL256P, S29GL128P 1 Gbit, 512, 256, 128 Mbit, 3 V, Page Flash with 90 nm MirrorBit Process Technology Document Number 002-00886

ECN No. -

Orig. of Change

RYSU

Submission Date

Description of Change
12/18/2006 A4:Global Changed tACC, tCE specifications on 128 Mb, 256 Mb, and 512 Mb
devices. Added 90 and 100 ns
speed options.

Write Buffer Programming, Sector Erase Write Buffer Programming Operation, Sector Erase Operation figures:

Deleted “Wait 4 ms” box from
flowcharts.

Password Protection Method Lock Register Program Algorithm figure Deleted “Wait 4 ms” box from flowchart.

Read-only Operations table Modified tRC, tACC, tCE, tOE specifications.

Program and Erase Operations tables Changed tDS specification, deleted write cycle time note. TSOP Pin and BGA Capacitance table Changed all specifications in table.

RYSU 05/18/2007 A5:Global

Changed data sheet status to Preliminary.

Deleted references to requirement for external WP# pull-up.

Performance Characteristics Max. Read Access Times table Added note.

Hardware Reset Deleted note from section. AC Characteristics Reset Timings figure Deleted note.

Command Definitions tables S29GL-P Sector Protection Command Definitions tables Changed “Global
Ordering Information Corrected samples OPN valid combinations changed speed options for S29GL512P
64-Ball Fortified BGA Clarified ball “D1” connection 56-Pin TSOP Clarified pin “30” connection Autoselect Added recommendation statement Accelerated Program Added recommendation statement Persistent Protection Bits Removed “Erase” from title and flow chart

Secured Silicon Sector Sections “Factory Locked Secured Silicon Sector” & “Customer Lockable

Secured Silicon Sector”:
clarified shipping options

Power-up Sequence Timing Changed tRH from “Max” to “Min” value

Advance Information on S29GL-R 65 nm MirrorBit Hardware Reset

RESET# and Power-up Sequence Added section Global Fixed cross-references that were not live hyperlinks

Page 78 of 82

S29GL01GP S29GL512P S29GL256P S29GL128P

Document History Page Continued

Document Title:S29GL01GP, S29GL512P, S29GL256P, S29GL128P 1 Gbit, 512, 256, 128 Mbit, 3 V, Page Flash with 90 nm MirrorBit Process Technology Document Number 002-00886

ECN No. -

Orig. of Change

RYSU

Submission Date

Description of Change
11/08/2007 A7:Advance Information on S29GL-R 65 nm MirrorBit Hardware Reset

RESET# and Power-up Sequence Changed timing specs and waveforms
RYSU 11/28/2007 A8:Ordering Information New commercial operating temperature option

Operating Ranges New operating temperature range

RYSU 02/15/2008 A9:Electrical Specification Modified Test Conditions

Erase and Programming Performance Chip Program Time removed
comment

Sector Protection Command Definition,x16 Table Corrected Lock Register “Read” address

Advance Information on S29GL-R 65 nm MirrorBit Hardware Reset

RESET# and Power-up Sequence Power-Up Sequence Timings Table modified Note 2 - reduced timing from 500 us to 300 us

RYSU 03/19/2008 A10:Global Changed document status to Full Production.

DC Characteristics Changed Max values for Input Load Current ILI

Sector Protection Command Definitions
x16 & x8 tables Changed Lock Register Read command from “DATA” to “RD”
Figure Write Operation Status

Flowchart Updated flowchart

Page 79 of 82

S29GL01GP S29GL512P S29GL256P S29GL128P

Document History Page Continued

Document Title:S29GL01GP, S29GL512P, S29GL256P, S29GL128P 1 Gbit, 512, 256, 128 Mbit, 3 V, Page Flash with 90 nm MirrorBit Process Technology Document Number 002-00886

ECN No. -

Orig. of Change

RYSU

Submission Date

Description of Change
11/20/2009 A12:Table Input/Output Descriptions Removed RFU description Figure 64-ball Fortified Ball Grid Array Changed all RFU pins to NC pins

Figure 56-pin Standard TSOP Top View

Changed all RFU pins to NC pins

Table Autoselect Exit Changed cycle description to Auto Select Exit

Command Table Chip Erase Changed address of last C source code command from 0x000h to 0x555h

Erase Suspend/Erase Resume Changed first paragraph, second sentence to sector address is “don't care” for Erase Suspend Changed sixth paragraph, second sentence to sector address is “don't care” for Erase Suspend

Tables Program Suspend Program Resume Unlock Bypass Entry Unlock Bypass Program Unlock Bypass Reset Added Byte Address to tables

Unlock Bypass Third paragraph, first sentence added unlock bypass Sector Erase and unlock bypass Chip Erase as valid commands Changed paragraph, third sentence to sector address of exit command is “don't care”.

Writing Commands/Command Sequence Changed tables listed in fourth sentence to Table WP#/ACC Method Changed table listed in Note section to

Secured Silicon Sector Entry/Exit Command Sequence Added source code for program under Table Secured Silicon Sector Exit Changed Byte and Word addresses of Exit Cycle to “XXXh” Figure Test Setup Changed test setup to show only a load of CL Table Test Specification Removed Output Load Test Condition

Table S29GL-P Erase and Program Operations Removed tGHWL

Table S29GL-P Alternate CE# Controlled Erase and Program

Operations Changed description of tGHEL to OE# High to CE# Low Change Note 2 to “DC Characteristics

TSOP Pin and BGA Package Capacitance Changed RESET# values.

Page 80 of 82

S29GL01GP S29GL512P S29GL256P S29GL128P

Document History Page Continued

Document Title:S29GL01GP, S29GL512P, S29GL256P, S29GL128P 1 Gbit, 512, 256, 128 Mbit, 3 V, Page Flash with 90 nm MirrorBit Process Technology Document Number 002-00886

ECN No. -

Orig. of Change

RYSU

Submission Date

Description of Change
11/20/2008 Table S29GL-P Memory Array Command Definitions, x16 Changed number of cycles for Device ID to 6

Changed number of cycles for Write Buffer to 6

Added note regarding the number of cycles in a Write Buffer command

Table S29GL-P Memory Array Command Definitions, x8 Changed number of cycles for Device ID to 6 Changed number of cycles for Write Buffer to 6 Added note regarding the number of cycles in a Write Buffer command

Table System Interface String Changed value of address 20h x16 to 0009h and description to “Typical timeout for buffer write 2n us” Added values of 128 Mb-512 Mb densities to address 22h x16 Table Device Geometry Definition For address 31h x16 corrected x8 address

RYSU 11/17/2010 A13:Performance Characteristics Updated access time options for

S29GL512P
Ordering Information Updated speed options for S29GL512P Read Operation Timing Figure Added note

RYSU 10/22/2012 A14:Sector Erase Clarified tSEA

Erase Suspend Clarified tSEA

Writing Commands/Command Sequences

Sub-section RY/BY# Clarified last sentence

Figure Advanced Sector Protection/Unprotection Corrected Note numbering

Table S29GL-P Memory Array Command Definitions, x8 Corrected Address for 3rd Cycle of Write-To-Buffer-Abort Reset command Table System Interface String Changed value of address 20h x16 to 0006h

Advance Information on S29GL-R 65 nm MirrorBit Hardware Reset

RESET# and Power-up Sequence Updated section title to Advance Information on S29GL-S Eclipse 65 nm MirrorBit Power-On and Warm Reset Timing Updated section to cover GL-S Power-On and Warm Reset Timing
5051914 RYSU 12/16/2015 Updated to Cypress template

Page 81 of 82

S29GL01GP S29GL512P S29GL256P S29GL128P

Sales, Solutions, and Legal Information

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Datasheet ID: S29GL01GP12FAI010 508316