FM1608B-SGTR

FM1608B-SGTR Datasheet

FM1608B

Part	Datasheet
FM1608B-SGTR	FM1608B-SGTR (pdf)

Related Parts	Information
FM1608B-SG	FM1608B-SG

PDF Datasheet Preview
FM1608B 64-Kbit 8 K x 8 Bytewide F-RAM Memory 2-Mbit 128 K x 16 F-RAM Memory • 64-Kbit ferroelectric random access memory F-RAM logically organized as 8 K x 8 High-endurance 100 trillion 1014 read/writes 151-year data retention see the Data Retention and Endurance table NoDelay writes Advanced high-reliability ferroelectric process • SRAM and EEPROM compatible Industry-standard 8 K x 8 SRAM and EEPROM pinout 70-ns access time, 130-ns cycle time • Superior to battery-backed SRAM modules No battery concerns Monolithic reliability True surface mount solution, no rework steps Superior for moisture, shock, and vibration Resistant to negative voltage undershoots • Low power consumption Active current 15 mA max Standby current 25 typ • Voltage operation VDD = V to V Logic Block Diagram • Industrial temperature C to +85 C • 28-pin small outline integrated circuit SOIC package • Restriction of hazardous substances RoHS compliant Functional Overview The FM1608B is a 8 K x 8 nonvolatile memory that reads and writes similar to a standard SRAM. A ferroelectric random access memory or F-RAM is nonvolatile, which means that data is retained after power is removed. It provides data retention for over 151 years while eliminating the reliability concerns, functional disadvantages, and system design complexities of battery-backed SRAM BBSRAM . Fast write timing and high write endurance make the F-RAM superior to other types of memory. The FM1608B operation is similar to that of other RAM devices and therefore, it can be used as a drop-in replacement for a standard SRAM in a system. Minimum read and write cycle times are equal. The F-RAM memory is nonvolatile due to its unique ferroelectric memory process. These features make the FM1608B ideal for nonvolatile memory applications requiring frequent or rapid writes. The device is available in a 28-pin SOIC surface mount package. Device specifications are guaranteed over the industrial temperature range °C to +85 °C. A12-0 A12-0 8Kx8 F-RAM Array Address Latch and Decoder Control Logic I/O Latch & Bus Driver DQ 7-0 • San Jose, CA 95134-1709 • 408-943-2600 FM1608B Contents Pinout 3 Pin Definitions 3 Device Operation 4 Memory Architecture 4 Memory 4 Read Operation 4 Write Operation 4 Pre-charge 4 Endurance 4 F-RAM Design 5 Maximum 7 Operating 7 DC Electrical Characteristics 7 Data Retention and Endurance 7 Capacitance 8 Thermal 8 AC Test Conditions 8 AC Switching Characteristics 9 SRAM Read Cycle 9 SRAM Write 10 Power Cycle Timing 12 Functional Truth 13 Ordering 14 Ordering Code Definitions 14 Package 15 Acronyms 16 Document Conventions 16 Units of Measure 16 Document History Page 17 Sales, Solutions, and Legal Information 18 Worldwide Sales and Design Support....................... 18 Products 18 Solutions 18 Cypress Developer 18 Technical Support 18 Page 2 of 18 FM1608B Pinout NC A12 A7 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS Figure 28-pin SOIC pinout 28-pin SOIC 23 Top view 9 not to scale 20 WE NC A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 Pin Definitions Pin Name I/O Type Input Address inputs The 13 address lines select one of 8,192 bytes in the F-RAM array. Input/Output Data I/O Lines 8-bit bidirectional data bus for accessing the F-RAM array. Input Write Enable A write cycle begins when WE is asserted. Asserting WE LOW causes the FM1608B to write the contents of the data bus to the address location latched by the falling edge of CE. Input Chip Enable The device is selected when CE is LOW. Asserting CE LOW causes the address to be latched internally. Address changes that occur after CE goes LOW will be ignored until the next falling edge occurs. Input Output Enable When OE is LOW, the FM1608B drives the data bus when the valid read data is available. Deasserting OE HIGH tristates the DQ pins. Ground for the device. Must be connected to the ground of the system. VDD Power supply Power supply input to the device. No connect No connect. This pin is not connected to the die. Page 3 of 18 FM1608B Device Operation The FM1608B is a bytewide F-RAM memory logically organized as 8,192 x 8 and accessed using an industry-standard parallel interface. All data written to the part is immediately nonvolatile with no delay. Functional operation of the F-RAM memory is the same as SRAM type devices, except the FM1608B requires a falling edge of CE to start each memory cycle. See the Functional Truth Table on page 13 for a complete description of read and write modes. Memory Architecture Users access 8,192 memory locations, each with 8 data bits through a parallel interface. The complete 13-bit address specifies each of the 8,192 bytes uniquely. The F-RAM array is organized as 1024 rows of 8-bytes each. This row segmentation has no effect on operation, however the user can group data into blocks by its endurance characteristics as explained in the Endurance section. The cycle time is the same for read and write memory operations. This simplifies memory controller logic and timing circuits. Likewise the access time is the same for read and write memory operations. When CE is deasserted HIGH, a pre-charge operation begins, and is required of every memory cycle. Thus unlike SRAM, the access and cycle times are not equal. Writes occur immediately at the end of the access with no delay. Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed. Ordering Information Ordering Code FM1608B-SG FM1608B-SGTR All the above parts are Pb-free. Package Diagram 51-85026 28-pin SOIC 51-85026 28-pin SOIC Package Type Ordering Code Definitions FM 16 08 B - SG TR Option blank = Standard TR = Tape and Reel Package Type SG = 28-pin SOIC Voltage V to V I/O Width x 8 64-Kbit Parallel F-RAM Cypress FM1608B Operating Range Industrial Page 14 of 18 Package Diagram Figure 28-pin SOIC Package Outline, 51-85026 FM1608B 51-85026 *G Page 15 of 18 Acronyms Acronym Central Processing Unit CMOS Complementary Metal Oxide Semiconductor JEDEC Joint Electron Devices Engineering Council JESD JEDEC Standards Electronic Industries Alliance F-RAM Ferroelectric Random Access Memory Input/Output Microcontroller Unit Microprocessor Unit Restriction of Hazardous Substances Read and Write SOIC Small Outline Integrated Circuit SRAM Static Random Access Memory FM1608B Document Conventions Units of Measure Symbol °C Hz kHz MHz mA ms ns % pF V W Unit of Measure degree Celsius hertz kilohertz kilohm megahertz microampere microfarad microsecond milliampere millisecond megaohm nanosecond ohm percent picofarad volt watt Page 16 of 18 FM1608B Document History Page Document Title FM1608B, 64-Kbit 8 K x 8 Bytewide F-RAM Memory Document Number 001-86211

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FM1608B
64-Kbit 8 K x 8 Bytewide F-RAM Memory
2-Mbit 128 K x 16 F-RAM Memory
• 64-Kbit ferroelectric random access memory F-RAM logically organized as 8 K x 8 High-endurance 100 trillion 1014 read/writes 151-year data retention see the Data Retention and Endurance table NoDelay writes Advanced high-reliability ferroelectric process
• SRAM and EEPROM compatible Industry-standard 8 K x 8 SRAM and EEPROM pinout 70-ns access time, 130-ns cycle time
• Superior to battery-backed SRAM modules No battery concerns Monolithic reliability True surface mount solution, no rework steps Superior for moisture, shock, and vibration Resistant to negative voltage undershoots
• Low power consumption Active current 15 mA max Standby current 25 typ
• Voltage operation VDD = V to V

Logic Block Diagram
• Industrial temperature C to +85 C
• 28-pin small outline integrated circuit SOIC package
• Restriction of hazardous substances RoHS compliant

Functional Overview

The FM1608B is a 8 K x 8 nonvolatile memory that reads and writes similar to a standard SRAM. A ferroelectric random access memory or F-RAM is nonvolatile, which means that data is retained after power is removed. It provides data retention for over 151 years while eliminating the reliability concerns, functional disadvantages, and system design complexities of battery-backed SRAM BBSRAM . Fast write timing and high write endurance make the F-RAM superior to other types of memory.

The FM1608B operation is similar to that of other RAM devices and therefore, it can be used as a drop-in replacement for a standard SRAM in a system. Minimum read and write cycle times are equal. The F-RAM memory is nonvolatile due to its unique ferroelectric memory process. These features make the FM1608B ideal for nonvolatile memory applications requiring frequent or rapid writes.

The device is available in a 28-pin SOIC surface mount package. Device specifications are guaranteed over the industrial temperature range °C to +85 °C.

A12-0

A12-0
8Kx8 F-RAM Array

Address Latch and Decoder

Control

Logic

I/O Latch & Bus Driver

DQ 7-0
• San Jose, CA 95134-1709
• 408-943-2600

FM1608B

Contents

Pinout 3 Pin Definitions 3 Device Operation 4

Memory Architecture 4 Memory 4 Read Operation 4 Write Operation 4 Pre-charge 4 Endurance 4 F-RAM Design 5 Maximum 7 Operating 7 DC Electrical Characteristics 7 Data Retention and Endurance 7 Capacitance 8 Thermal 8 AC Test Conditions 8

AC Switching Characteristics 9 SRAM Read Cycle 9 SRAM Write 10

Power Cycle Timing 12

Functional Truth 13
Ordering 14 Ordering Code Definitions 14

Package 15

Acronyms 16

Document Conventions 16 Units of Measure 16

Document History Page 17

Sales, Solutions, and Legal Information 18 Worldwide Sales and Design Support....................... 18 Products 18 Solutions 18 Cypress Developer 18 Technical Support 18

Page 2 of 18

FM1608B

Pinout

NC A12 A7

A5 A4 A3 A2 A1 A0

DQ0 DQ1 DQ2 VSS

Figure 28-pin SOIC pinout
28-pin SOIC 23

Top view
9 not to scale 20

WE NC

A8 A9 A11

OE A10

CE DQ7 DQ6 DQ5 DQ4 DQ3

Pin Definitions

Pin Name I/O Type

Input Address inputs The 13 address lines select one of 8,192 bytes in the F-RAM array.

Input/Output Data I/O Lines 8-bit bidirectional data bus for accessing the F-RAM array.

Input

Write Enable A write cycle begins when WE is asserted. Asserting WE LOW causes the FM1608B to write the contents of the data bus to the address location latched by the falling edge of CE.

Input Chip Enable The device is selected when CE is LOW. Asserting CE LOW causes the address to be
latched internally. Address changes that occur after CE goes LOW will be ignored until the next falling
edge occurs.

Input Output Enable When OE is LOW, the FM1608B drives the data bus when the valid read data is
available. Deasserting OE HIGH tristates the DQ pins.

Ground for the device. Must be connected to the ground of the system.

VDD Power supply Power supply input to the device.

No connect No connect. This pin is not connected to the die.

Page 3 of 18

FM1608B

Device Operation

The FM1608B is a bytewide F-RAM memory logically organized as 8,192 x 8 and accessed using an industry-standard parallel interface. All data written to the part is immediately nonvolatile with no delay. Functional operation of the F-RAM memory is the same as SRAM type devices, except the FM1608B requires a falling edge of CE to start each memory cycle. See the Functional Truth Table on page 13 for a complete description of read and write modes.

Memory Architecture

Users access 8,192 memory locations, each with 8 data bits through a parallel interface. The complete 13-bit address specifies each of the 8,192 bytes uniquely. The F-RAM array is organized as 1024 rows of 8-bytes each. This row segmentation has no effect on operation, however the user can group data into blocks by its endurance characteristics as explained in the Endurance section.

The cycle time is the same for read and write memory operations. This simplifies memory controller logic and timing circuits. Likewise the access time is the same for read and write memory operations. When CE is deasserted HIGH, a pre-charge operation begins, and is required of every memory cycle. Thus unlike SRAM, the access and cycle times are not equal. Writes occur immediately at the end of the access with no delay. Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed.
Ordering Information
Ordering Code

FM1608B-SG FM1608B-SGTR

All the above parts are Pb-free.

Package Diagram
51-85026 28-pin SOIC
51-85026 28-pin SOIC

Package Type
Ordering Code Definitions FM 16 08 B - SG TR

Option blank = Standard TR = Tape and Reel Package Type SG = 28-pin SOIC

Voltage V to V I/O Width x 8 64-Kbit Parallel F-RAM Cypress

FM1608B

Operating Range

Industrial

Page 14 of 18

Package Diagram

Figure 28-pin SOIC Package Outline, 51-85026

FM1608B
51-85026 *G

Page 15 of 18

Acronyms

Acronym

Central Processing Unit

CMOS

Complementary Metal Oxide Semiconductor

JEDEC Joint Electron Devices Engineering Council

JESD

JEDEC Standards

Electronic Industries Alliance

F-RAM Ferroelectric Random Access Memory

Input/Output

Microcontroller Unit

Microprocessor Unit

Restriction of Hazardous Substances

Read and Write

SOIC

Small Outline Integrated Circuit

SRAM

Static Random Access Memory

FM1608B

Document Conventions

Units of Measure

Symbol °C Hz kHz MHz mA ms ns
% pF V W

Unit of Measure degree Celsius hertz kilohertz kilohm megahertz microampere microfarad microsecond milliampere millisecond megaohm nanosecond ohm percent picofarad volt watt

Page 16 of 18

FM1608B

Document History Page

Document Title FM1608B, 64-Kbit 8 K x 8 Bytewide F-RAM Memory Document Number 001-86211

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived FM1608B-SGTR Datasheet file may be downloaded here without warranties.

Datasheet ID: FM1608B-SGTR 508268