CYW4390DKWBG

CYW4390DKWBG Datasheet

CYW4390

Part	Datasheet
CYW4390DKWBG	CYW4390DKWBG (pdf)

PDF Datasheet Preview
ADVANCE CYW4390 WICED Wi-Fi IEEE b/g/n SoC with Embedded Application Processor The Cypress CYW4390 is a single-chip device that provides the highest level of integration for applications targeting the Internet of Things and provides a complete embedded wireless system solution included in a system-on-a-chip SOC . The CYW4390 device supports all the rates specified in the IEEE b/g/n specifications. Included on-chip are an ARM Cortex-based applications processor, single stream IEEE 802.11n MAC/baseband/radio, a GHz transmit power amplifier PA , and a receive low-noise amplifier LNA . It also supports optional antenna diversity for improved RF performance in difficult environments. CYW4390 is an optimized SoC targeting embedded applications in the industrial and medical sensor, home appliances and, generally, internet-of-things space. Using advanced design techniques and process technology to reduce active and idle power, the CYW4390 is designed to address the needs of embedded devices that require minimal power consumption and compact size. It includes a power management unit which simplifies the system power topology and allows for direct operation from a battery for battery powered applications while maximizing battery life. Cypress Part Numbering Scheme Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion, there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides Cypress ordering part number that matches an existing IoT part number. Table Mapping Table for Part Number between Broadcom and Cypress Broadcom Part Number BCM4390 BCM4390DKWBG BCM4390DKWBGT CYW4390 CYW4390DKWBG CYW4390DKWBGT Cypress Part Number Acronyms and Abbreviations In most cases, acronyms and abbreviations are defined on first use. For a comprehensive list of acronyms and other terms used in Cypress documents, go to General Features • Supports battery voltage range from 3.0V to 5.25V supplies with internal switching regulator. • Programmable dynamic power management Key IEEE 802.11x Features • IEEE 802.11n compliant • Single-stream spatial multiplexing up to 72 Mbps data rate • Supports 20 MHz channels with optional SGI. • Full IEEE b/g legacy compatibility with enhanced perfor- mance • Tx and Rx low-density parity check LDPC support for improved range and power efficiency • On-chip power and low-noise amplifiers. • Internal fractional nPLL allows support for a wide range of reference clock frequencies. • 6k-bit OTP for storing board parameters • Package options 286 bump WLCSP mm x mm; mm pitch • Supports IEEE external coexistence interface to optimize bandwidth utilization with other co-located wireless technologies such as Bluetooth, LTE, GPS, or WiMAX. • Integrated ARMCR4 processor with tightly coupled memory for complete WLAN subsystem functionality, minimizing the need to wake up the applications processor for standard WLAN functions to further minimize power consumption while maintaining the ability to upgrade to future features in the field • Software architecture supported by standard WICED SDK to allow easy migration from existing discrete MCU designs and to future devices • San Jose, CA 95134-1709 • 408-943-2600 ADVANCE CYW4390 • Security support: WPA and WPA2 Personal support for powerful encryption and authentication AES and TKIP in hardware for faster data encryption and IEEE 802.11i compatibility Reference WLAN subsystem provides Compatible Extensions CCX, CCX Supports Wi-Fi Protected Setup and Wi-Fi Easy-Setup • Worldwide regulatory support Global products supported with worldwide homologated design Application Processor Features • ARM Cortex-M3 32-bit RISC processor • 448 KB RAM for application code and data execution Figure Functional Block Diagram WLAN System I/F WL_REG_ON W L_JTA G W L_G PIO VIO VBAT CYW4390 Application CPU Host I/F CLK_REQ UART SPI Flash I2S Apps_GPIO GHz WLAN Tx GHz WLAN T/R Switch MHz XTAL IoT Resources Cypress provides a wealth of data at to help you to select the right IoT device for your design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software updates. Customers can acquire technical documentation and software from the Cypress Support Community website PSIJT Versus THETAJC 59 Environmental Characteristics 59 Mechanical Information 60 Ordering Information 62 Document History 63 Sales, Solutions, and Legal Information 64 Page 3 of 64 ADVANCE CYW4390 Overview Overview The Cypress CYW4390 is a single-chip device that provides the highest level of integration for an embedded system-on-a-chip with integrated IEEE b/g/n MAC/baseband/radio and a separate ARM-Cortex M3 applications processor. It provides a small formfactor solution with minimal external components to drive down cost for mass volumes and allows for an embedded system with flexibility in size, form, and function. Comprehensive power management circuitry and software ensure the system can meet the needs of highly embedded systems that require minimal power consumption and reliable operation. Figure 2 shows the interconnect of all the major physical blocks in the CYW4390 and their associated external interfaces, which are described in greater detail in the following sections. Figure Block Diagram and IO GPIO_A[0:11] SPI Flash GPIO_B[0:11] UART4 UART1/2 UART3 I2S I2C SPI Master/Slave JTAG WAKE RESET_N CYW4390 48 MHz 448 KB RAM WLAN Core 802.11n 1x1 GHz RF Tx RF Rx Tx/Rx Switch Control Antenna Diversity 3V3 GND Features The CYW4390 supports the following features • ARM Cortex-M3 clocked at 48 MHz • 448 KB of SRAM available for the applications processor • Two high-speed 4-wire UART interfaces with operation up to 4 Mbps • Two low-speed 2-wire UART interfaces • One generic SPI master/slave interface with operation up to 24 MHz • One SPI master interface for serial flash • One I2C interface • One I2S interface • 24 x GPIOs 12 dedicated,12 with alternate functions • IEEE b/g/n 1x1 GHz radio • Single- and dual-antenna support Page 4 of 64 ADVANCE Standards Compliance The CYW4390 supports the following standards: • IEEE 802.11n • IEEE 802.11b • IEEE 802.11g • IEEE 802.11d • IEEE 802.11h • IEEE 802.11i • Security WEP WPA Personal WPA2 Personal WMM-PS U-APSD WMM-SA AES hardware accelerator TKIP hardware accelerator CKIP software support • Proprietary Protocols CCXv2 CCXv3 CCXv4 CCXv5 WFAEC The CYW4390 supports the following additional standards: • IEEE roaming between APs • IEEE management frames • IEEE Extensions IEEE 802.11e QoS enhancements as per the specification is already supported IEEE 802.11i MAC enhancements IEEE 802.11k radio resource measurement CYW4390 Page 5 of 64 ADVANCE CYW4390 Power Supplies and Power Management CYW4390 PMU Features • VBAT to 1.35Vout 275 mA nominal, 600 mA maximum Core-Buck CBUCK switching regulator • VBAT to 3.3Vout 200 mA nominal, 450 mA maximum LDO3P3 • 1.35V to 1.2Vout 100 mA nominal, 150 mA maximum LNLDO • 1.35V to 1.2out 175 mA nominal, 300 mA maximum CLDO with bypass mode for deep sleep • Additional internal LDOs not externally accessible Power Supply Topology One buck regulator, multiple LDO regulators, and a power management unit PMU are integrated into the CYW4390. All regulators are programmable via the PMU. These blocks simplify power supply design for embedded designs. A single VBAT 3.0V to 5.25V DC max and VIO supply 1.8V to 3.3V can be used, with all additional voltages being provided by the regulators in the CYW4390. Two control signals, APPS_REG_ON and WL_REG_ON, are used to power-up the regulators and take the respective core out of reset. The CBUCK CLDO and LNLDO power up when any of the reset signals are deasserted. All regulators are powered down only when both APPS_REG_ON and WL_REG_ON are deasserted. The applications processor can drive WL_REG_ON internally when the pin is externally tied to ground. The CLDO and LNLDO may be turned off/on based on the dynamic demands of the application. The CYW4390 allows for an extremely low power-consumption mode by completely shutting down the CBUCK, CLDO, and LNLDO regulators. When in this state, LPLDO1 and LPLDO2 which are low-power linear regulators that are supplied by the system VIO supply provide the CYW4390 with all the voltages it requires, further reducing leakage currents. Figure 3 shows the regulators and a typical power topology. SPI Master/Slave Interface In addition to the SPI flash interface the CYW4390 supports a secondary SPI interface with a clock frequency of up to 24 MHz to support external SPI peripherals. This interface can be configured either as a master or a slave interface. The SPI interface has various configuration options including support for active-low or active-high operation for the chip-select, active-low or active-high operation for the interrupt line and bit ordering on the MISO/MOSI lines to be either big endian or little endian. UART Interfaces UART1 and UART2 have standard 4-wire interfaces RX, TX, RTS, and CTS with adjustable baud rates from 9600 bps to Mbps. UART1 has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support high data throughput. UART2 has a smaller FIFO that is only 256-bytes. Access to the FIFOs is available to the application processor through the AHB interface and supports either DMA or CPU driven data transfer. The CYW4390 UART can perform XON/XOFF flow control and includes hardware support for the Serial Line Input Protocol SLIP . It can also perform wake-on activity. For example, activity on the RX or CTS inputs can wake the chip from a sleep state. The CYW4390 UARTs can operate correctly with other devices as long as the combined baud rate error of the two devices is within Table Example of Common Baud Rates Desired Rate 3692000 921600 460800 230400 115200 57600 38400 28800 19200 14400 9600 Actual Rate 3692308 1454544 923077 461538 230796 115385 57692 38400 28846 19200 14423 9600 Error % Page 16 of 64 ADVANCE The UART timing is shown by the combination of Figure 6 and Table Figure UART Timing UART_CTS_N 1 UART_TXD UART_RXD UART_RTS_N Midpoint of STOP bit 3 CYW4390 2 Midpoint of STOP bit Table UART Timing Specifications Ref No. Characteristics 1 Delay time, UART_CTS_N low to UART_TXD valid 2 Setup time, UART_CTS_N high before midpoint of stop bit 3 Delay time, midpoint of stop bit to UART_RTS_N high Min. Typ. Max. Unit Bit periods Bit periods Bit periods I2S Interface The CYW4390 has one I2S digital audio port, which supports both master and slave modes. The I2S SCK and I2S WS clock and word select become outputs in master mode and inputs in slave mode, while the I2S SDO is always output. The channel word length is 16 bits and the data is justified so that the MSB of the left-channel data is aligned with the MSB of the I2S, per the I2S specification. The MSB of each data word is transmitted one-bit clock cycle after the I2S WS transition, synchronous with the falling edge of the bit clock. Left-channel data is transmitted when I2S WS is low right-channel data is transmitted when I2S WS is high. Data bits sent by the CYW4390 are synchronized with the falling edge of I2S_SCLK and should be sampled by the receiver on the rising edge of I2S_SCK. In master mode, the clock rate is 48 KHz x 32 bits per frame = MHz. The master clock is generated from the input reference clock using an N/M clock divider. In the slave mode, any clock rate up to MHz is supported. Page 17 of 64 ADVANCE CYW4390 General Purpose Input and Output The CYW4390 has 24 general purpose IO GPIO pins that can be configured as input or output. Each IO can be configured to have internal pull-up or pull-down resistors. At power-on reset all IOs are configured as input with no pull. Software can configure the IOs appropriately. In power-down modes, the IOs are configured as high-Z with no pull. GPIOs are grouped into two banks of twelve GPIOs: • Bank A GPIOs have alternate functions seeTable 5 on page • Bank B GPIOs are dedicated GPIOs, except during test see Table Table Bank B GPIO Test Functions GPIO_B0 GPIO_B1 GPIO_B2 GPIO_B3 GPIO Ordering Information Part Number CYW4390DKWBG Package 286-bump WLCSP mm x mm, mm pitch Description Single-band GHz WLAN Ambient Operating Temperature to +85°C Page 62 of 64 ADVANCE CYW4390 Document History Document Title CYW4390 WICED Wi-Fi IEEE b/g/n SoC with Embedded Application Processor Document Number 002-15055 Orig. of Submission Change Description of Change 05/15/2013 4390-DS100-R Initial release 4390-DS101-R: 12/05/2013 Updated: • Significant changes throughout the document. 4390-DS102-R: Updated: • Figure 1 on page 1 • “General Features” on page 2 • “Power Supply Topology” on page 12 • Figure 3 “Typical Power Topology,” on page 13 • “External KHz Low-Power Oscillator” on page 20 • Table 4 “GPIO Port A Alternate Functions,” on page 23 • Figure 9 “WLAN PHY Block Diagram,” on page 35 • Figure 10 “Radio Functional Block Diagram,” on page 36 • “Receiver Path” on page 36 12/11/2013 • Table 8 “WLAN MAC Architecture,” on page 30 • Table 9 “WLCSP and FCFBGA Pin Descriptions,” on page 48 • Table 14 “Recommended Operating Conditions and DC Characteristics,” on page 57 • Table 16 “WLAN GHz Receiver Performance Specifications,” on page 60 • Table 19 “Core Buck Switching Regulator CBUCK Specifications,” on page 65 • Table 20 “LDO3P3 Specifications,” on page 66 • Table 24 “Typical WLAN Power Consumption,” on page 69 • Figure 14 “WLAN = OFF, APPS CPU = OFF,” on page 72 • Figure 15 “WLAN = ON, APPS CPU = OFF,” on page 73 • Figure 16 “WLAN = OFF, APPS CPU= ON,” on page 73 • Figure 18 “WLCSP Keep-Out Areas for PCB Layout View, Bumps Facing Up,” on page 76

PDF Datasheet Preview

ADVANCE

CYW4390

WICED Wi-Fi IEEE b/g/n SoC with Embedded Application Processor

The Cypress CYW4390 is a single-chip device that provides the highest level of integration for applications targeting the Internet of Things and provides a complete embedded wireless system solution included in a system-on-a-chip SOC . The CYW4390 device supports all the rates specified in the IEEE b/g/n specifications. Included on-chip are an ARM Cortex-based applications processor, single stream IEEE 802.11n MAC/baseband/radio, a GHz transmit power amplifier PA , and a receive low-noise amplifier LNA . It also supports optional antenna diversity for improved RF performance in difficult environments. CYW4390 is an optimized SoC targeting embedded applications in the industrial and medical sensor, home appliances and, generally, internet-of-things space. Using advanced design techniques and process technology to reduce active and idle power, the CYW4390 is designed to address the needs of embedded devices that require minimal power consumption and compact size. It includes a power management unit which simplifies the system power topology and allows for direct operation from a battery for battery powered applications while maximizing battery life.

Cypress Part Numbering Scheme
Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion, there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides Cypress ordering part number that matches an existing IoT part number.

Table Mapping Table for Part Number between Broadcom and Cypress

Broadcom Part Number BCM4390 BCM4390DKWBG BCM4390DKWBGT

CYW4390 CYW4390DKWBG CYW4390DKWBGT

Cypress Part Number

Acronyms and Abbreviations In most cases, acronyms and abbreviations are defined on first use. For a comprehensive list of acronyms and other terms used in Cypress documents, go to

General Features
• Supports battery voltage range from 3.0V to 5.25V supplies
with internal switching regulator.
• Programmable dynamic power management

Key IEEE 802.11x Features
• IEEE 802.11n compliant
• Single-stream spatial multiplexing up to 72 Mbps data rate
• Supports 20 MHz channels with optional SGI.
• Full IEEE b/g legacy compatibility with enhanced perfor-
mance
• Tx and Rx low-density parity check LDPC support for
improved range and power efficiency
• On-chip power and low-noise amplifiers.
• Internal fractional nPLL allows support for a wide range of
reference clock frequencies.
• 6k-bit OTP for storing board parameters
• Package options 286 bump WLCSP mm x mm;
mm pitch
• Supports IEEE external coexistence interface to optimize bandwidth utilization with other co-located wireless technologies such as Bluetooth, LTE, GPS, or WiMAX.
• Integrated ARMCR4 processor with tightly coupled memory for complete WLAN subsystem functionality, minimizing the need to wake up the applications processor for standard WLAN functions to further minimize power consumption while maintaining the ability to upgrade to future features in the field
• Software architecture supported by standard WICED SDK to allow easy migration from existing discrete MCU designs and to future devices
• San Jose, CA 95134-1709
• 408-943-2600

ADVANCE

CYW4390
• Security support:

WPA and WPA2 Personal support for powerful encryption and authentication

AES and TKIP in hardware for faster data encryption and IEEE 802.11i compatibility

Reference WLAN subsystem provides Compatible Extensions CCX, CCX

Supports Wi-Fi Protected Setup and Wi-Fi Easy-Setup
• Worldwide regulatory support Global products supported with worldwide homologated design

Application Processor Features
• ARM Cortex-M3 32-bit RISC processor
• 448 KB RAM for application code and data execution

Figure Functional Block Diagram

WLAN System I/F

WL_REG_ON W L_JTA G W L_G PIO

VIO VBAT

CYW4390

Application CPU Host I/F

CLK_REQ UART SPI Flash I2S

Apps_GPIO

GHz WLAN Tx GHz WLAN

T/R Switch

MHz XTAL

IoT Resources

Cypress provides a wealth of data at to help you to select the right IoT device for your design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software updates. Customers can acquire technical documentation and software from the Cypress Support Community website
PSIJT Versus THETAJC 59 Environmental Characteristics 59 Mechanical Information 60 Ordering Information 62 Document History 63 Sales, Solutions, and Legal Information 64

Page 3 of 64

ADVANCE

CYW4390

Overview

Overview The Cypress CYW4390 is a single-chip device that provides the highest level of integration for an embedded system-on-a-chip with integrated IEEE b/g/n MAC/baseband/radio and a separate ARM-Cortex M3 applications processor. It provides a small formfactor solution with minimal external components to drive down cost for mass volumes and allows for an embedded system with flexibility in size, form, and function. Comprehensive power management circuitry and software ensure the system can meet the needs of highly embedded systems that require minimal power consumption and reliable operation. Figure 2 shows the interconnect of all the major physical blocks in the CYW4390 and their associated external interfaces, which are described in greater detail in the following sections.

Figure Block Diagram and IO

GPIO_A[0:11]

SPI Flash GPIO_B[0:11] UART4 UART1/2 UART3

I2S I2C SPI Master/Slave JTAG WAKE RESET_N

CYW4390
48 MHz
448 KB RAM

WLAN Core 802.11n
1x1 GHz

RF Tx RF Rx

Tx/Rx Switch Control Antenna Diversity
3V3 GND

Features The CYW4390 supports the following features
• ARM Cortex-M3 clocked at 48 MHz
• 448 KB of SRAM available for the applications processor
• Two high-speed 4-wire UART interfaces with operation up to 4 Mbps
• Two low-speed 2-wire UART interfaces
• One generic SPI master/slave interface with operation up to 24 MHz
• One SPI master interface for serial flash
• One I2C interface
• One I2S interface
• 24 x GPIOs 12 dedicated,12 with alternate functions
• IEEE b/g/n 1x1 GHz radio
• Single- and dual-antenna support

Page 4 of 64

ADVANCE

Standards Compliance The CYW4390 supports the following standards:
• IEEE 802.11n
• IEEE 802.11b
• IEEE 802.11g
• IEEE 802.11d
• IEEE 802.11h
• IEEE 802.11i
• Security WEP WPA Personal WPA2 Personal WMM-PS U-APSD WMM-SA AES hardware accelerator TKIP hardware accelerator CKIP software support
• Proprietary Protocols CCXv2 CCXv3 CCXv4 CCXv5 WFAEC

The CYW4390 supports the following additional standards:
• IEEE roaming between APs
• IEEE management frames
• IEEE Extensions IEEE 802.11e QoS enhancements as per the specification is already supported IEEE 802.11i MAC enhancements IEEE 802.11k radio resource measurement

CYW4390

Page 5 of 64

ADVANCE

CYW4390

Power Supplies and Power Management

CYW4390 PMU Features
• VBAT to 1.35Vout 275 mA nominal, 600 mA maximum Core-Buck CBUCK switching regulator
• VBAT to 3.3Vout 200 mA nominal, 450 mA maximum LDO3P3
• 1.35V to 1.2Vout 100 mA nominal, 150 mA maximum LNLDO
• 1.35V to 1.2out 175 mA nominal, 300 mA maximum CLDO with bypass mode for deep sleep
• Additional internal LDOs not externally accessible

Power Supply Topology One buck regulator, multiple LDO regulators, and a power management unit PMU are integrated into the CYW4390. All regulators are programmable via the PMU. These blocks simplify power supply design for embedded designs. A single VBAT 3.0V to 5.25V DC max and VIO supply 1.8V to 3.3V can be used, with all additional voltages being provided by the regulators in the CYW4390. Two control signals, APPS_REG_ON and WL_REG_ON, are used to power-up the regulators and take the respective core out of reset. The CBUCK CLDO and LNLDO power up when any of the reset signals are deasserted. All regulators are powered down only when both APPS_REG_ON and WL_REG_ON are deasserted. The applications processor can drive WL_REG_ON internally when the pin is externally tied to ground. The CLDO and LNLDO may be turned off/on based on the dynamic demands of the application. The CYW4390 allows for an extremely low power-consumption mode by completely shutting down the CBUCK, CLDO, and LNLDO regulators. When in this state, LPLDO1 and LPLDO2 which are low-power linear regulators that are supplied by the system VIO supply provide the CYW4390 with all the voltages it requires, further reducing leakage currents. Figure 3 shows the regulators and a typical power topology.
SPI Master/Slave Interface In addition to the SPI flash interface the CYW4390 supports a secondary SPI interface with a clock frequency of up to 24 MHz to support external SPI peripherals. This interface can be configured either as a master or a slave interface. The SPI interface has various configuration options including support for active-low or active-high operation for the chip-select, active-low or active-high operation for the interrupt line and bit ordering on the MISO/MOSI lines to be either big endian or little endian.

UART Interfaces UART1 and UART2 have standard 4-wire interfaces RX, TX, RTS, and CTS with adjustable baud rates from 9600 bps to Mbps. UART1 has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support high data throughput. UART2 has a smaller FIFO that is only 256-bytes. Access to the FIFOs is available to the application processor through the AHB interface and supports either DMA or CPU driven data transfer. The CYW4390 UART can perform XON/XOFF flow control and includes hardware support for the Serial Line Input Protocol SLIP . It can also perform wake-on activity. For example, activity on the RX or CTS inputs can wake the chip from a sleep state. The CYW4390 UARTs can operate correctly with other devices as long as the combined baud rate error of the two devices is within

Table Example of Common Baud Rates

Desired Rate 3692000 921600 460800 230400 115200 57600 38400 28800 19200 14400 9600

Actual Rate 3692308 1454544 923077 461538 230796 115385 57692 38400 28846 19200 14423 9600

Error %

Page 16 of 64

ADVANCE

The UART timing is shown by the combination of Figure 6 and Table Figure UART Timing

UART_CTS_N 1

UART_TXD

UART_RXD UART_RTS_N

Midpoint of STOP bit 3

CYW4390
2 Midpoint of STOP bit

Table UART Timing Specifications

Ref No.

Characteristics
1 Delay time, UART_CTS_N low to UART_TXD valid
2 Setup time, UART_CTS_N high before midpoint of stop bit
3 Delay time, midpoint of stop bit to UART_RTS_N high

Min.

Typ.

Max.

Unit

Bit periods

Bit periods

Bit periods

I2S Interface The CYW4390 has one I2S digital audio port, which supports both master and slave modes. The I2S SCK and I2S WS clock and word select become outputs in master mode and inputs in slave mode, while the I2S SDO is always output. The channel word length is 16 bits and the data is justified so that the MSB of the left-channel data is aligned with the MSB of the I2S, per the I2S specification. The MSB of each data word is transmitted one-bit clock cycle after the I2S WS transition, synchronous with the falling edge of the bit clock. Left-channel data is transmitted when I2S WS is low right-channel data is transmitted when I2S WS is high.

Data bits sent by the CYW4390 are synchronized with the falling edge of I2S_SCLK and should be sampled by the receiver on the rising edge of I2S_SCK.

In master mode, the clock rate is 48 KHz x 32 bits per frame = MHz.

The master clock is generated from the input reference clock using an N/M clock divider.

In the slave mode, any clock rate up to MHz is supported.

Page 17 of 64

ADVANCE

CYW4390

General Purpose Input and Output The CYW4390 has 24 general purpose IO GPIO pins that can be configured as input or output. Each IO can be configured to have internal pull-up or pull-down resistors. At power-on reset all IOs are configured as input with no pull. Software can configure the IOs appropriately. In power-down modes, the IOs are configured as high-Z with no pull. GPIOs are grouped into two banks of twelve GPIOs:
• Bank A GPIOs have alternate functions seeTable 5 on page
• Bank B GPIOs are dedicated GPIOs, except during test see Table

Table Bank B GPIO Test Functions

GPIO_B0 GPIO_B1 GPIO_B2 GPIO_B3

GPIO
Ordering Information

Part Number CYW4390DKWBG

Package 286-bump WLCSP mm x mm, mm pitch

Description Single-band GHz WLAN

Ambient Operating Temperature
to +85°C

Page 62 of 64

ADVANCE

CYW4390

Document History

Document Title CYW4390 WICED Wi-Fi IEEE b/g/n SoC with Embedded Application Processor Document Number 002-15055

Orig. of Submission

Change

Description of Change
05/15/2013
4390-DS100-R Initial release
4390-DS101-R:
12/05/2013 Updated:
• Significant changes throughout the document.
4390-DS102-R:

Updated:
• Figure 1 on page 1
• “General Features” on page 2
• “Power Supply Topology” on page 12
• Figure 3 “Typical Power Topology,” on page 13
• “External KHz Low-Power Oscillator” on page 20
• Table 4 “GPIO Port A Alternate Functions,” on page 23
• Figure 9 “WLAN PHY Block Diagram,” on page 35
• Figure 10 “Radio Functional Block Diagram,” on page 36
• “Receiver Path” on page 36
12/11/2013
• Table 8 “WLAN MAC Architecture,” on page 30
• Table 9 “WLCSP and FCFBGA Pin Descriptions,” on page 48
• Table 14 “Recommended Operating Conditions and DC Characteristics,” on page 57
• Table 16 “WLAN GHz Receiver Performance Specifications,” on page 60
• Table 19 “Core Buck Switching Regulator CBUCK Specifications,” on page 65
• Table 20 “LDO3P3 Specifications,” on page 66
• Table 24 “Typical WLAN Power Consumption,” on page 69
• Figure 14 “WLAN = OFF, APPS CPU = OFF,” on page 72
• Figure 15 “WLAN = ON, APPS CPU = OFF,” on page 73
• Figure 16 “WLAN = OFF, APPS CPU= ON,” on page 73
• Figure 18 “WLCSP Keep-Out Areas for PCB Layout View, Bumps Facing Up,” on page 76

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CYW4390DKWBG Datasheet file may be downloaded here without warranties.

Datasheet ID: CYW4390DKWBG 508257