5962F1120102QXA

5962F1120102QXA Datasheet

250 5962F1120102QXA

Part	Datasheet
5962F1120102QXA	5962F1120102QXA (pdf)

Related Parts	Information
5962F1120202QXA	5962F1120202QXA

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CYRS1543AV18 CYRS1545AV18 72-Mbit II+ SRAM Four-Word Burst Architecture with RadStop Technology 72-Mbit II+ SRAM Four-Word Burst Architecture with RadStop Technology Radiation Performance Radiation Data • Total Dose =300 Krad • Soft error rate both Heavy Ion and proton Heavy ions 1 x 10-10 upsets/bit-day with an external SECDED EDAC Controller • Neutrons = x 1014 N/cm2 • Dose rate = x 109 rad Si /sec • Dose rate survivability rad Si /sec = x rad Si /sec • Latch up immunity = 120 MeV.cm2/mg 125 °C Prototyping • Non-qualified CYPT1543AV18, and CYPT1545AV18 devices with same functional and timing characteristics in a 165-ball Ceramic Column Grid Array CCGA package • Separate independent read and write data ports Supports concurrent transactions • 250 MHz clock for high bandwidth • Four-word burst for reducing address bus frequency • Double data rate DDR interfaces on both read and write ports at 250 MHz data transferred at 500 MHz • Two input clocks K and K for precise DDR timing SRAM uses rising edges only • Echo clocks CQ and CQ simplify data capture in high speed systems • Single multiplexed address input bus latches address inputs for read and write ports • Separate port selects for depth expansion • Synchronous internally self-timed writes • II+ operates with cycle read latency when the delay lock loop DLL is enabled • Available in x 18, and x 36 configurations • Full data coherency, providing most current data • Core VDD = ± V I/O VDDQ = V to VDD • Available in 165-ball CCGA 21 x 25 x mm • HSTL inputs and variable drive HSTL output buffers • JTAG compatible test access port • DLL for accurate data placement Configurations CYRS1543AV18 4 M x 18 CYRS1545AV18 2 M x 36 Functional Description The CYRS1543AV18 and CYRS1545AV18 are synchronous pipelined SRAMs, equipped with V QDR II+ architecture with RadStop technology. Cypress’s state-of-the-art RadStop Technology is radiation hardened through proprietary design and process hardening techniques. The QDR II+ architecture consists of two separate ports the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to turnaround the data bus that exists with common I/O devices. Each port can be accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input K clock. Accesses to the QDR II+ read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with four 18-bit words CYRS1543AV18 or 36-bit words CYRS1545AV18 that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks K and K , memory bandwidth is maximized while simplifying system design by eliminating bus turnarounds. Depth expansion is accomplished with port selects, which enables each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. For a complete list of related resources, click here. Selection Guide Maximum operating frequency Maximum operating current 125 °C, concurrent R/W x 18 x 36 250 MHz 250 1275 Unit MHz mA Power Up Sequence 21 DLL Constraints 21 Maximum Ratings 22 Operating Range 22 Electrical Characteristics 22 DC Electrical Characteristics 22 AC Electrical Characteristics 23 Radiation Performance 23 Capacitance 23 Thermal Resistance 23 AC Test Loads and Waveforms 24 Switching Characteristics 25 Switching Waveforms 26 Ordering Information 27 Ordering Code Definitions 27 Package Diagram 28 Acronyms 29 Document Conventions 29 Units of Measure 29 Glossary 30 Document History Page 31 Sales, Solutions, and Legal Information 34 Worldwide Sales and Design Support 34 Products 34 Solutions 34 Cypress Developer Community 34 Technical Support 34 Page 3 of 34 CYRS1543AV18 CYRS1545AV18 Manufacturing Flow Step Screen 1 Wafer lot acceptance test 2 Internal visual 3 Serialization 4 Temperature cycling 5 Constant acceleration 7 Particle impact noise detection PIND 8 Radiographic X-Ray 9 Pre burn in electrical parameters 10 Dynamic burn in 11 Interim Post dynamic burn in electricals 12 Static burn in 13 Interim post static burn in electricals 14 Percentage defective allowable PDA calculation 15 Final electrical test a. Static tests 1 25 °C 2 °C and +125 °C b. Functional tests 1 25 C 2 °C and +125 °C. Switching test at 25 °C 16 Seal fine and gross leak test 17 External visual 18 Wafer lot specific life test Group C TM 5007 2010, Condition A Method 1010, Condition C, 50 cycles minimum 2001, YI orientation only Condition TBD package in design 2020 Condition A 2012, one view Y-1 orientation only In accordance with applicable Cypress specification 1015, Condition D 240 hours at 125 °C or 120 hours at 150 °C minimum In accordance with applicable Cypress device specifications 1015, Condition C, 72 hours at 150 °C or 144 hours at 125 °C minimum In accordance with applicable Cypress device specifications 5% overall, 3% functional parameters at 25 °C Requirement 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% All lots In accordance with applicable Cypress device specifications 100% 5005, Table I, Subgroup 1 5005, Table I, Subgroup 2, 3 5005, Table I, Subgroup 7 5005, Table I, Subgroup 8a, 8b 5005, Table I, Subgroup 9 1014 2009 Mil-PRF 38535, Appendix B, section B.4.2.c 100% 100% All wafer lots Radiation Hardened Design The single event latch up SEL immunity is improved by a radiation hardened design technique developed by Cypress called RadStop. This design mitigation technique allows the SEL performance to achieve radiation hard performance levels. Neutron Soft Error Immunity Parameter Test Conditions Max* Unit LSBU Ordering Information The following table contains only the parts that are currently available. If you do not see what you are looking for x 18 option , contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at Speed MHz Ordering Code 250 CYRS1543AV18-250GCMB 72M QDR II+, x 18, Burst of 4 250 CYRS1545AV18-250GCMB 72M QDR II+, x 36, Burst of 4 250 CYPT1543AV18-250GCMB 72M QDR II+, x 18, Burst of 4, Prototype 250 CYPT1545AV18-250GCMB 72M QDR II+, x 36, Burst of 4, Prototype 250 5962F1120102QXA 72M QDR II+, x 18, Burst of 4, DLAM Part 250 5962F1120102VXA 72M QDR II+, x 18, Burst of 4, DLAM Part 250 5962F1120202QXA 72M QDR II+, x 36, Burst of 4, DLAM Part 250 5962F1120202VXA 72M QDR II+, x 36, Burst of 4, DLAM Part Package Diagram Package Type Operating Range 001-58969 165-ball CCGA 21 x 25 x mm Military 001-58969 165-ball CCGA 21 x 25 x mm Military 001-58969 165-ball CCGA 21 x 25 x mm Military 001-58969 165-ball CCGA 21 x 25 x mm Military 001-58969 165-ball CCGA 21 x 25 x mm Military 001-58969 165-ball CCGA 21 x 25 x mm Military 001-58969 165-ball CCGA 21 x 25 x mm Military 001-58969 165-ball CCGA 21 x 25 x mm Military Ordering Code Definitions CY XX 154X A V18 - 250 GC M B Page 27 of 34 CYRS1543AV18 CYRS1545AV18 Package Diagram Figure 165-ball Ceramic Column Grid Array CCGA 21 x 25 mm Package Outline, 001-58969 001-58969 *D Page 28 of 34 Acronyms Acronym byte write select CCGA ceramic column grid array double error detection delay lock loop double data rate DSCC defense supply center columbus EDAC error detection and correction HSTL high speed transceiver logic input/output JTAG Joint Test Action Group least significant bit LSBU logical single-bit upsets LMBU logical multi-bit upsets most significant bit percent defect allowable PIND particle impact noise detection percent defective allowable quad data rate read port select single error correction single event latch up SRAM static random access memory test access port the parameters tCO, tDOH, tCCQO, tCQOH based on device characterization. Updated Ordering Information Removed x 18 option from ordering table . Updated Package Diagram. Changed DLL lockup cycles from 2048 to 10240 throughout document. Updated in new template. 3471321 12/21/2011 HRP Updated Identification Register Definitions Replaced the value of Cypress device ID 28:12 from 11010011011010100 to 11010010101010100 for CYRS1543AV18 and replaced the value of Cypress device ID 28:12 from 11010011011100100 to 11010010101100100 for CYRS1545AV18 . 3524961 02/14/2012 HRP Updated Prototyping under Radiation Performance Added two devices . Updated Selection Guide Removed 200 MHz option . Updated Application Example. Updated Truth Table. Updated Maximum Ratings. Updated Operating Range. Updated Radiation Performance. Updated Capacitance. Updated Thermal Resistance. Updated Switching Characteristics. 3537277 02/29/2012 HRP Updated Radiation Data under Radiation Performance. Updated Ordering Information Added the part numbers CYRS1543AV18-250GCMB, CYPT1543AV18-250GCMB, CYPT1545AV18-250GCMB, 5962F1120203VXA CYRS1543AV18-1XWI . 3617759 05/15/2012 HRP Updated Ordering Information Added part 5962F1120103VXA . Updated Glossary. 3640834 06/08/2012 HRP Updated Radiation Performance Updated Prototyping . Renamed the section Class V Flow as Manufacturing Flow. Updated Glossary. 3857750 01/04/2013 HRP Updated Ordering Information Updated part numbers . Page 31 of 34 CYRS1543AV18 CYRS1545AV18 Document History Page continued Document Title CYRS1543AV18/CYRS1545AV18, 72-Mbit II+ SRAM Four-Word Burst Architecture with RadStop Technology Document Number 001-60007 ECN No. Submission Date Orig. of Change Description of Change 3900846 02/11/2013 HRP Updated Neutron Soft Error Immunity Changed value of Test Conditions of SEL parameter from 85 °C to 125 °C . Updated Pin Definitions Changed Pin Name from A to A[x:0] . Updated Functional Overview Updated Qualification and Screening Replaced Class V with Class Q . Updated Application Example Replaced four with two . 3934155 03/15/2013 MISA Updated Selection Guide: Changed Maximum operating current 125 °C, concurrent R/W corresponding to “x 18” for 250 MHz frequency from 1225 mA to 1275 mA. Changed Maximum operating current 125 °C, concurrent R/W corresponding to “x 36” for 250 MHz frequency from 1225 mA to 1275 mA. Updated Electrical Characteristics Updated DC Electrical Characteristics Changed maximum value of IDD parameter corresponding to “x 18” for 250 MHz frequency from 1225 mA to 1275 mA. Changed maximum value of IDD parameter corresponding to “x 36” for 250 MHz frequency from 1225 mA to 1275 mA. Changed maximum value of ISB1 parameter corresponding to “x 18” for 250 MHz frequency from 510 mA to 570 mA. Changed maximum value of ISB1 parameter corresponding to “x 36” for 250 MHz frequency from 510 mA to 570 mA. Removed 200 MHz frequency related information. Updated Switching Characteristics Changed maximum value of tCO and tCHQV parameters from ns to ns. Changed minimum value of tDOH and tCHQX parameters from ns to ns. Changed maximum value of tCCQO and tCHCQV parameters from ns to ns. Changed minimum value of tCQOH and tCHCQX parameters from ns to ns. Removed 200 MHz frequency related information. 4286754 02/21/2014 MISA Updated Functional Overview: Updated Qualification and Screening: Replaced “Class Q” with “Class Q, Class V”. Updated Ordering Information Updated part numbers . Updated to new template. Page 32 of 34 CYRS1543AV18 CYRS1545AV18 Document History Page continued Document Title CYRS1543AV18/CYRS1545AV18, 72-Mbit II+ SRAM Four-Word Burst Architecture with RadStop Technology Document Number 001-60007 ECN No. Submission Date Orig. of Change Description of Change 4618500 01/09/2015 PRIT Updated Radiation Performance: Updated Radiation Data Updated 2nd bulleted point. Updated Functional Description: Added “For a complete list of related resources, click here.” at the end. Updated Pin Definitions: Updated description of CQ and CQ pins. Updated Functional Overview: Updated description. Updated Read Operations: Updated description. Updated Write Operations: Updated description. Updated Application Example: Updated Figure Page 33 of 34 CYRS1543AV18 CYRS1545AV18 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Solutions Automotive cypress.com/go/automotive psoc.cypress.com/solutions Clocks & Buffers cypress.com/go/clocks PSoC 1 \| PSoC 3 \| PSoC 4 \| PSoC 5LP Interface Lighting & Power Control Memory PSoC cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory

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CYRS1543AV18 CYRS1545AV18
72-Mbit II+ SRAM Four-Word Burst Architecture with RadStop Technology
72-Mbit II+ SRAM Four-Word Burst Architecture with RadStop Technology

Radiation Performance

Radiation Data
• Total Dose =300 Krad
• Soft error rate both Heavy Ion and proton Heavy ions 1 x 10-10 upsets/bit-day with an external SECDED EDAC Controller
• Neutrons = x 1014 N/cm2
• Dose rate = x 109 rad Si /sec
• Dose rate survivability rad Si /sec = x rad Si /sec
• Latch up immunity = 120 MeV.cm2/mg 125 °C

Prototyping
• Non-qualified CYPT1543AV18, and CYPT1545AV18 devices with same functional and timing characteristics in a 165-ball Ceramic Column Grid Array CCGA package
• Separate independent read and write data ports Supports concurrent transactions
• 250 MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double data rate DDR interfaces on both read and write ports at 250 MHz data transferred at 500 MHz
• Two input clocks K and K for precise DDR timing SRAM uses rising edges only
• Echo clocks CQ and CQ simplify data capture in high speed systems
• Single multiplexed address input bus latches address inputs for read and write ports
• Separate port selects for depth expansion
• Synchronous internally self-timed writes
• II+ operates with cycle read latency when the delay
lock loop DLL is enabled
• Available in x 18, and x 36 configurations
• Full data coherency, providing most current data
• Core VDD = ± V I/O VDDQ = V to VDD
• Available in 165-ball CCGA 21 x 25 x mm
• HSTL inputs and variable drive HSTL output buffers
• JTAG compatible test access port
• DLL for accurate data placement

Configurations

CYRS1543AV18 4 M x 18

CYRS1545AV18 2 M x 36

Functional Description

The CYRS1543AV18 and CYRS1545AV18 are synchronous pipelined SRAMs, equipped with V QDR II+ architecture with RadStop technology. Cypress’s state-of-the-art RadStop Technology is radiation hardened through proprietary design and process hardening techniques.

The QDR II+ architecture consists of two separate ports the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to turnaround the data bus that exists with common I/O devices. Each port can be accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input K clock. Accesses to the QDR II+ read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with four 18-bit words CYRS1543AV18 or 36-bit words CYRS1545AV18 that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks K and K , memory bandwidth is maximized while simplifying system design by eliminating bus turnarounds.

Depth expansion is accomplished with port selects, which enables each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

For a complete list of related resources, click here.

Selection Guide

Maximum operating frequency

Maximum operating current 125 °C, concurrent R/W
x 18 x 36
250 MHz 250 1275

Unit MHz mA
Power Up Sequence 21 DLL Constraints 21 Maximum Ratings 22 Operating Range 22 Electrical Characteristics 22 DC Electrical Characteristics 22 AC Electrical Characteristics 23 Radiation Performance 23 Capacitance 23 Thermal Resistance 23 AC Test Loads and Waveforms 24 Switching Characteristics 25 Switching Waveforms 26 Ordering Information 27 Ordering Code Definitions 27 Package Diagram 28 Acronyms 29 Document Conventions 29 Units of Measure 29 Glossary 30 Document History Page 31 Sales, Solutions, and Legal Information 34 Worldwide Sales and Design Support 34 Products 34 Solutions 34 Cypress Developer Community 34 Technical Support 34

Page 3 of 34

CYRS1543AV18 CYRS1545AV18

Manufacturing Flow

Step

Screen
1 Wafer lot acceptance test
2 Internal visual
3 Serialization
4 Temperature cycling
5 Constant acceleration
7 Particle impact noise detection PIND
8 Radiographic X-Ray
9 Pre burn in electrical parameters
10 Dynamic burn in
11 Interim Post dynamic burn in electricals 12 Static burn in
13 Interim post static burn in electricals 14 Percentage defective allowable PDA
calculation 15 Final electrical test
a. Static tests 1 25 °C 2 °C and +125 °C b. Functional tests 1 25 C 2 °C and +125 °C. Switching test at 25 °C 16 Seal fine and gross leak test 17 External visual 18 Wafer lot specific life test Group C

TM 5007 2010, Condition A

Method
1010, Condition C, 50 cycles minimum 2001, YI orientation only Condition TBD package in design 2020 Condition A 2012, one view Y-1 orientation only In accordance with applicable Cypress specification 1015, Condition D 240 hours at 125 °C or 120 hours at 150 °C minimum In accordance with applicable Cypress device specifications 1015, Condition C, 72 hours at 150 °C or 144 hours at 125 °C minimum In accordance with applicable Cypress device specifications 5% overall, 3% functional parameters at 25 °C

Requirement
100% 100% 100% 100%
100%
100% 100%
100% 100%
100% All lots

In accordance with applicable Cypress device specifications
100%
5005, Table I, Subgroup 1 5005, Table I, Subgroup 2, 3
5005, Table I, Subgroup 7 5005, Table I, Subgroup 8a, 8b 5005, Table I, Subgroup 9 1014 2009 Mil-PRF 38535, Appendix B, section B.4.2.c
100% 100% All wafer lots

Radiation Hardened Design

The single event latch up SEL immunity is improved by a radiation hardened design technique developed by Cypress called RadStop. This design mitigation technique allows the SEL performance to achieve radiation hard performance levels.

Neutron Soft Error Immunity

Parameter

Test Conditions

Max*

Unit

LSBU
Ordering Information

The following table contains only the parts that are currently available. If you do not see what you are looking for x 18 option , contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at

Speed MHz
Ordering Code
250 CYRS1543AV18-250GCMB 72M QDR II+, x 18, Burst of 4
250 CYRS1545AV18-250GCMB 72M QDR II+, x 36, Burst of 4
250 CYPT1543AV18-250GCMB 72M QDR II+, x 18, Burst of 4, Prototype
250 CYPT1545AV18-250GCMB 72M QDR II+, x 36, Burst of 4, Prototype
250 5962F1120102QXA
72M QDR II+, x 18, Burst of 4, DLAM Part
250 5962F1120102VXA
72M QDR II+, x 18, Burst of 4, DLAM Part
250 5962F1120202QXA
72M QDR II+, x 36, Burst of 4, DLAM Part
250 5962F1120202VXA
72M QDR II+, x 36, Burst of 4, DLAM Part

Package Diagram

Package Type

Operating Range
001-58969 165-ball CCGA 21 x 25 x mm Military
001-58969 165-ball CCGA 21 x 25 x mm Military
001-58969 165-ball CCGA 21 x 25 x mm Military
001-58969 165-ball CCGA 21 x 25 x mm Military
001-58969 165-ball CCGA 21 x 25 x mm Military
001-58969 165-ball CCGA 21 x 25 x mm Military
001-58969 165-ball CCGA 21 x 25 x mm Military
001-58969 165-ball CCGA 21 x 25 x mm Military
Ordering Code Definitions CY XX 154X A V18 - 250 GC M B

Page 27 of 34

CYRS1543AV18 CYRS1545AV18

Package Diagram

Figure 165-ball Ceramic Column Grid Array CCGA 21 x 25 mm Package Outline, 001-58969
001-58969 *D

Page 28 of 34

Acronyms

Acronym
byte write select

CCGA
ceramic column grid array
double error detection
delay lock loop
double data rate

DSCC
defense supply center columbus

EDAC
error detection and correction

HSTL
high speed transceiver logic
input/output

JTAG

Joint Test Action Group
least significant bit

LSBU
logical single-bit upsets

LMBU
logical multi-bit upsets
most significant bit
percent defect allowable

PIND
particle impact noise detection
percent defective allowable
quad data rate
read port select
single error correction
single event latch up

SRAM
static random access memory
test access port
the parameters tCO, tDOH, tCCQO, tCQOH based on device characterization. Updated Ordering Information Removed x 18 option from ordering table .

Updated Package Diagram.

Changed DLL lockup cycles from 2048 to 10240 throughout document.

Updated in new template.
3471321 12/21/2011

HRP Updated Identification Register Definitions Replaced the value of Cypress
device ID 28:12 from 11010011011010100 to 11010010101010100 for

CYRS1543AV18 and replaced the value of Cypress device ID 28:12 from
11010011011100100 to 11010010101100100 for CYRS1545AV18 .
3524961 02/14/2012 HRP Updated Prototyping under Radiation Performance Added two devices .

Updated Selection Guide Removed 200 MHz option .

Updated Application Example.

Updated Truth Table.

Updated Maximum Ratings.

Updated Operating Range.

Updated Radiation Performance.

Updated Capacitance.

Updated Thermal Resistance.

Updated Switching Characteristics.
3537277 02/29/2012 HRP Updated Radiation Data under Radiation Performance.
Updated Ordering Information Added the part numbers

CYRS1543AV18-250GCMB,

CYPT1543AV18-250GCMB,

CYPT1545AV18-250GCMB,
5962F1120203VXA

CYRS1543AV18-1XWI .
3617759 05/15/2012 HRP Updated Ordering Information Added part 5962F1120103VXA .

Updated Glossary.
3640834 06/08/2012 HRP Updated Radiation Performance Updated Prototyping .

Renamed the section Class V Flow as Manufacturing Flow.

Updated Glossary.
3857750 01/04/2013 HRP Updated Ordering Information Updated part numbers .

Page 31 of 34

CYRS1543AV18 CYRS1545AV18

Document History Page continued

Document Title CYRS1543AV18/CYRS1545AV18, 72-Mbit II+ SRAM Four-Word Burst Architecture with RadStop Technology Document Number 001-60007

ECN No.

Submission Date

Orig. of Change

Description of Change
3900846 02/11/2013

HRP Updated Neutron Soft Error Immunity Changed value of Test Conditions of

SEL parameter from 85 °C to 125 °C .

Updated Pin Definitions Changed Pin Name from A to A[x:0] .

Updated Functional Overview Updated Qualification and Screening Replaced Class V with Class Q .

Updated Application Example Replaced four with two .
3934155 03/15/2013 MISA Updated Selection Guide:

Changed Maximum operating current 125 °C, concurrent R/W corresponding
to “x 18” for 250 MHz frequency from 1225 mA to 1275 mA.

Changed Maximum operating current 125 °C, concurrent R/W corresponding
to “x 36” for 250 MHz frequency from 1225 mA to 1275 mA.

Updated Electrical Characteristics Updated DC Electrical Characteristics Changed maximum value of IDD parameter corresponding to “x 18” for 250 MHz frequency from 1225 mA to 1275 mA. Changed maximum value of IDD parameter corresponding to “x 36” for 250 MHz frequency from 1225 mA to 1275 mA. Changed maximum value of ISB1 parameter corresponding to “x 18” for 250 MHz frequency from 510 mA to 570 mA. Changed maximum value of ISB1 parameter corresponding to “x 36” for 250 MHz frequency from 510 mA to 570 mA. Removed 200 MHz frequency related information.

Updated Switching Characteristics Changed maximum value of tCO and tCHQV parameters from ns to ns. Changed minimum value of tDOH and tCHQX parameters from ns to ns. Changed maximum value of tCCQO and tCHCQV parameters from ns to ns. Changed minimum value of tCQOH and tCHCQX parameters from ns to ns. Removed 200 MHz frequency related information.
4286754 02/21/2014 MISA Updated Functional Overview:

Updated Qualification and Screening:

Replaced “Class Q” with “Class Q, Class V”.
Updated Ordering Information Updated part numbers .

Updated to new template.

Page 32 of 34

CYRS1543AV18 CYRS1545AV18

Document History Page continued

Document Title CYRS1543AV18/CYRS1545AV18, 72-Mbit II+ SRAM Four-Word Burst Architecture with RadStop Technology Document Number 001-60007

ECN No.

Submission Date

Orig. of Change

Description of Change
4618500 01/09/2015 PRIT Updated Radiation Performance:

Updated Radiation Data Updated 2nd bulleted point.

Updated Functional Description:

Added “For a complete list of related resources, click here.” at the end.

Updated Pin Definitions:

Updated description of CQ and CQ pins.

Updated Functional Overview:

Updated description.

Updated Read Operations:

Updated description.

Updated Write Operations:

Updated description.

Updated Application Example:

Updated Figure

Page 33 of 34

CYRS1543AV18 CYRS1545AV18

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products

Solutions

Automotive
cypress.com/go/automotive
psoc.cypress.com/solutions

Clocks & Buffers
cypress.com/go/clocks

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Interface Lighting & Power Control

Memory PSoC
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 5962F1120102QXA Datasheet file may be downloaded here without warranties.

Datasheet ID: 5962F1120102QXA 508229