CYP15G0401TB-BGI

CYP15G0401TB-BGI Datasheet

CYP15G0401TB

Part	Datasheet
CYP15G0401TB-BGI	CYP15G0401TB-BGI (pdf)

Related Parts	Information
CYP15G0401TB-BGXC	CYP15G0401TB-BGXC
CYP15G0401TB-BGC	CYP15G0401TB-BGC

PDF Datasheet Preview
CYP15G0401TB Quad HOTLink II Transmitter • Quad transmitter for 195 to 1500 MBaud serial signaling rate Aggregate throughput of 6 GBits/second • Second-generation technology • Compliant to multiple standards ESCON, DVB-ASI, Fibre Channel and Gigabit Ethernet IEEE802.3z 8B/10B encoded or 10-bit unencoded data • Selectable parity check • Selectable input clocking options • Synchronous LVTTL parallel interface • Optional Phase Align Buffer in Transmit Path • Internal phase-locked loop PLL with no external PLL components • Dual differential PECL-compatible serial outputs per channel Source matched for transmission lines No external bias resistors required Signaling-rate controlled edge-rates • Compatible with fiber-optic modules copper cables circuit board traces • JTAG boundary scan • Built-In Self-Test BIST for at-speed link testing • Low power 1.9W 3.3V typical • Single 3.3V supply • 256-ball thermally enhanced BGA • Pb free package option available • BiCMOS technology Functional Description The CYP15G0401TB Quad HOTLink II Transmitter is a point-to-point or point-to-multipoint communications building block allowing the transfer of data over high-speed serial links optical fiber, balanced, and unbalanced copper transmission lines at signaling speeds ranging from 195-to-1500 MBaud per serial link. Each transmitter accepts parallel characters in an Input Register, encodes each character for transport, and converts it to serial data. Figure 1 illustrates typical connections between independent host systems and corresponding CYP15G0401TB and CYP15G0401RB parts. As a second-generation HOTLink device, the CYP15G0401TB extends the HOTLink family with enhanced levels of integration and faster data rates, while maintaining serial-link compatibility data, command, and BIST with other HOTLink devices. The transmitters TX of the CYP15G0401TB Quad HOTLink II consist of four byte-wide channels. Each channel can accept either eight-bit data characters or pre-encoded 10-bit transmission characters. Data characters are passed from the Transmit Input Register to an embedded 8B/10B Encoder to improve their serial transmission characteristics. These encoded characters are then serialized and output from dual Positive ECL PECL -compatible differential transmission-line drivers at a bit-rate of either 10- or 20-times the input reference clock. The integrated 8B/10B Encoder may be bypassed for systems that present externally encoded or scrambled data at the parallel interface. System Host CYP15G0401TB CYP15G0401RB System Host Serial Link Serial Link Serial Link Serial Link Backplane or Cabled Connections Figure HOTLink II System Connections Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 [+] Feedback CYP15G0401TB The parallel input interface may be configured for numerous forms of clocking to provide the highest flexibility in system architecture. Each transmitter contains an independent BIST pattern generator. This BIST hardware allows at-speed testing of the high-speed serial data paths in each transmit section, and across the interconnecting links. HOTLink II devices are ideal for a variety of applications where parallel interfaces can be replaced with high-speed, point-to-point serial links. Some applications include interconnecting backplanes on switches, routers, servers and video transmission systems. CYP15G0401TB Transmitter Logic Block Diagram TXDA[7:0] TXCTA[1:0] TXDB[7:0] TXCTB[1:0] TXDC[7:0] TXCTC[1:0] TXDD[7:0] TXCTD[1:0] Phase Align Buffer Encoder 8B/10B Phase Align Buffer Encoder 8B/10B Phase Align Buffer Encoder 8B/10B The following information describes how the tables are used for both generating valid Transmission Characters encoding and checking the validity of received Transmission Characters decoding . It also specifies the ordering rules to be followed when transmitting the bits within a character and the characters within any higher-level constructs specified by a standard. Transmission Order Within the definition of the 8B/10B Transmission Code, the bit positions of the Transmission Characters are labeled a, b, c, d, e, i, f, g, h, j. Bit “a” is transmitted first followed by bits b, c, d, e, i, f, g, h, and j in that order. Note that bit i is transmitted between bit e and bit f, rather than in alphabetical order. Valid and Invalid Transmission Characters The following tables define the valid Data Characters and valid Special Characters K characters , respectively. The tables are used for both generating valid Transmission Characters and checking the validity of received Transmission Characters. In the tables, each Valid-Data-byte or Special-Character-code entry has two columns that represent two Transmission Characters. The two columns correspond to the current value of the running disparity. Running disparity is a binary parameter with either a negative or positive + value. After powering on, the Transmitter may assume either a positive or negative value for its initial running disparity. Upon transmission of any Transmission Character, the transmitter will select the proper version of the Transmission Character based on the current running disparity value, and the Trans- Page 22 of 30 [+] Feedback CYP15G0401TB mitter calculates a new value for its running disparity based on the contents of the transmitted character. Special Character codes C1.7 and C2.7 can be used to force the transmission of a specific Special Character with a specific running disparity as required for some special sequences in X3.230. After powering on, the Receiver may assume either a positive or negative value for its initial running disparity. Upon reception of any Transmission Character, the Receiver decides whether the Transmission Character is valid or invalid according to the following rules and tables and calculates a new value for its Running Disparity based on the contents of the received character. The following rules for running disparity are used to calculate the new running-disparity value for Transmission Characters that have been transmitted and received. Running disparity for a Transmission Character is calculated from sub-blocks, where the first six bits abcdei form one sub-block and the second four bits fghj form the other sub-block. Running disparity at the beginning of the six-bit sub-block is the running disparity at the end of the previous Transmission Character. Running disparity at the beginning of the four-bit sub-block is the running disparity at the end of the six-bit sub-block. Running disparity at the end of the Transmission Character is the running disparity at the end of the four-bit sub-block. Running disparity for the sub-blocks is calculated as follows: Running disparity at the end of any sub-block is positive if the sub-block contains more ones than zeros. It is also positive at the end of the six-bit sub-block if the six-bit sub-block is 000111, and it is positive at the end of the four-bit sub-block if the four-bit sub-block is Running disparity at the end of any sub-block is negative if the sub-block contains more zeros than ones. It is also negative at the end of the six-bit sub-block if the six-bit sub-block is 111000, and it is negative at the end of the six-bit sub-block if the four-bit sub-block is Otherwise, running disparity at the end of the sub-block is the same as at the beginning of the sub-block. Use of the Tables for Generating Transmission Characters The appropriate entry in Table 13 for the Valid Data byte or Table 14 for Special Character byte identify which Transmission Character is to be generated. The current value of the Transmitter’s running disparity is used to select the Transmission Character from its corresponding column. For each Transmission Character transmitted, a new value of the running disparity is calculated. This new value is used as the Transmitter’s current running disparity for the next Valid Data byte or Special Character byte to be encoded and transmitted. Table 11shows naming notations and examples of valid transmission characters. Use of the Tables for Checking the Validity of Received Transmission Characters The column corresponding to the current value of the Receiver’s running disparity is searched for the received Transmission Character. If the received Transmission Character is found in the proper column, then the Transmission Character is valid and the associated Data byte or Special Character code is determined decoded . If the received Transmission Character is not found in that column, then the Transmission Character is invalid. This is called a code violation. Independent of the Transmission Character’s validity, the received Transmission Character is used to calculate a new value of running disparity. The new value is used as the Receiver’s current running disparity for the next received Transmission Character. Table 11.Valid Transmission Characters Byte Name Data DIN or QOUT 765 43210 Hex Value D0.0 D1.0 000 00001 D2.0 000 00010 D5.2 010 00101 D30.7 111 11110 D31.7 Detection of a code violation does not necessarily show that the Transmission Character in which the code violation was detected is in error. Code violations may result from a prior error that altered the running disparity of the bit stream which did not result in a detectable error at the Transmission Character in which the error occurred. Table 11 shows an example of this behavior. Table 12.Code Violations Resulting from Prior Errors Character Character Ordering Information Speed Standard Standard Ordering Code CYP15G0401TB-BGC CYP15G0401TB-BGI CYP15G0401TB-BGXC CYP15G0401TB-BGXI Package Name Package Type Operating Range BL256 256-ball Thermally Enhanced Ball Grid Array Commercial BL256 256-ball Thermally Enhanced Ball Grid Array Industrial BL256 Pb Free 256-ball Thermally Enhanced Ball Grid Commercial Array BL256 Pb Free 256-ball Thermally Enhanced Ball Grid Industrial Array Package Diagram 256-Lead L2 Ball Grid Array 27 x 27 x mm BL256 A1 CORNER I.D. TOP VIEW REF. 0.20 4X A BOTTOM VIEW BALL SIDE Ø0.75±0.15 256X 20 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 7 5 3 1 R Max 4X L M N P R MIN. A1 CORNER I.D. SIDE VIEW 26° TYP. SEATING PLANE MIN TOP OF MOLD COMPOUND TO TOP OF BALLS 51-85123-*E HOTLink is a registered trademark, and HOTLink II, and MultiFrame are trademarks, of Cypress Semiconductor. IBM and ESCON are registered trademarks, and FICON is a trademark, of International Business Machines. All product and company names mentioned in this document are the trademarks of their respective holders. Page 29 of 30 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CYP15G0401TB

PDF Datasheet Preview

CYP15G0401TB

Quad HOTLink II Transmitter
• Quad transmitter for 195 to 1500 MBaud serial signaling rate Aggregate throughput of 6 GBits/second
• Second-generation technology
• Compliant to multiple standards

ESCON, DVB-ASI, Fibre Channel and Gigabit Ethernet IEEE802.3z
8B/10B encoded or 10-bit unencoded data
• Selectable parity check
• Selectable input clocking options
• Synchronous LVTTL parallel interface
• Optional Phase Align Buffer in Transmit Path
• Internal phase-locked loop PLL with no external PLL
components
• Dual differential PECL-compatible serial outputs per
channel Source matched for transmission lines No external bias resistors required Signaling-rate controlled edge-rates
• Compatible with fiber-optic modules copper cables circuit board traces
• JTAG boundary scan
• Built-In Self-Test BIST for at-speed link testing
• Low power 1.9W 3.3V typical
• Single 3.3V supply
• 256-ball thermally enhanced BGA
• Pb free package option available
• BiCMOS technology

Functional Description

The CYP15G0401TB Quad HOTLink II Transmitter is a point-to-point or point-to-multipoint communications building block allowing the transfer of data over high-speed serial links optical fiber, balanced, and unbalanced copper transmission lines at signaling speeds ranging from 195-to-1500 MBaud per serial link.

Each transmitter accepts parallel characters in an Input Register, encodes each character for transport, and converts it to serial data. Figure 1 illustrates typical connections between independent host systems and corresponding CYP15G0401TB and CYP15G0401RB parts.

As a second-generation HOTLink device, the CYP15G0401TB extends the HOTLink family with enhanced levels of integration and faster data rates, while maintaining serial-link compatibility data, command, and BIST with other HOTLink devices. The transmitters TX of the CYP15G0401TB Quad HOTLink II consist of four byte-wide channels. Each channel can accept either eight-bit data characters or pre-encoded 10-bit transmission characters. Data characters are passed from the Transmit Input Register to an embedded 8B/10B Encoder to improve their serial transmission characteristics. These encoded characters are then serialized and output from dual Positive ECL PECL -compatible differential transmission-line drivers at a bit-rate of either 10- or 20-times the input reference clock. The integrated 8B/10B Encoder may be bypassed for systems that present externally encoded or scrambled data at the parallel interface.

System Host

CYP15G0401TB CYP15G0401RB

System Host

Serial Link

Serial Link

Serial Link

Serial Link

Backplane or

Cabled

Connections

Figure HOTLink II System Connections

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose, CA 95134
• 408-943-2600
[+] Feedback

CYP15G0401TB

The parallel input interface may be configured for numerous forms of clocking to provide the highest flexibility in system architecture.

Each transmitter contains an independent BIST pattern generator. This BIST hardware allows at-speed testing of the high-speed serial data paths in each transmit section, and across the interconnecting links.

HOTLink II devices are ideal for a variety of applications where parallel interfaces can be replaced with high-speed, point-to-point serial links. Some applications include interconnecting backplanes on switches, routers, servers and video transmission systems.

CYP15G0401TB Transmitter Logic Block Diagram

TXDA[7:0] TXCTA[1:0] TXDB[7:0] TXCTB[1:0] TXDC[7:0] TXCTC[1:0] TXDD[7:0] TXCTD[1:0]

Phase Align Buffer

Encoder 8B/10B

Phase Align Buffer

Encoder 8B/10B

Phase Align Buffer

Encoder 8B/10B
The following information describes how the tables are used for both generating valid Transmission Characters encoding and checking the validity of received Transmission Characters decoding . It also specifies the ordering rules to be followed when transmitting the bits within a character and the characters within any higher-level constructs specified by a standard.

Transmission Order

Within the definition of the 8B/10B Transmission Code, the bit positions of the Transmission Characters are labeled a, b, c, d, e, i, f, g, h, j. Bit “a” is transmitted first followed by bits b, c, d, e, i, f, g, h, and j in that order.

Note that bit i is transmitted between bit e and bit f, rather than in alphabetical order.

Valid and Invalid Transmission Characters

The following tables define the valid Data Characters and valid Special Characters K characters , respectively. The tables are used for both generating valid Transmission Characters and checking the validity of received Transmission Characters. In the tables, each Valid-Data-byte or Special-Character-code entry has two columns that represent two Transmission Characters. The two columns correspond to the current value of the running disparity. Running disparity is a binary parameter with either a negative or positive + value.

After powering on, the Transmitter may assume either a positive or negative value for its initial running disparity. Upon transmission of any Transmission Character, the transmitter will select the proper version of the Transmission Character based on the current running disparity value, and the Trans-

Page 22 of 30
[+] Feedback

CYP15G0401TB
mitter calculates a new value for its running disparity based on the contents of the transmitted character. Special Character codes C1.7 and C2.7 can be used to force the transmission of a specific Special Character with a specific running disparity as required for some special sequences in X3.230.

After powering on, the Receiver may assume either a positive or negative value for its initial running disparity. Upon reception of any Transmission Character, the Receiver decides whether the Transmission Character is valid or invalid according to the following rules and tables and calculates a new value for its Running Disparity based on the contents of the received character.

The following rules for running disparity are used to calculate the new running-disparity value for Transmission Characters that have been transmitted and received.

Running disparity for a Transmission Character is calculated from sub-blocks, where the first six bits abcdei form one sub-block and the second four bits fghj form the other sub-block. Running disparity at the beginning of the six-bit sub-block is the running disparity at the end of the previous Transmission Character. Running disparity at the beginning of the four-bit sub-block is the running disparity at the end of the six-bit sub-block. Running disparity at the end of the Transmission Character is the running disparity at the end of the four-bit sub-block.

Running disparity for the sub-blocks is calculated as follows:

Running disparity at the end of any sub-block is positive if the sub-block contains more ones than zeros. It is also positive at the end of the six-bit sub-block if the six-bit sub-block is 000111, and it is positive at the end of the four-bit sub-block if the four-bit sub-block is

Running disparity at the end of any sub-block is negative if the sub-block contains more zeros than ones. It is also negative at the end of the six-bit sub-block if the six-bit sub-block is 111000, and it is negative at the end of the six-bit sub-block if the four-bit sub-block is

Otherwise, running disparity at the end of the sub-block is the same as at the beginning of the sub-block.

Use of the Tables for Generating Transmission Characters

The appropriate entry in Table 13 for the Valid Data byte or Table 14 for Special Character byte identify which Transmission Character is to be generated. The current value of the Transmitter’s running disparity is used to select the Transmission Character from its corresponding column. For each Transmission Character transmitted, a new value of the running disparity is calculated. This new value is used as the Transmitter’s current running disparity for the next Valid Data
byte or Special Character byte to be encoded and transmitted. Table 11shows naming notations and examples of valid transmission characters.

Use of the Tables for Checking the Validity of Received Transmission Characters

The column corresponding to the current value of the Receiver’s running disparity is searched for the received Transmission Character. If the received Transmission Character is found in the proper column, then the Transmission Character is valid and the associated Data byte or Special Character code is determined decoded . If the received Transmission Character is not found in that column, then the Transmission Character is invalid. This is called a code violation. Independent of the Transmission Character’s validity, the received Transmission Character is used to calculate a new value of running disparity. The new value is used as the Receiver’s current running disparity for the next received Transmission Character.

Table 11.Valid Transmission Characters

Byte Name

Data DIN or QOUT 765 43210

Hex Value

D0.0

D1.0
000 00001

D2.0
000 00010

D5.2
010 00101

D30.7
111 11110

D31.7

Detection of a code violation does not necessarily show that the Transmission Character in which the code violation was detected is in error. Code violations may result from a prior error that altered the running disparity of the bit stream which did not result in a detectable error at the Transmission Character in which the error occurred. Table 11 shows an example of this behavior.

Table 12.Code Violations Resulting from Prior Errors

Character

Character
Ordering Information

Speed Standard

Standard
Ordering Code CYP15G0401TB-BGC CYP15G0401TB-BGI CYP15G0401TB-BGXC

CYP15G0401TB-BGXI

Package Name

Package Type

Operating Range

BL256
256-ball Thermally Enhanced Ball Grid Array Commercial

BL256
256-ball Thermally Enhanced Ball Grid Array Industrial

BL256

Pb Free 256-ball Thermally Enhanced Ball Grid Commercial Array

BL256

Pb Free 256-ball Thermally Enhanced Ball Grid Industrial Array

Package Diagram
256-Lead L2 Ball Grid Array 27 x 27 x mm BL256

A1 CORNER I.D.

TOP VIEW

REF.
0.20 4X A

BOTTOM VIEW BALL SIDE
Ø0.75±0.15 256X
20 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 7 5 3 1

R Max 4X

L M N P R

MIN.

A1 CORNER I.D.

SIDE VIEW
26°

TYP.

SEATING PLANE

MIN TOP OF MOLD COMPOUND TO TOP OF BALLS
51-85123-*E

HOTLink is a registered trademark, and HOTLink II, and MultiFrame are trademarks, of Cypress Semiconductor. IBM and ESCON are registered trademarks, and FICON is a trademark, of International Business Machines. All product and company names mentioned in this document are the trademarks of their respective holders.

Page 29 of 30

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CYP15G0401TB

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CYP15G0401TB-BGI Datasheet file may be downloaded here without warranties.

Datasheet ID: CYP15G0401TB-BGI 508219