CYK512K16SCAU-70BAXI

CYK512K16SCAU-70BAXI Datasheet

CYK512K16SCCA

Part	Datasheet
CYK512K16SCAU-70BAXI	CYK512K16SCAU-70BAXI (pdf)

Related Parts	Information
CYK512K16SCAU-70BAXIT	CYK512K16SCAU-70BAXIT

PDF Datasheet Preview
CYK512K16SCCA 8-Mbit 512K x 16 Pseudo Static RAM • Advanced low-power architecture • High speed 55 ns, 70 ns • Wide voltage range 2.7V to 3.3V • Typical active current 2 mA f = 1 MHz • Typical active current 11 mA f = fMAX • Low standby power • Automatic power-down when deselected Functional Description[1] The CYK512K16SCCA is a high-performance CMOS pseudo static RAM PSRAM organized as 512K words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life MoBL in portable applications such as cellular telephones. The device can be put into standby mode reducing power consumption dramatically when deselected CE1 LOW, CE2 HIGH or both BHE and BLE are HIGH . The input/output pins I/O0 through I/O15 are placed in a high-impedance state when deselected CE1 HIGH, CE2 LOW , OE is deasserted HIGH, or during a write operation Chip Enabled and Write Enable WE LOW . Reading from the device is accomplished by asserting the Chip Enables CE1 LOW and CE2 HIGH and Output Enable OE LOW while forcing the Write Enable WE HIGH. If Byte Low Enable BLE is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable BHE is LOW, then data from memory will appear on I/O8 to I/O15. See the Truth Table for a complete description of read and write modes. Logic Block Diagram A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DATA IN DRIVERS 512K x 16 RAM Array ROW DECODER SENSE AMPS A11 A12 A13 A14 A15 A16 A17 A18 COLUMN DECODER Power -Down Circuit BHE BLE BHE WE OE BLE CE2 CE1 CE2 CE1 Note For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Pin Configuration[2, 3, 4] CYK512K16SCCA 48-Ball FBGA Top View BLE OE A0 A1 A2 CE2 I/O8 BHE A3 A4 CE1 I/O0 I/O9 I/O10 A5 A6 I/O1 I/O2 VSS I/O11 A17 A7 I/O3 VCC VCC I/O12 DNU A16 I/O4 VSS I/O14 I/O13 A14 A15 I/O5 I/O6 I/O15 NC A12 A13 WE I/O7 A18 A8 A9 A10 A11 NC Product Portfolio[5] Power Dissipation Product VCC Range V Min. Typ. Max. Speed ns Operating, ICC mA f = 1 MHz Typ.[5] Max. Ordering Information Speed ns Ordering Code CYK512K16SCCAU-55BAI CYK512K16SCCAU-70BAI CYK512K16SCAU-55BAXI CYK512K16SCAU-70BAXI Note H = Logic HIGH, L = Logic LOW, X = Don’t Care Package Name BA48K Package Type 48-ball Fine Pitch BGA x mm 48-ball Fine Pitch BGA x mm 48-ball Fine Pitch BGA x mm Pb-Free 48-ball Fine Pitch BGA x mm Pb-Free Operating Range Industrial Industrial Page 8 of 10 Package Diagrams 48-Ball 6 mm x 8mm x mm FBGA BA48K TOP VIEW A1 CORNER 1 2 3 456 A B C D E F G H CYK512K16SCCA BOTTOM VIEW M C M C A B Ø0.30±0.05 48X A1 CORNER 6 5 4321 A B C D E F G H SEATING PLANE C B 0.15 4X REFERENCE JEDEC MO-207 51-85150-B 51-85193-A MoBL is a registered trademark, and MoBL3 and More Battery Life are trademarks, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Page 9 of 10 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CYK512K16SCCA Document History Page Document Title CYK512K16SCCA 8-Mbit 512K x 16 Pseudo Static RAM Document # 38-05425 Orig. of ECN NO. Issue Date Change Description of Change 130538 01/27/04 AWK New Data Sheet 216680 See ECN REF Added 55 ns Speed bin Updated from Advance Information to Final Data Sheet. 220121 See ECN REF Changed the tOHA for 70 ns speed grade from 10 ns to 5 ns Changed the ISB2 from 80 µA to 100 µA 230851 See ECN AJU Changed Ordering code from CYK512K16SCCA to CYK512K16SCCAU in ‘Ordering Information’ table Modified MAX limit on DC Input voltage from 3.3V to 3.7V in ‘Maximum Ratings’ section 283389 See ECN REF Changed the tSD write parameter from 25ns to 42ns for both the 55ns and 70ns speed grade. 313999 See ECN RKF Added Pb-Free parts to the Ordering information Page 10 of 10

PDF Datasheet Preview

CYK512K16SCCA
8-Mbit 512K x 16 Pseudo Static RAM
• Advanced low-power architecture
• High speed 55 ns, 70 ns
• Wide voltage range 2.7V to 3.3V
• Typical active current 2 mA f = 1 MHz
• Typical active current 11 mA f = fMAX
• Low standby power
• Automatic power-down when deselected

Functional Description[1]

The CYK512K16SCCA is a high-performance CMOS pseudo static RAM PSRAM organized as 512K words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life MoBL in portable applications such as cellular telephones. The device can be put into standby mode reducing power consumption dramatically when deselected CE1 LOW, CE2 HIGH or both BHE and BLE are HIGH . The input/output pins I/O0 through I/O15 are placed in a high-impedance state when deselected CE1 HIGH, CE2 LOW , OE is deasserted HIGH, or during a write operation Chip Enabled and Write Enable WE LOW . Reading from the device is accomplished by asserting the Chip Enables CE1 LOW and CE2 HIGH and Output Enable OE LOW while forcing the Write Enable WE HIGH. If Byte Low Enable BLE is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable BHE is LOW, then data from memory will appear on I/O8 to I/O15. See the Truth Table for a complete description of read and write modes.

Logic Block Diagram

A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

DATA IN DRIVERS
512K x 16 RAM Array

ROW DECODER SENSE AMPS

A11 A12 A13 A14 A15 A16 A17 A18

COLUMN DECODER

Power -Down

Circuit

BHE BLE

BHE WE

OE BLE

CE2 CE1

CE2 CE1

Note For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose, CA 95134
• 408-943-2600

Pin Configuration[2, 3, 4]

CYK512K16SCCA
48-Ball FBGA

Top View

BLE OE A0 A1 A2 CE2

I/O8 BHE A3 A4 CE1 I/O0

I/O9 I/O10 A5 A6 I/O1 I/O2

VSS I/O11 A17 A7 I/O3 VCC

VCC I/O12 DNU A16 I/O4 VSS

I/O14 I/O13 A14 A15 I/O5 I/O6

I/O15 NC A12 A13 WE I/O7

A18 A8 A9 A10 A11 NC

Product Portfolio[5]

Power Dissipation

Product

VCC Range V

Min. Typ. Max.

Speed ns

Operating, ICC mA
f = 1 MHz Typ.[5] Max.
Ordering Information

Speed ns
Ordering Code

CYK512K16SCCAU-55BAI

CYK512K16SCCAU-70BAI

CYK512K16SCAU-55BAXI

CYK512K16SCAU-70BAXI

Note H = Logic HIGH, L = Logic LOW, X = Don’t Care

Package Name BA48K

Package Type 48-ball Fine Pitch BGA x mm 48-ball Fine Pitch BGA x mm 48-ball Fine Pitch BGA x mm Pb-Free 48-ball Fine Pitch BGA x mm Pb-Free

Operating Range Industrial

Industrial

Page 8 of 10

Package Diagrams
48-Ball 6 mm x 8mm x mm FBGA BA48K

TOP VIEW

A1 CORNER 1 2 3 456

A B C D E F G H

CYK512K16SCCA

BOTTOM VIEW

M C M C A B Ø0.30±0.05 48X

A1 CORNER
6 5 4321

A B C D E F G H

SEATING PLANE C

B 0.15 4X

REFERENCE JEDEC MO-207 51-85150-*B 51-85193-*A

MoBL is a registered trademark, and MoBL3 and More Battery Life are trademarks, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.

Page 9 of 10

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

CYK512K16SCCA

Document History Page

Document Title CYK512K16SCCA 8-Mbit 512K x 16 Pseudo Static RAM Document # 38-05425

Orig. of ECN NO. Issue Date Change

Description of Change
130538 01/27/04 AWK New Data Sheet
216680 See ECN REF Added 55 ns Speed bin

Updated from Advance Information to Final Data Sheet.
220121 See ECN REF Changed the tOHA for 70 ns speed grade from 10 ns to 5 ns

Changed the ISB2 from 80 µA to 100 µA
230851 See ECN AJU Changed Ordering code from CYK512K16SCCA to CYK512K16SCCAU in
‘Ordering Information’ table

Modified MAX limit on DC Input voltage from 3.3V to 3.7V in ‘Maximum

Ratings’ section
283389 See ECN REF Changed the tSD write parameter from 25ns to 42ns for both the 55ns and
70ns speed grade.
313999 See ECN RKF Added Pb-Free parts to the Ordering information

Page 10 of 10

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Datasheet ID: CYK512K16SCAU-70BAXI 508209