CYD18S72V18-250BBXC
CYD18S72V18-250BBXC Datasheet
• FullFlex72 family 36-Mbit 512 K x 72 CYD36S72V18 18-Mbit 256 K x 72 CYD18S72V18 9-Mbit 128 K x 72 CYD09S72V18 4-Mbit 64 K x 72 CYD04S72V18
| Part | Datasheet |
|---|---|
CYD18S72V18-250BBXC |
CYD18S72V18-250BBXC (pdf) |
| Related Parts | Information |
|---|---|
CYD18S72V18-167BGC |
CYD18S72V18-167BGC |
CYD09S72V18-200BGXI |
CYD09S72V18-200BGXI |
CYD09S72V18-250BBXC |
CYD09S72V18-250BBXC |
CYD09S18V18-167BBXC |
CYD09S18V18-167BBXC |
CYD09S72V18-167BBXC |
CYD09S72V18-167BBXC |
CYD18S72V18-200BBXI |
CYD18S72V18-200BBXI |
CYD18S72V18-200BBXC |
CYD18S72V18-200BBXC |
CYD18S72V18-167BBXC |
CYD18S72V18-167BBXC |
CYD09S72V18-200BBXI |
CYD09S72V18-200BBXI |
CYD09S72V18-167BBXI |
CYD09S72V18-167BBXI |
CYD18S72V18-167BBXI |
CYD18S72V18-167BBXI |
CYD09S72V18-200BBXC |
CYD09S72V18-200BBXC |
CYD18S72V18-167BGXC |
CYD18S72V18-167BGXC |
| PDF Datasheet Preview |
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| FullFlex FullFlexTM Synchronous SDR Dual Port SRAM FullFlex Synchronous SDR Dual Port SRAM • True dual port memory enables simultaneous access to the shared array from each port • Synchronous pipelined operation with single data rate SDR operation on each port SDR interface at 200 MHz Up to Gb/s bandwidth 200 MHz x 72-bit x 2 ports • Selectable pipelined or flow-through mode • V or V core power supply • Commercial and Industrial temperature • IEEE JTAG boundary scan • Available in 484-ball PBGA x 72 and 256-ball FBGA x 36 and x 18 packages • FullFlex72 family 36-Mbit 512 K x 72 CYD36S72V18 18-Mbit 256 K x 72 CYD18S72V18 9-Mbit 128 K x 72 CYD09S72V18 4-Mbit 64 K x 72 CYD04S72V18 • FullFlex36 family 36-Mbit 1 M x 36 CYD36S36V18 18-Mbit 512 K x 36 CYD18S36V18 9-Mbit 256 K x 36 CYD09S36V18 4-Mbit 128 K x 36 CYD04S36V18 2-Mbit 64 K x 36 CYD02S36V18 • FullFlex18 family 36-Mbit 2 M x 18 CYD36S18V18 18-Mbit 1 M x 18 CYD18S18V18 9-Mbit 512 K x 18 CYD09S18V18 4-Mbit 256 K x 18 CYD04S18V18 • Built in deterministic access control to manage address collisions Deterministic flag output upon collision detection Collision detection on back-to-back clock cycles First busy address readback • Advanced features for improved high speed data transfer and flexibility Variable impedance matching VIM Echo clocks Selectable LVTTL V , Extended HSTL V to V , V LVCMOS, or V LVCMOS IO on each port Burst counters for sequential memory access Mailbox with interrupt flags for message passing Dual chip enables for easy depth expansion Functional Description The FullFlex dual port SRAM families consist of 2-Mbit, 4-Mbit, 9-Mbit, 18-Mbit, and 36-Mbit synchronous, true dual port static RAMs that are high speed, low power V or V CMOS. Two ports are provided, enabling simultaneous access to the array. Simultaneous access to a location triggers deterministic access control. For FullFlex72 these ports operate independently with 72-bit bus widths and each port is independently configured for two pipelined stages. Each port is also configured to operate in pipelined or flow through mode. The advanced features include the following • Built in deterministic access control to manage address collisions during simultaneous access to the same memory location • Variable Impedance Matching VIM to improve data transmission by matching the output driver impedance to the line impedance • Echo clocks to improve data transfer To reduce the static power consumption, chip enables power down the internal circuitry. The number of latency cycles before a change in CE0 or CE1 enables or disables the databus matches the number of cycles of read latency selected for the device. For a valid write or read to occur, activate both chip enable inputs on a port. Each port contains an optional burst counter on the input address register. After externally loading the counter with the initial address, the counter increments the address internally. Additional device features include a mask register and a mirror register to control counter increments and wrap around. The counter interrupt CNTINT flags notify the host that the counter reaches maximum count value on the next clock cycle. The host reads the burst counter internal address, mask register address, and busy address on the address lines. The host also loads the counter with the address stored in the mirror register by using the retransmit functionality. Mailbox interrupt flags are used for message passing, and JTAG boundary scan and asynchronous Master Reset MRST are also available. The Logic Block Diagram on page 2 shows these features. The FullFlex72 is offered in a 484-ball plastic BGA package. The FullFlex36 and FullFlex18 are available in 256-ball fine pitch BGA package. • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Logic Block Diagram The Logic Block Diagram for FullFlex72, FullFlex36, and FullFlex18 family follows [1, 2, 3] FTSELL CQENL PORTSTD[1:0]L CONFIG Block CONFIG Block DQ[71:0]L BE [7:0]L CCEE10LL OEL RC/QW1LL CQ1L CQ0L IO Control IO Control Dual Port Array FullFlex FTSELR CQENR PORTSTD[1:0]R DQ [71:0]R BE [7:0]R CCEE01RR OER R/WR CCCQQQ101RRR CQ0R A [20:0]L CNATD/M SLSKL CNTENL CNTRSTL RETL CNTINTL CL WRPL BUSYL Collision Detection Logic BUSYR Electrical Characteristics 24 AC Test Load and Waveforms 25 Switching Characteristics 26 Switching Waveforms 29 Ordering Information 43 Acronyms 48 Document Conventions 48 Document History Page 49 Sales, Solutions, and Legal Information 52 Page 3 of 52 [+] Feedback FullFlex Figure FullFlex72 SDR 484-ball BGA Pinout Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 DNU DQ61L DQ59L DQ57L DQ54L DQ51L DQ48L DQ45L DQ42L DQ39L DQ36L DQ36R DQ39R DQ42R DQ45R DQ48R DQ51R DQ54R DQ57R DQ59R DQ61R DNU B DQ63L DQ62L DQ60L DQ58L DQ55L DQ52L DQ49L DQ46L DQ43L DQ40L DQ37L DQ37R DQ40R DQ43R DQ46R DQ49R DQ52R DQ55R DQ58R DQ60R DQ62R DQ63R C DQ65L DQ64L VSS VSS DQ56L DQ53L DQ50L DQ47L DQ44L DQ41L DQ38L DQ38R DQ41R DQ44R DQ47R DQ50R DQ53R DQ56R VSS VSS DQ64R DQ65R D DQ67L DQ66L VSS E DQ69L DQ68L VDDIOL VSS VSS CQ1L VSS LOWSP PORTST ZQ0L BUSYL CNTINT PORTST DNU CQ1R VSS VDDIOL VTTL VDDIOR DNU VSS DQ66R DQ67R VSS VDDIOR DQ68R DQ69R DQ71L DQ70L CE1L CE0L VDDIOL VCORE VDDIOR CE0R CE1R DQ70R DQ71R A1L RETL BE4L VDDIOL VREFL VSS VSS VREFR VDDIOR BE4R RETR A1R A3L WRPL BE5L VDDIOL VSS VSS VDDIOR BE5R WRPR A3R A5L READYL BE6L VDDIOL VSS VSS VDDIOR BE6R READYR A5R A7L ZQ1L BE7L VTTL VCORE VSS VSS VCORE VDDIOR BE7R ZQ1R A7R [4, 5] [4, 5] OEL VTTL VCORE VSS VSS VCORE VTTL OER A10L A11L VSS BE3L VTTL VCORE VSS VSS VCORE VTTL BE3R VSS A11R A10R A12L A13L ADSL BE2L VDDIOL VCORE VSS VSS VCORE VTTL BE2R ADSR A13R A12R A14L A15L CNT/MS BE1L VDDIOL VSS KL VSS VDDIOR BE1R CNT/MS A15R KR A14R Ordering Information 512 K x 72 36-Mbit V/1.5 V Synchronous CYD36S72V18 Dual Port SRAM Speed MHz Ordering Code Package Diagram Package Type Operating Range 200 CYD36S72V18-200BGXC 001-07825 484-ball Grid Array 27 mm x 27 mm with mm pitch Pb-free Commercial 167 CYD36S72V18-167BGXI 001-07825 484-ball Grid Array 27 mm x 27 mm with mm pitch Pb-free Industrial 167 CYD36S72V18-167BGI 001-07825 484-ball Grid Array 27 mm x 27 mm with mm pitch Industrial 256 K x 72 18-Mbit V/1.5 V Synchronous CYD18S72V18 Dual Port SRAM Speed MHz Ordering Code Package Diagram Package Type Operating Range 200 CYD18S72V18-200BGXI 51-85218 484-ball Grid Array 23 mm x 23 mm with mm pitch Pb-free Industrial 200 CYD18S72V18-200BGI 51-85218 484-ball Grid Array 23 mm x 23 mm with mm pitch Industrial 167 CYD18S72V18-167BGXC 51-85218 484-ball Grid Array 23 mm x 23 mm with mm pitch Pb-free Commercial 167 CYD18S72V18-167BGC 51-85218 484-ball Grid Array 23 mm x 23 mm with mm pitch Commercial 167 CYD18S72V18-167BGI 51-85218 484-ball Grid Array 23 mm x 23 mm with mm pitch Industrial 128 K x 72 9-Mbit V/1.5 V Synchronous CYD09S72V18 Dual Port SRAM Speed MHz Ordering Code Package Diagram Package Type Operating Range 200 CYD09S72V18-200BGXI 51-85218 484-ball Grid Array 23 mm x 23 mm with mm pitch Pb-free Industrial 167 CYD09S72V18-167BBXC 51-85218 484-ball Grid Array 23 mm x 23 mm with mm pitch Pb-free Commercial 1024 K x 36-Mbit V/1.5 V Synchronous CYD36S36V18 Dual Port SRAM Speed MHz Ordering Code Package Diagram Package Type Operating Range 200 CYD36S36V18-200BGXC 001-07825 484-ball Grid Array 27 mm x 27 mm with mm pitch Pb-free Commercial 167 CYD36S36V18-167BGXC 001-07825 484-ball Grid Array 27 mm x 27 mm with mm pitch Pb-free Commercial 167 CYD36S36V18-167BGXI 001-07825 484-ball Grid Array 27 mm x 27 mm with mm pitch Pb-free Industrial 512 K x 36 18-Mbit V/1.5 V Synchronous CYD18S36V18 Dual Port SRAM Speed MHz Ordering Code Package Diagram Package Type Operating Range 200 CYD18S36V18-200BBAXI 51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Pb-free Industrial 167 CYD18S36V18-167BBAI 51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Industrial Page 43 of 52 [+] Feedback FullFlex Ordering Information continued 256 K x 36 9-Mbit V/1.5 V Synchronous CYD09S36V18 Dual Port SRAM Speed MHz Ordering Code Package Diagram Package Type Operating Range 200 CYD09S36V18-200BBXC 51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Pb-free Commercial 200 CYD09S36V18-200BBXI 51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Pb-free Industrial 167 CYD09S36V18-167BBXC 51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Pb-free Commercial 64 K x 36 2-Mbit V or V Synchronous CYD02S36V18 Dual Port SRAM Speed MHz Ordering Code Package Diagram Package Type 200 CYD02S36V18-200BBC 51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Operating Range Commercial Page 44 of 52 [+] Feedback FullFlex Ordering Information continued 2048 K x 18 36-Mbit V/1.5 V Synchronous CYD36S18V18 Dual Port SRAM Speed MHz Ordering Code Package Diagram Package Type Operating Range 200 CYD36S18V18-200BGXC 001-07825 484-ball Grid Array 27 mm x 27 mm with mm pitch Pb-free Commercial 167 CYD36S18V18-167BGXC 001-07825 484-ball Grid Array 27 mm x 27 mm with mm pitch Pb-free Commercial 167 CYD36S18V18-167BGXI 001-07825 484-ball Grid Array 27 mm x 27 mm with mm pitch Pb-free Industrial 1024 K x 18-Mbit V/1.5 V Synchronous CYD18S18V18 Dual Port SRAM Speed MHz Ordering Code Package Diagram Package Type Operating Range 200 CYD18S18V18-200BBAXI 51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Pb-free Industrial 200 CYD18S18V18-200BBAI 51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Industrial 167 CYD18S18V18-167BBAXI 51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Pb-free Industrial 512 K x 18 9-Mbit V/1.5 V Synchronous CYD09S18V18 Dual Port SRAM Speed MHz Ordering Code Package Diagram Package Type Operating Range 200 CYD09S18V18-200BBXC 51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Pb-free Commercial 200 CYD09S18V18-200BBXI 51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Pb-free Industrial 167 CYD09S18V18-167BBXC 51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Pb-free Commercial 167 CYD09S18V18-167BBXI 51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Pb-free Industrial Ordering Code Definitions CY DXX SXX V18 - XXX XXXX X Temperature Range X = C or I C = Commercial I = Industrial Package Type XXXX = BG or BB or BBA or BGX or BBX or BBAX BG, BB, BBA = Ball Grid Array BGX, BBX, BBAX = Ball Grid Array Pb-free Speed Grade XXX = 167 MHz / 200 MHz V18 = V SXX = Data Width DXX = Density in Mb CY = Cypress Page 45 of 52 [+] Feedback Package Diagrams Figure 256-ball FPBGA 17 x 17 mm , 51-85108 FullFlex 51-85108 *H Page 46 of 52 [+] Feedback Package Diagrams Figure 484-ball PBGA 23 mm x 23 mm x mm , 51-85218 FullFlex 51-85218 *A Page 47 of 52 [+] Feedback Package Diagrams Figure 484-ball PBGA 27 mm x 27 mm x mm , 001-07825 FullFlex 001-07825 *A Acronyms Acronym BGA CMOS DLL FPBGA HSTL I/O SDR SRAM TCK TDI TDO TMS VIM Description ball grid array complementary metal oxide semiconductor delay lock loop fine pitch ball gird array high speed transceiver logic input/output single data rate static random access memory test clock test data in test data out test mode select variable impedance matching Document Conventions Units of Measure Symbol ns V µA mA ms mV MHz pF W °C Unit of Measure nano seconds Volts micro Amperes milli Amperes milli seconds milli Volts Mega Hertz pico Farad Watts degree Celcius Page 48 of 52 [+] Feedback FullFlex Document History Page Document Title FullFlex Synchronous SDR Dual Port SRAM Document Number 38-06082 ECN NO. Submission Date Orig. of Change Description of Change 302411 See ECN YDT New data sheet 334036 See ECN YDT Corrected typo on page 1 Reproduced PDF file to fix formatting errors 395800 See ECN SPN Added statement about no echo clocks for flow through mode Updated electrical characteristics Added note 16 and 17 V timing YDT Changed ordering information with Pb-free part numbers Removed VC_SEL Added IO and core voltage adders Removed references to bin drop for LVTTL/2.5 V LVCMOS and V core modes Updated Cin and Cout Updated ICC, ISB1, ISB2 and ISB3 tables Updated busy address read back timing diagram Added HTSL input waveform Removed HSTL AC from DC tables Added 484-ball 27 mmx27 mmx2.33 mm PBGA package 470031 SEE ECN YDT Changed VOL of V LVCMOS to V Updated tRSF VREF is DNU when HSTL is not used Formatted pin description table Changed VDDIO pins for 36M x 36 and 36M x 18 pinouts Changed 36Mx72 JTAG IDCODE 500001 SEE ECN YDT DLL Change, added Clock Input Cycle to Cycle Jitter Modified DLL description Changed Input Capacitance Table Changed tCCS number Added note 31 627539 SEE ECN QSL change all NC to DNU corrected switching waveform for CQEN = High from both Pipeline and Flow through mode to only pipeline mode Modified master reset description Modified switching characteristics tables, extracted signals effected by the DLL into one table and combine all other signals into one table updated package name Added footnote for tHD, tHAC and tSAC changed note 26 description Page 50 of 52 [+] Feedback FullFlex Document History Page Document Title FullFlex Synchronous SDR Dual Port SRAM Document Number 38-06082 ECN NO. Submission Date Orig. of Change Description of Change 2505003 See ECN VKN/ Modified footnote #1 AESA Removed 250 MHz speed bin Added 2-Mbit part and it’s related information Updated Ordering Information table 2898491 07/01/2010 RAME Modified “Counter Load Operation” section on page 12 and in Table7. on page Corrected typo in Table by making LowSPD = 0 for tCD1 spec in the description. Modified figure on page Removed inactive parts from Ordering Information. Updated Packaging Information. Corrected “ Counter Interrupt operation” Section in Page 14 of the datasheet Updated ordering information with the parts, CYD02S36V18-200BBC and CYD36S72V18-167BGI. 2995098 07/28/2010 RAME Updated Ordering Information and added Ordering Code Definitions. Added Acronyms and Units of Measure. Minor edits. Page 51 of 52 [+] Feedback FullFlex Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. 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