CYD04S18V-167BBC

CYD04S18V-167BBC Datasheet

CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V

Part	Datasheet
CYD04S18V-167BBC	CYD04S18V-167BBC (pdf)

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CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V FLEx18 3.3V 64K/128K/256K/512K x 18 Synchronous Dual-Port RAM Functional Description • True dual-ported memory cells that allow simultaneous access of the same memory location • Synchronous pipelined operation • Organization of 1 Mbit, 2 Mbits, 4 Mbits and 9 Mbits devices • Pipelined output mode allows fast operation • 0.18-micron CMOS for optimum speed and power • High-speed clock to data access • 3.3V low power Active as low as 225 mA typ Standby as low as 55 mA typ • Mailbox function for message passing • Global master reset • Separate byte enables on both ports • Commercial and industrial temperature ranges • IEEE 1149.1-compatible JTAG boundary scan • 256-ball FBGA 1 mm pitch • Counter wrap-around control Internal mask register controls counter wrap-around Counter-interrupt flags to indicate wrap-around Memory block retransmit operation • Counter readback on address lines • Mask register readback on address lines • Dual Chip Enables on both ports for easy depth expansion • Seamless migration to next-generation dual-port family The FLEx18 family includes 1-Mbit, 2-Mbit, 4-Mbit and 9-Mbit pipelined, synchronous, true dual-port static RAMs that are high-speed, low-power 3.3V CMOS. Two ports are provided, permitting independent, simultaneous access to any location in memory. The result of writing to the same location by more than one port at the same time is undefined. Registers on control, address, and data lines allow for minimal set-up and hold time. During a Read operation, data is registered for decreased cycle time. Each port contains a burst counter on the input address register. After externally loading the counter with the initial address, the counter will increment the address internally more details to follow . The internal Write pulse width is independent of the duration of the R/W input signal. The internal Write pulse is self-timed to allow the shortest possible cycle times. A HIGH on CE0 or LOW on CE1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. One cycle with chip enables asserted is required to reactivate the outputs. Additional features include readback of burst-counter internal address value on address lines, counter-mask registers to control the counter wrap-around, counter interrupt CNTINT flags, readback of mask register value on address lines, retransmit functionality, interrupt flags for message passing, JTAG for boundary scan, and asynchronous Master Reset MRST . The CYD09S18V device in this family has limited features. Please see Address Counter and Mask Register Operations on page 5 for details. Seamless Migration to Next Generation Dual Port Family Cypress offers a migration path for all devices in this family to the next-generation devices in the Dual-Port family with a compatible footprint. Please contact Cypress Sales for more details. Table Product Selection Guide Density Part Number Max. Speed MHz Max. Access Time Clock to Data ns Typical operating current mA Package 1 Mbit 64K x 18 2 Mbit 128K x 18 4 Mbit 256K x 18 9 Mbit 512K x 18 CYD01S18V CYD02S18V CYD04S18V CYD09S18V 256FBGA 256FBGA 256FBGA 256FBGA 17 mm x 17 mm 17 mm x 17 mm 17 mm x 17 mm 17 mm x 17 mm Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Logic Block Diagram[1] FTSELL PORTSTD 1:0 L DQ 17:0 L BE 1:0 L CE0L CE1L OEL R/WL CONFIG Block IO Control CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V CONFIG Block IO Control FTSELR Ordering Information 512K x 18 9Mb 3.3V Synchronous CYD09S18V Dual-Port SRAM Speed MHz Ordering Code Package Name Package Type Operating Range 133 CYD09S18V-133BBC BB256 256-ball Grid Array 17 mm x 17 mm with mm pitch BGA Commercial 100 CYD09S18V-100BBC BB256 256-ball Grid Array 17 mm x 17 mm with mm pitch BGA Commercial CYD09S18V-100BBI BB256 256-ball Grid Array 17 mm x 17 mm with mm pitch BGA Industrial 256K x 18 4Mb 3.3V Synchronous CYD04S36V Dual-Port SRAM Speed MHz Ordering Code Package Name Package Type Operating Range 167 CYD04S18V-167BBC BB256 256-ball Grid Array 17 mm x 17 mm with mm pitch BGA Commercial 133 CYD04S18V-133BBC BB256 256-ball Grid Array 17 mm x 17 mm with mm pitch BGA Commercial CYD04S18V-133BBI BB256 256-ball Grid Array 17 mm x 17 mm with mm pitch BGA Industrial 128K x 18 2Mb 3.3V Synchronous CYD02S18V Dual-Port SRAM Speed MHz Ordering Code Package Name Package Type Operating Range 167 CYD02S18V-167BBC BB256 256-ball Grid Array 17 mm x 17 mm with mm pitch BGA Commercial 133 CYD02S18V-133BBC BB256 256-ball Grid Array 17 mm x 17 mm with mm pitch BGA Commercial CYD02S18V-133BBI BB256 256-ball Grid Array 17 mm x 17 mm with mm pitch BGA Industrial 64K x 18 1Mb 3.3V Synchronous CYD01S18V Dual-Port SRAM Speed MHz Ordering Code Package Name Package Type Operating Range 167 CYD01S18V-167BBC BB256 256-ball Grid Array 17 mm x 17 mm with mm pitch BGA Commercial 133 CYD01S18V-133BBC BB256 256-ball Grid Array 17 mm x 17 mm with mm pitch BGA Commercial CYD01S18V-133BBI BB256 256-ball Grid Array 17 mm x 17 mm with mm pitch BGA Industrial Page 24 of 26 CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V Package Diagram 256-Ball FBGA 17 x 17 mm BB256 TOP VIEW M C M C A B BOTTOM VIEW PIN 1 CORNER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Ø0.45±0.05 256X -CPLD DEVICES 37K & 39K PIN 1 CORNER +205.160X -ALL OTHER DEVICES 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SEATING PLANE 0.20 4X REFERENCE JEDEC MO-192 A MAX. MAX. 51-85108-*F FLEx18 and FLEx18-E are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. Page 25 of 26 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V Document History Page Document Title CYD01S18V/CYD02S18V/CYD04S18V/CYD09S18V FLEx18 3.3V 64K/128K/256K/512K x 18 Synchronous Dual-Port RAM Document Number 38-06077 Orig. of ECN NO. Issue Date Change Description of Change 259671 See ECN WWZ New data sheet 289711 See ECN YDT Change Pinout D10 from NC to VSS Changed tRSCNTINT to tRSINT Added tRSINT to the master reset timing diagram Added ISB5 and changed IIX2

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CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V

FLEx18 3.3V 64K/128K/256K/512K x 18 Synchronous Dual-Port RAM

Functional Description
• True dual-ported memory cells that allow simultaneous access of the same memory location
• Synchronous pipelined operation
• Organization of 1 Mbit, 2 Mbits, 4 Mbits and 9 Mbits
devices
• Pipelined output mode allows fast operation
• 0.18-micron CMOS for optimum speed and power
• High-speed clock to data access
• 3.3V low power

Active as low as 225 mA typ Standby as low as 55 mA typ
• Mailbox function for message passing
• Global master reset
• Separate byte enables on both ports
• Commercial and industrial temperature ranges
• IEEE 1149.1-compatible JTAG boundary scan
• 256-ball FBGA 1 mm pitch
• Counter wrap-around control Internal mask register controls counter wrap-around Counter-interrupt flags to indicate wrap-around Memory block retransmit operation
• Counter readback on address lines
• Mask register readback on address lines
• Dual Chip Enables on both ports for easy depth expansion
• Seamless migration to next-generation dual-port family

The FLEx18 family includes 1-Mbit, 2-Mbit, 4-Mbit and 9-Mbit pipelined, synchronous, true dual-port static RAMs that are high-speed, low-power 3.3V CMOS. Two ports are provided, permitting independent, simultaneous access to any location in memory. The result of writing to the same location by more than one port at the same time is undefined. Registers on control, address, and data lines allow for minimal set-up and hold time.

During a Read operation, data is registered for decreased cycle time. Each port contains a burst counter on the input address register. After externally loading the counter with the initial address, the counter will increment the address internally more details to follow . The internal Write pulse width is independent of the duration of the R/W input signal. The internal Write pulse is self-timed to allow the shortest possible cycle times.

A HIGH on CE0 or LOW on CE1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. One cycle with chip enables asserted is required to reactivate the outputs.

Additional features include readback of burst-counter internal address value on address lines, counter-mask registers to control the counter wrap-around, counter interrupt CNTINT flags, readback of mask register value on address lines, retransmit functionality, interrupt flags for message passing, JTAG for boundary scan, and asynchronous Master Reset MRST .

The CYD09S18V device in this family has limited features. Please see Address Counter and Mask Register Operations on page 5 for details.

Seamless Migration to Next Generation Dual Port Family

Cypress offers a migration path for all devices in this family to the next-generation devices in the Dual-Port family with a compatible footprint. Please contact Cypress Sales for more details.

Table Product Selection Guide

Density Part Number Max. Speed MHz Max. Access Time Clock to Data ns Typical operating current mA Package
1 Mbit 64K x 18
2 Mbit 128K x 18
4 Mbit 256K x 18
9 Mbit 512K x 18

CYD01S18V

CYD02S18V

CYD04S18V

CYD09S18V
256FBGA
256FBGA
256FBGA
256FBGA
17 mm x 17 mm 17 mm x 17 mm 17 mm x 17 mm 17 mm x 17 mm

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose, CA 95134
• 408-943-2600

Logic Block Diagram[1]

FTSELL

PORTSTD 1:0 L

DQ 17:0 L BE 1:0 L

CE0L CE1L OEL R/WL

CONFIG Block

IO Control

CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V

CONFIG Block

IO Control

FTSELR
Ordering Information
512K x 18 9Mb 3.3V Synchronous CYD09S18V Dual-Port SRAM

Speed MHz
Ordering Code

Package Name

Package Type

Operating Range
133 CYD09S18V-133BBC

BB256 256-ball Grid Array 17 mm x 17 mm with mm pitch BGA Commercial
100 CYD09S18V-100BBC

BB256 256-ball Grid Array 17 mm x 17 mm with mm pitch BGA Commercial

CYD09S18V-100BBI

BB256 256-ball Grid Array 17 mm x 17 mm with mm pitch BGA Industrial
256K x 18 4Mb 3.3V Synchronous CYD04S36V Dual-Port SRAM

Speed MHz
Ordering Code

Package Name

Package Type

Operating Range
167 CYD04S18V-167BBC

BB256 256-ball Grid Array 17 mm x 17 mm with mm pitch BGA Commercial
133 CYD04S18V-133BBC

BB256 256-ball Grid Array 17 mm x 17 mm with mm pitch BGA Commercial

CYD04S18V-133BBI

BB256 256-ball Grid Array 17 mm x 17 mm with mm pitch BGA Industrial
128K x 18 2Mb 3.3V Synchronous CYD02S18V Dual-Port SRAM

Speed MHz
Ordering Code

Package Name

Package Type

Operating Range
167 CYD02S18V-167BBC

BB256 256-ball Grid Array 17 mm x 17 mm with mm pitch BGA Commercial
133 CYD02S18V-133BBC

BB256 256-ball Grid Array 17 mm x 17 mm with mm pitch BGA Commercial

CYD02S18V-133BBI

BB256 256-ball Grid Array 17 mm x 17 mm with mm pitch BGA Industrial
64K x 18 1Mb 3.3V Synchronous CYD01S18V Dual-Port SRAM

Speed MHz
Ordering Code

Package Name

Package Type

Operating Range
167 CYD01S18V-167BBC

BB256 256-ball Grid Array 17 mm x 17 mm with mm pitch BGA Commercial
133 CYD01S18V-133BBC

BB256 256-ball Grid Array 17 mm x 17 mm with mm pitch BGA Commercial

CYD01S18V-133BBI

BB256 256-ball Grid Array 17 mm x 17 mm with mm pitch BGA Industrial

Page 24 of 26

CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V

Package Diagram
256-Ball FBGA 17 x 17 mm BB256

TOP VIEW

M C M C A B

BOTTOM VIEW

PIN 1 CORNER
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Ø0.45±0.05 256X -CPLD DEVICES 37K & 39K

PIN 1 CORNER
+205.160X -ALL OTHER DEVICES
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

SEATING PLANE
0.20 4X

REFERENCE JEDEC MO-192

A MAX. MAX.
51-85108-*F

FLEx18 and FLEx18-E are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.

Page 25 of 26

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V

Document History Page

Document Title CYD01S18V/CYD02S18V/CYD04S18V/CYD09S18V FLEx18 3.3V 64K/128K/256K/512K x 18 Synchronous Dual-Port RAM Document Number 38-06077

Orig. of ECN NO. Issue Date Change

Description of Change
259671 See ECN WWZ New data sheet
289711 See ECN YDT Change Pinout D10 from NC to VSS

Changed tRSCNTINT to tRSINT

Added tRSINT to the master reset timing diagram

Added ISB5 and changed IIX2

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CYD04S18V-167BBC Datasheet file may be downloaded here without warranties.

Datasheet ID: CYD04S18V-167BBC 508192