CY8C3865AXI-056

CY8C3865AXI-056 Datasheet


PRELIMINARY 3 CY8C38 Family Datasheet

Part Datasheet
CY8C3865AXI-056 CY8C3865AXI-056 CY8C3865AXI-056 (pdf)
Related Parts Information
CY8C3866LTI-065 CY8C3866LTI-065 CY8C3866LTI-065
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CY8C3865LTI-062 CY8C3865LTI-062 CY8C3865LTI-062
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PRELIMINARY 3 CY8C38 Family Datasheet

Programmable System-on-Chip

With its unique array of configurable blocks, 3 is a true system level solution providing microcontroller unit MCU , memory, analog, and digital peripheral functions in a single chip. The CY8C38 family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples near DC voltages to ultrasonic signals. The CY8C38 family can handle dozens of data acquisition channels and analog inputs on every general-purpose input/output GPIO pin. The CY8C38 family is also a high-performance configurable digital system with some part numbers including interfaces such as USB, multimaster inter-integrated circuit I2C , and controller area network CAN . In addition to communication interfaces, the CY8C38 family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance single cycle 8051 microprocessor core. You can easily create system-level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator , a hierarchical schematic design entry tool. The CY8C38 family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.
- Single cycle 8051 CPU DC to 67 MHz operation Multiply and divide instructions Flash program memory, up to 64 KB, 100,000 write cycles, 20 years retention, and multiple security features Up to 8-KB flash error correcting code ECC or configuration storage Up to 8 KB SRAM Up to 2 KB electrically erasable programmable read-only memory EEPROM , 1 M cycles, and 20 years retention 24-channel direct memory access DMA with multilayer AHB[1] bus access
• Programmable chained descriptors and priorities
• High bandwidth 32-bit transfer support
- Low voltage, ultra low-power Wide operating voltage range V to V High efficiency boost regulator from 0.5-V input through 1.8-V to 5.0-V output mA at 3 MHz, mA at 6 MHz, and mA at 48 MHz Low-power modes including
• 1-µA sleep mode with real time clock and low-voltage detect LVD interrupt
• 200-nA hibernate mode with RAM retention
- Versatile I/O system 28 to 72 I/O 62 GPIOs, eight special input/outputs SIO , two USBIOs[2] Any GPIO to any digital or analog peripheral routability LCD direct drive from any GPIO, up to 46 x 16 segments[2] support from any GPIO[3] 1.2-V to 5.5-V I/O interface voltages, up to four domains Maskable, independent IRQ on any pin or port Schmitt-trigger transistor-transistor logic TTL inputs All GPIO configurable as open drain high/low, pull-up/pull-down, High Z, or strong output Configurable GPIO pin state at power-on reset POR 25 mA sink on SIO
- Digital peripherals 20 to 24 programmable logic device PLD based universal digital blocks UDB Full CAN 2.0b 16 Rx, 8 Tx buffers[2] Full-speed FS USB 12 Mbps using internal oscillator[2] Up to four 16-bit configurable timer, counter, and PWM blocks Library of standard peripherals
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
• Serial peripheral interface SPI , universal asynchronous transmitter receiver UART , and I2C
• Many others available in catalog Library of advanced peripherals
• Cyclic redundancy check CRC
• Pseudo random sequence PRS generator
• Local interconnect network LIN bus
• Quadrature decoder
- Analog peripherals V VDDA V ± internal voltage reference across °C to +85 °C 14 ppm/°C Configurable delta-sigma ADC with 8- to 20-bit resolution
• Sample rates up to 192 ksps
• Programmable gain stage to x16
• 12-bit mode, 192 ksps, 66-dB signal to noise and distortion ratio SINAD , ±1-bit INL/DNL
• 16-bit mode, 48 ksps, 84-dB SINAD, ±2-bit INL, ±1-bit DNL 67 MHz, 24-bit fixed point digital filter block DFB to implement FIR and IIR filters Up to four 8-bit, 8-Msps IDACs or 1-Msps VDACs Four comparators with 95-ns response time Up to four uncommitted opamps with 25-mA drive capability Up to four configurable multifunction analog blocks. Example configurations are programmable gain amplifier PGA , transimpedance amplifier TIA , mixer, and sample and hold CapSense support
- Programming, debug, and trace JTAG 4-wire , serial wire debug SWD 2-wire , and single wire viewer SWV interfaces Eight address and one data breakpoint 4-KB instruction trace buffer Bootloader programming supportable through I2C, SPI, UART, USB, and other interfaces
- Precision, programmable clocking 3- to 62-MHz internal oscillator over full temperature and voltage range 4- to 33-MHz crystal oscillator for crystal PPM accuracy Internal PLL clock generation up to 67 MHz 32.768-kHz watch crystal oscillator Low-power internal oscillator at 1, 33, and 100 kHz
- Temperature and packaging to +85 °C degrees industrial temperature 48-pin SSOP, 48-pin QFN, 68-pin QFN, and 100-pin TQFP package options
Notes AHB AMBA advanced microcontroller bus architecture high-performance bus, an ARM data transfer bus This feature on select devices only. See Ordering Information on page 105 for details. GPIOs with opamp outputs are not recommended for use with CapSense.
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PRELIMINARY 3 CY8C38 Family Datasheet

Contents

Architectural Overview 3 Pinouts 5 Pin Descriptions 10 CPU 11
8051 CPU 11 Addressing Modes 11 Instruction Set 11 DMA and PHUB 15 Interrupt Controller 17 Memory 18 Static RAM 18 Flash Program Memory 18 Flash Security 18 EEPROM 18 External Memory Interface 18 Memory Map 19 System Integration 21 Clocking System 21 Power System 24 Reset 27 I/O System and Routing 28 Digital Subsystem 34 Example Peripherals 35 Universal Digital Block 37 UDB Array Description 41 DSI Routing Interface Description 41 CAN 43 USB 44 Timers, Counters, and PWMs 45 I2C 45 Digital Filter Block 45 Analog Subsystem 46 Analog Routing 47 Delta-sigma ADC 49 Comparators 50 Opamps 51 Programmable SC/CT Blocks 52 LCD Direct Drive 53
Page 2 of 117
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PRELIMINARY 3 CY8C38 Family Datasheet

Architectural Overview

Introducing the CY8C38 family of ultra low-power, flash Programmable System-on-Chip devices, part of a scalable 8-bit PSoC 3 and 32-bit PSoC 5 platform. The CY8C38 family provides configurable blocks of analog, digital, and interconnect circuitry around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables a high level of integration in a wide variety of consumer, industrial, and medical applications.

Figure Simplified Block Diagram
4 to 33 MHz Optiona l

KHz Optiona l

GPIOs

GPIOs

GPIOs

System Wide Resources

Xtal Osc

RTC Timer

WDT and Wake

Clock Tree

Usage Example for UDB Sequencer

Digital Interconnect

Analog Interconnect

Digital System

Universal Digital Block Array 24x UDB
8-bit

Quadrature Decoder

Timer
16- bit PWM
16-bit PRS UDB

UDB I 2C Slave

UDB 8-bit SPI

UDB UART

UDB 12-bit SPI

UDB 8-bit Timer

Logic

Logic UDB
12- bit PWM
4x Timer Counter PWM

Master/ Slave

FS USB

System Bus

Memory System

EEPROM

SRAM
Notes This feature on select devices only. See Ordering Information on page 105 for details. GPIOs with opamp outputs are not recommended for use with CapSense.

Page 4 of 117
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PRELIMINARY 3 CY8C38 Family Datasheet

It also contains a separate, very low-power internal low-speed oscillator ILO for the sleep and watchdog timers. A 32.768-kHz external watch crystal is also supported for use in real-time clock RTC applications. The clocks, together with programmable clock dividers, provide the flexibility to integrate most timing requirements.

The CY8C38 family supports a wide supply operating range from V to V. This allows operation from regulated supplies such as V ± 5%, V ±10%, V ± 10%, or V ± 10%, or directly from a wide range of battery types. In addition, it provides an integrated high efficiency synchronous boost converter that can power the device from supply voltages as low as V. This enables the device to be powered directly from a single battery or solar cell. In addition, you can use the boost converter to generate other voltages required by the device, such as a 3.3-V supply for LCD glass drive. The boost’s output is available on the Vboost pin, allowing other devices in the application to be powered from the PSoC.

PSoC supports a wide range of low-power modes. These include a 200-nA hibernate mode with RAM retention and a 1-µA sleep mode with RTC. In the second mode, the optional 32.768-kHz watch crystal runs continuously and maintains an accurate RTC.

Power to all major functional blocks, including the programmable digital and analog peripherals, can be controlled independently by firmware. This allows low-power background processing when some peripherals are not in use. This, in turn, provides a total device current of only mA when the CPU is running at 6 MHz, or mA running at 3 MHz.

The details of the PSoC power modes are covered in the “Power System” section on page 24 of this datasheet.

PSoC uses JTAG 4-wire or SWD 2-wire interfaces for programming, debug, and test. The 1-wire SWV may also be used for ‘printf’ style debugging. By combining SWD and SWV, you can implement a full debugging interface with just three pins. Using these standard interfaces you can debug or program the PSoC with a variety of hardware solutions from Cypress or third party vendors. PSoC supports on-chip break points and 4-KB instruction and data race memory for debug. Details of the programming, test, and debugging interfaces are discussed in the “Programming, Debug Interfaces, Resources” section on page 56 of this datasheet.

Pinouts

The Vddio pin that supplies a particular set of pins is indicated by the black lines drawn on the pinout diagrams in Figure 2-1 through Figure Using the Vddio pins, a single PSoC can support multiple interface voltage levels, eliminating the need for off-chip level shifters. Each Vddio may sink up to 100 mA total to its associated I/O pins and opamps. On the 68-pin and 100-pin devices each set of Vddio associated pins may sink up to 100 mA. The 48-pin device may sink up to 100 mA total for all Vddio0 plus Vddio2 associated I/O pins and 100 mA total for all Vddio1 plus Vddio3 associated I/O pins.

Figure 48-pin SSOP Part Pinout

SIO P12[2] 1 SIO P12[3] 2 OpAmp2out, GPIO P0[0] 3 OpAmp0out, GPIO P0[1] 4 OpAmp0+, GPIO P0[2] 5 OpAmp0-/Extref0, GPIO P0[3] 6

Vddio0 7 OpAmp2+, GPIO P0[4] 8 OpAmp2-, GPIO P0[5] 9

IDAC0, GPIO P0[6] 10 IDAC2, GPIO P0[7] 11

Vccd 12 Vssd 13 Vddd 14 GPIO P2[3] 15 GPIO P2[4] 16 Vddio2 17 GPIO P2[5] 18 GPIO P2[6] 19 GPIO P2[7] 20 Vssb 21

Ind 22 Vboost 23

Vbat 24

Lines show 46

Vddio to I/O supply
association 44

SSOP 37

Vdda

Vssa

Vcca

P15[3] GPIO, kHz XTAL Xi

P15[2] GPIO, kHz XTAL Xo

P12[1] SIO, I2C1 SDA

P12[0] SIO, I2C1 SCL

Vddio3

P15[1] GPIO, MHz XTAL Xi

P15[0] GPIO, MHz XTAL Xo

Vccd

Vssd

Vddd

P15[7] USBIO, D-, SWDCK [6]

P15[6] USBIO, D+, SWDIO

P1[7] GPIO

P1[6] GPIO

Vddio1
Ordering Information

In addition to the features listed in Table 12-1, every CY8C38 device includes a precision on-chip voltage reference, precision oscillators, flash, ECC, DMA, a fixed function I2C, 4 KB trace RAM, JTAG/SWD programming and debug, external memory interface, and more. In addition to these features, the flexible UDBs and analog subsection support a wide range of peripherals. To assist you in selecting the ideal part, PSoC Creator makes a part recommendation after you choose the components required by your application. All CY8C38 derivatives incorporate device and flash security in user-selectable security levels see the TRM for details.

Table CY8C38 Family with Single Cycle 8051

MCU Core

Analog

Digital

I/O[56]

Package JTAG ID[57]

CapSense UDBs[55] 16-bit Timer/PWM FS USB CAN 2.0b Total I/O GPIO SIO USBIO

Blocks[54]

Opamps

SC/CT Analog

Comparator

CPU Speed MHz Flash KB SRAM KB EEPROM KB LCD Segment Drive
32 KB Flash

CY8C3865AXI-056 67 32 4 1 20-bit Del-Sig 4 20 4 70 62 8 0 100-pin TQFP 0x0E038069 CY8C3865LTI-045 67 32 4 1 20-bit Del-Sig 4 20 4 46 38 8 0 68-pin QFN 0x0E02D069 CY8C3865LTI-058 67 32 4 1 20-bit Del-Sig 4 2 20 4 29 25 4 0 48-pin QFN 0x0E03A069 CY8C3865PVI-051 67 32 4 1 20-bit Del-Sig 4 2 20 4 29 25 4 0 48-pin SSOP 0x0E033069 CY8C3865AXI-015 67 32 4 1 20-bit Del-Sig 4 20 4 72 62 8 2 100-pin TQFP 0x0E00F069 CY8C3865LTI-032 67 32 4 1 20-bit Del-Sig 4 20 4 48 38 8 2 68-pin QFN 0x0E020069 CY8C3865LTI-061 67 32 4 1 20-bit Del-Sig 4 2 20 4 31 25 4 2 48-pin QFN 0x0E03D069 CY8C3865PVI-053 67 32 4 1 20-bit Del-Sig 4 2 20 4 31 25 4 2 48-pin SSOP 0x0E035069 CY8C3865AXI-018 67 32 4 1 20-bit Del-Sig 4 20 4 70 62 8 0 100-pin TQFP 0x0E012069 CY8C3865LTI-024 67 32 4 1 20-bit Del-Sig 4 20 4 46 38 8 0 68-pin QFN 0x0E018069 CY8C3865LTI-059 67 32 4 1 20-bit Del-Sig 4 2 20 4 29 25 4 0 48-pin QFN 0x0E03B069 CY8C3865PVI-060 67 32 4 1 20-bit Del-Sig 4 2 20 4 29 25 4 0 48-pin SSOP 0x0E03C069 CY8C3865AXI-019 67 32 4 1 20-bit Del-Sig 4 20 4 72 62 8 2 100-pin TQFP 0x0E013069 CY8C3865LTI-014 67 32 4 1 20-bit Del-Sig 4 20 4 48 38 8 2 68-pin QFN 0x0E00E069 CY8C3865LTI-062 67 32 4 1 20-bit Del-Sig 4 2 20 4 31 25 4 2 48-pin QFN 0x0E03E069 CY8C3865PVI-063 67 32 4 1 20-bit Del-Sig 4 2 20 4 31 25 4 2 48-pin SSOP 0x0E03F069 64 KB Flash CY8C3866AXI-054 67 64 8 2 20-bit Del-Sig 4 24 4 70 62 8 0 100-pin TQFP 0x0E036069 CY8C3866LTI-020 67 64 8 2 20-bit Del-Sig 4 24 4 46 38 8 0 68-pin QFN 0x0E014069 CY8C3866LTI-064 67 64 8 2 20-bit Del-Sig 4 2 24 4 29 25 4 0 48-pin QFN 0x0E040069 CY8C3866PVI-005 67 64 8 2 20-bit Del-Sig 4 2 24 4 29 25 4 0 48-pin SSOP 0x0E005069 CY8C3866AXI-033 67 64 8 2 20-bit Del-Sig 4 24 4 72 62 8 2 100-pin TQFP 0x0E021069 CY8C3866LTI-023 67 64 8 2 20-bit Del-Sig 4 24 4 48 38 8 2 68-pin QFN 0x0E017069 CY8C3866LTI-067 67 64 8 2 20-bit Del-Sig 4 2 24 4 31 25 4 2 48-pin QFN 0x0E043069 CY8C3866PVI-021 67 64 8 2 20-bit Del-Sig 4 2 24 4 31 25 4 2 48-pin SSOP 0x0E015069 CY8C3866AXI-038 67 64 8 2 20-bit Del-Sig 4 24 4 70 62 8 0 100-pin TQFP 0x0E026069 CY8C3866LTI-029 67 64 8 2 20-bit Del-Sig 4 24 4 46 38 8 0 68-pin QFN 0x0E01D069 CY8C3866LTI-065 67 64 8 2 20-bit Del-Sig 4 2 24 4 29 25 4 0 48-pin QFN 0x0E041069 CY8C3866PVI-066 67 64 8 2 20-bit Del-Sig 4 2 24 4 29 25 4 0 48-pin SSOP 0x0E042069

Notes

Analog blocks support a variety of functionality including TIA, PGA, and mixers. See the Example Peripherals on page 35 for more information on how analog blocks can be used.

UDBs support a variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or multiple UDBs. Multiple functions can share a single UDB. See the Example Peripherals on page 35 for more information on how UDBs can be used.

The I/O Count includes all types of digital I/O GPIO, SIO, and the two USB I/O. See the I/O System and Routing on page 28 for details on the functionality of each of these types of I/O.

The JTAG ID has three major fields. The most significant nibble left digit is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID.

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Table CY8C38 Family with Single Cycle 8051 continued

MCU Core

Analog

Digital

I/O[60] Package JTAG ID[61]

CapSense UDBs[59] 16-Bit Timer/PWM FS USB CAN 2.0b Total I/O GPIO SIO USBIO

Blocks[58]

Opamps

SC/CT Analog

Comparator

CPU Speed MHz Flash KB SRAM KB EEPROM KB LCD Segment Drive

CY8C3866AXI-039 67 64 8 2 20-bit Del-Sig 4 24 4 72 62 8 2 100-pin TQFP 0x0E027069 CY8C3866LTI-030 67 64 8 2 20-bit Del-Sig 4 24 4 48 38 8 2 68-pin QFN 0x0E01E069 CY8C3866LTI-068 67 64 8 2 20-bit Del-Sig 4 2 24 4 31 25 4 2 48-pin QFN 0x0E044069 CY8C3866PVI-069 67 64 8 2 20-bit Del-Sig 4 2 24 4 31 25 4 2 48-pin SSOP 0x0E045069 CY8C3866AXI-040 67 64 8 2 20-bit Del-Sig 4 24 4 72 62 8 2 100-pin TQFP 0x0E028069 CY8C3866PVI-047 67 64 8 2 20-bit Del-Sig 4 2 24 4 29 25 4 0 48-pin SSOP 0x0E02F069 CY8C3866PVI-070 67 64 8 2 20-bit Del-Sig 4 2 24 4 29 25 4 0 48-pin SSOP 0x0E046069 CY8C3866AXI-055 67 64 8 2 20-bit Del-Sig 4 24 4 70 62 8 0 100-pin TQFP 0x0E037069 CY8C3866AXI-035 67 64 8 2 20-bit Del-Sig 4 24 4 70 62 8 0 100-pin TQFP 0x0E023069

Notes

Analog blocks support a variety of functionality including TIA, PGA, and mixers. See the Example Peripherals on page 35 for more information on how analog blocks can be used.

UDBs support a variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or multiple UDBs. Multiple functions can share a single UDB. See the Example Peripherals on page 35 for more information on how UDBs can be used.

The I/O Count includes all types of digital I/O GPIO, SIO, and the two USB I/O. See the I/O System and Routing on page 28 for details on the functionality of each of these types of I/O.

The JTAG ID has three major fields. The most significant nibble left digit is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID.
Signals section. Classified Ordering Information according to CPU speed;
added information on security features and ROHS compliance

Added a section on XRES Specifications under Electrical Specification.

Updated Analog Subsystem and CY8C35/55 Architecture block diagrams.

Updated Electrical Specifications. Renamed CyDesigner as PSoC Creator
2712468 05/29/09

MKEA Updates to Electrical Specifications. Added Analog Routing section
Updates to Ordering Information table
2758970 09/02/09

MKEA Updated Part Numbering Conventions. Added Section EMIF Figures
and Tables . Updated GPIO and SIO AC specifications. Updated XRES Pin

Description and Xdata Address Map specifications. Updated DFB and

Comparator specifications. Updated PHUB features section and RTC in sleep
mode. Updated IDAC and VDAC DC and Analog Global specifications

Updated USBIO AC and Delta Sigma ADC specifications. Updated PPOR and

Voltage Monitors DC specifications. Updated Drive Mode diagram

Added 48-QFN Information. Updated other electrical specifications
2824546 12/09/09

MKEA Updated I2C section to reflect 1 Mbps. Updated Table 11-6 and 11- 7 Boost AC
and DC specs also added Shottky Diode specs. Changed current for
sleep/hibernate mode to include SIO Added footnote to analog global specs.

Updated Figures 1-1, 6-2, 7-14, and Updated Table 6-2 and Table 6-3

Hibernate and Sleep rows and Power Modes section. Updated GPIO and SIO

AC specifications. Updated Gain error in IDAC and VDAC specifications.

Updated description of VDDA spec in Table 11-1 and removed GPIO Clamp Current parameter. Updated number of UDBs on page

Moved FILO from ILO DC to AC table.

Added PCB Layout and PCB Schematic diagrams.

Updated Fgpioout spec Table Added duty cycle frequency in PLL AC
spec table. Added note for Sleep and Hibernate modes and Active Mode specs
in Table Linked URL in Section to PSoC Creator site.

Updated Ja and Jc values in Table Updated Single Sample Mode and Fast

FIR Mode sections. Updated Input Resistance specification in Del-Sig ADC
table. Added Tio_init parameter. Updated PGA and UGB AC Specs. Removed

SPC ADC. Updated Boost Converter section.

Added section 'SIO as Comparator' updated Hysteresis spec differential
mode in Table

Updated VBAT condition and deleted Vstart parameter in Table Added 'Bytes' column for Tables 4-1 to
2873322 02/04/10

MKEA Changed maximum value of PPOR_TR to Updated VBIAS specification.

Updated PCB Schematic. Updated Figure 8-1 and Figure Updated Interrupt

Vector table, Updated Sales links. Updated JTAG and SWD specifications.

Removed Jp-p and Jperiod from ECO AC Spec table. Added note on sleep timer
in Table Updated ILO AC and DC specifications. Added Resolution
parameter in VDAC and IDAC tables. Updated IOUT typical and maximum values. Changed Temperature Sensor range to °C to +85 °C. Removed

Latchup specification from Table

Page 114 of 117
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PRELIMINARY 3 CY8C38 Family Datasheet
Removed ESO parts from ordering information

Changed USBIO pins from NC to DNU and removed redundant USBIO pin
description notes

Updated POR with brown out DC and AC specs

Updated PGA AC specs

Updated 32 kHz External Crystal DC Specifications

Updated opamp AC specs

Updated XRES IO specs

Updated Inductive boost regulator section

Delta sigma ADC spec updates

Updated comparator section

Removed buzz mode from Power Mode Transition diagram

Updated opamp DC and AC spec tables

Updated PGA DC table

Page 116 of 117
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PRELIMINARY 3 CY8C38 Family Datasheet

Description Title 3 CY8C38 Family Datasheet Programmable System-on-Chip Document Number 001-11729
3179219 02/22/2011 MKEA Updated conditions for flash data retention time

Updated 100-pin TQFP package spec.

Updated EEPROM AC specifications.

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturers’ representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

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and Creator are trademarks and is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations.

Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

ARM is a registered trademark, and Keil, and RealView are trademarks, of ARM Limited. All products and company names mentioned in this document may be the trademarks of their respective holders.
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More datasheets: CY8C3866PVI-005 | CY8C3866LTI-064 | CY8C3866LTI-029 | CY8C3866LTI-023 | CY8C3866LTI-020 | CY8C3866AXI-038 | CY8C3866AXI-054 | CY8C3866PVI-047 | CY8CKIT-009A | CY8C3865AXI-018


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Datasheet ID: CY8C3865AXI-056 508167