CY8C27643-24PVIT

CY8C27643-24PVIT Datasheet

CY8C27143, CY8C27243, CY8C27443, CY8C27543, and CY8C27643

Part	Datasheet
CY8C27643-24PVIT	CY8C27643-24PVIT (pdf)

Related Parts	Information
CY8C27643-24LFXIT	CY8C27643-24LFXIT
CY8C27243-24PVI	CY8C27243-24PVI
CY8C27443-24PVI	CY8C27443-24PVI
CY8C27243-24PVIT	CY8C27243-24PVIT
CY8C27443-24PVIT	CY8C27443-24PVIT
CY8C27643-24LFXI	CY8C27643-24LFXI

PDF Datasheet Preview
PSoC Mixed Signal Array CY8C27143, CY8C27243, CY8C27443, CY8C27543, and CY8C27643 Final Data Sheet • Powerful Harvard Architecture Processor M8C Processor Speeds to 24 MHz 8x8 Multiply, 32-Bit Accumulate Low Power at High Speed to V Operating Voltage Operating Voltages Down to 1.0V Using OnChip Switch Mode Pump SMP Industrial Temperature Range -40°C to +85°C • Advanced Peripherals PSoC Blocks 12 Rail-to-Rail Analog PSoC Blocks Provide: - Up to 14-Bit ADCs - Up to 9-Bit DACs - Programmable Gain Amplifiers - Programmable Filters and Comparators 8 Digital PSoC Blocks Provide: - 8- to 32-Bit Timers, Counters, and PWMs - CRC and PRS Modules - Up to 2 Full-Duplex UARTs - Multiple SPI Masters or Slaves - Connectable to all GPIO Pins Complex Peripherals by Combining Blocks • Precision, Programmable Clocking Internal 24/48 MHz Oscillator 24/48 MHz with Optional 32 kHz Crystal Optional External Oscillator, up to 24 MHz Internal Oscillator for Watchdog and Sleep • Flexible On-Chip Memory 16K Bytes Flash Program Storage 50,000 Erase/Write Cycles 256 Bytes SRAM Data Storage In-System Serial Programming ISSP Partial Flash Updates Flexible Protection Modes EEPROM Emulation in Flash • Programmable Pin Configurations 25 mA Sink on all GPIO Pull up, Pull down, High Z, Strong, or Open Drain Drive Modes on all GPIO Up to 12 Analog Inputs on GPIO Four 30 mA Analog Outputs on GPIO Configurable Interrupt on all GPIO • Additional System Resources I2C Slave, Master, and Multi-Master to 400 kHz Watchdog and Sleep Timers User-Configurable Low Voltage Detection Integrated Supervisory Circuit On-Chip Precision Voltage Reference • Complete Development Tools Free Development Software PSoC Designer Full-Featured, In-Circuit Emulator and Programmer Full Speed Emulation Complex Breakpoint Structure 128K Bytes Trace Memory PSoC CORE Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Analog Drivers System Bus Global Digital Interconnect Global Analog Interconnect SRAM 256 Bytes SROM Flash 16K Interrupt Controller CPU Core M8C Sleep and Watchdog Multiple Clock Sources Includes IMO, ILO, PLL, and ECO DIGITAL SYSTEM Digital Block Array 2 Rows, 8 Blocks ANALOG SYSTEM Analog Block Array Analog Ref 4 Columns, 12 Blocks Analog Input Muxing Digital Clocks Multiply Accum. For up-to-date Ordering, Packaging, and Electrical Specification information, reference the latest PSoC device data sheets on the web at Development Kits Development Kits are available from the following distributors Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store at contains development kits, C compilers, and all accessories for PSoC development. Click on PSoC Programmable System-on-Chip to view a current list of available items. Tele-Training Free PSoC "Tele-training" is available for beginners and taught by a live marketing or application engineer over the phone. Five training classes are available to accelerate the learning curve including introduction, designing, debugging, advanced design, advanced analog, as well as application-specific classes covering topics like PSoC and the LIN bus. For days and times of the tele-training, see Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant, go to the following Cypress support web site: Technical Support PSoC application engineers take pride in fast and accurate response. They can be reached with a 4-hour guaranteed response at Application Notes A long list of application notes will assist you in every aspect of your design effort. To locate the PSoC application notes, go to Development Tools The Cypress MicroSystems PSoC Designer is a Windows-based, integrated development environment for the Programmable System-on-Chip PSoC devices. The PSoC Designer IDE and application runs on Windows NT Windows 2000, Windows Millennium Me , or Windows XP. Reference the PSoC Designer Functional Flow diagram below. PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the PSoC, and debug the application. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and the CYASM macro assembler for the CPUs. PSoC Designer also supports a high-level C language compiler developed specifically for the devices in the family. PSoCTM Designer Graphical Designer Interface Context Sensitive Help Commands Results Importable Design Database Device Database Application Database Project Database User Modules Library PSoCTM Designer Core Engine PSoC Configuration Sheet Manufacturing Information File Emulation Pod In-Circuit Emulator Device Programmer PSoC Designer Subsystems August 3, 2004 CY8C27x43 Final Data Sheet PSoC Overview PSoC Designer Software Subsystems Device Editor Ordering Information 42 Ordering Code Definitions 43 Sales and Service Information 44 August 3, 2004 Pin Information This chapter describes, lists, and illustrates the CY8C27x43 PSoC device pins and pinout configurations. Pinouts The CY8C27x43 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin labeled with a “P” is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO. 8-Pin Part Pinout Table 8-Pin Part Pinout PDIP Type No. Digital Analog Name IO P0[5] Analog column mux input and column output. IO P0[3] Analog column mux input and column output. P1[1] Crystal Input XTALin , I2C Serial Clock SCL Power Ground connection. P1[0] Crystal Output XTALout , I2C Serial Data SDA IO P0[2] Analog column mux input and column output. IO P0[4] Analog column mux input and column output. Power Supply voltage. LEGEND A = Analog, I = Input, and O = Output. CY8C27143 8-Pin PSoC Device AIO, P0[5] AIO, P0[3] I2C SCL, XTALin, P1[1] 2PDIP7 36 45 Vdd P0[4], AIO P0[2], AIO P1[0], XTALout, I2C SDA August 3, 2004 CY8C27x43 Final Data Sheet 20-Pin Part Pinout Table 20-Pin Part Pinout SSOP, SOIC Type No. Digital Analog Name I P0[7] Analog column mux input. IO P0[5] Analog column mux input and column output. IO P0[3] Analog column mux input and column output. I P0[1] Analog column mux input. Power SMP Switch Mode Pump SMP connection to external components required. b. Refer to the Ordering Information chapter on page DC General Purpose IO Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges 4.75V to 5.25V and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table DC GPIO Specifications Symbol RPU RPD VOH Pull up Resistor Pull down Resistor High Output Level Low Output Level VIL VIH VH IIL CIN COUT Input Low Level Input High Level Input Hysterisis Input Leakage Absolute Value Capacitive Load on Pins as Input Capacitive Load on Pins as Output Min 4 Vdd - Max 8 Units V V mV nA pF Notes IOH = 10 mA, Vdd = to 5.25V 8 total loads, 4 on even port pins for example, P0[2], P1[4] , 4 on odd port pins for example, P0[3], P1[5] . IOL = 25 mA, Vdd = to 5.25V 8 total loads, 4 on even port pins for example, P0[2], P1[4] , 4 on odd port pins for example, P0[3], P1[5] . Vdd = to Vdd = to Gross tested to 1 µA. Package and pin dependent. Temp = 25oC. Package and pin dependent. Temp = 25oC. August 3, 2004 CY8C27x43 Final Data Sheet Electrical Specifications DC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges 4.75V to 5.25V and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 5V DC Operational Amplifier Specifications Symbol VOSOA TCVOSOA IEBOA CINOA VCMOA Description Input Offset Voltage absolute value Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Average Input Offset Voltage Drift Input Leakage Current Port 0 Analog Pins Input Capacitance Port 0 Analog Pins Common Mode Voltage Range Common Mode Voltage Range high power or high opamp bias CMRROA GOLOA VOHIGHOA VOLOWOA ISOA PSRROA Common Mode Rejection Ratio Power = Low Power = Medium Power = High Open Loop Gain Power = Low Power = Medium Power = High Output Voltage Swing internal signals Power = Low Power = Medium Power = High Low Output Voltage Swing internal signals Power = Low Power = Medium Power = High Supply Current including associated AGND buffer Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High Supply Voltage Rejection Ratio 60 80 Vdd - Vdd - Vdd - 1200 2400 4600 Units Notes µV/oC Vdd - a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz 42 ns nominal period . b. Refer to the Ordering Information chapter on page Notes 4.75V < Vdd < 5.25V. 3.0V < Vdd < 4.75V. 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V. Maximum data rate at MHz due to 2 x over clocking. Maximum data rate at MHz due to 8 x over clocking. Maximum data rate at MHz due to 8 x over clocking. Maximum data rate at MHz due to 8 x over clocking. Maximum data rate at MHz due to 8 x over clocking. August 3, 2004 CY8C27x43 Final Data Sheet Electrical Specifications AC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges 4.75V to 5.25V and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 5V AC Analog Output Buffer Specifications Symbol TROB TSOB SRROB SRFOB BWOB Description Rising Settling Time to 1V Step, 100pF Load Power = Low Power = High Falling Settling Time to 1V Step, 100pF Load Power = Low Power = High Rising Slew Rate 20% to 80% , 1V Step, 100pF Load Power = Low Power = High Falling Slew Rate 80% to 20% , 1V Step, 100pF Load Power = Low Power = High Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load Power = Low Power = High Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load Power = Low Power = High Units µs µs µs µs V/µs V/µs V/µs V/µs Notes Table 3.3V AC Analog Output Buffer Specifications Symbol TROB TSOB SRROB SRFOB BWOB Description Rising Settling Time to 1V Step, 100pF Load Power = Low Power = High Falling Settling Time to 1V Step, 100pF Load Power = Low Power = High Rising Slew Rate 20% to 80% , 1V Step, 100pF Load Power = Low Power = High Falling Slew Rate 80% to 20% , 1V Step, 100pF Load Power = Low Power = High Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load Power = Low Power = High Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load Power = Low Power = High Units µs µs µs µs V/µs V/µs V/µs V/µs Notes August 3, 2004 CY8C27x43 Final Data Sheet Electrical Specifications AC External Clock Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges 4.75V to 5.25V and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 5V AC External Clock Specifications Symbol FOSCEXT Description Frequency High Period Low Period Power Up IMO to Switch Min 150 Ordering Information The following table lists the CY8C27x43 PSoC device family’s key package features and ordering codes. Table CY8C27x43 PSoC Device Family Key Features and Ordering Information Flash Kbytes RAM Bytes Switch Mode Pump Temperature Range Digital Blocks Rows of 4 Analog Blocks Columns of 3 Digital IO Pins Analog Inputs Analog Outputs XRES Pin Package Ordering Code CY8C27x43 Silicon B These parts are lead free and offer the following improvements. The DEC_CR1 register selections are enhanced to allow any digital block to be the decimator clock source, the ECO EX and ECO EXW bits in the CPU_SCR1 register are readable, and the accuracy of the analog reference is enhanced see the Electrical Specifications chapter . All silicon A errata are fixed in silicon B. 8 Pin 300 Mil DIP CY8C27143-24PXI 16 256 No -40C to +85C 8 20 Pin 210 Mil SSOP CY8C27243-24PVXI 16 256 Yes -40C to +85C 8 12 16 4 Yes 20 Pin 210 Mil SSOP Tape and Reel CY8C27243-24PVXIT 16 256 Yes -40C to +85C 8 12 16 8 4 Yes 20 Pin 300 Mil SOIC CY8C27243-24SXI 16 256 Yes -40C to +85C 8 12 16 8 4 Yes 20 Pin 300 Mil SOIC Tape and Reel CY8C27243-24SXIT 16 256 Yes -40C to +85C 8 12 16 8 4 Yes 28 Pin 300 Mil DIP CY8C27443-24PXI 16 256 Yes -40C to +85C 8 12 24 12 4 Yes 28 Pin 210 Mil SSOP CY8C27443-24PVXI 16 256 Yes -40C to +85C 8 12 24 12 4 Yes 28 Pin 210 Mil SSOP Tape and Reel CY8C27443-24PVXIT 16 256 Yes -40C to +85C 8 12 24 12 4 Yes 28 Pin 300 Mil SOIC CY8C27443-24SXI 16 256 Yes -40C to +85C 8 Ordering Information Table CY8C27x43 PSoC Device Family Key Features and Ordering Information continued Flash Kbytes RAM Bytes Switch Mode Pump Temperature Range Digital Blocks Rows of 4 Analog Blocks Columns of 3 Digital IO Pins Analog Inputs Analog Outputs XRES Pin Package 28 Pin 210 Mil SSOP Tape and Reel 28 Pin 300 Mil SOIC 28 Pin 300 Mil SOIC Tape and Reel 44 Pin TQFP 44 Pin TQFP Tape and Reel 48 Pin 300 Mil SSOP 48 Pin 300 Mil SSOP Tape and Reel 48 Pin 7x7 MLF 48 Pin 7x7 MLF Tape and Reel Ordering Code CY8C27443-24PVIT CY8C27443-24SI CY8C27443-24SIT CY8C27543-24AI CY8C27543-24AIT CY8C27643-24PVI CY8C27643-24PVIT CY8C27643-24LFI CY8C27643-24LFIT 16 256 Yes -40C to +85C 8 16 256 Yes -40C to +85C 8 16 256 Yes -40C to +85C 8 16 256 Yes -40C to +85C 8 16 256 Yes -40C to +85C 8 16 256 Yes -40C to +85C 8 16 256 Yes -40C to +85C 8 16 256 Yes -40C to +85C 8 16 256 Yes -40C to +85C 8 12 24 12 24 12 24 12 40 12 40 12 44 12 44 12 44 12 44 12 4 Yes 4 Yes 4 Yes 4 Yes 4 Yes 4 Yes 4 Yes 4 Yes 4 Yes Ordering Code Definitions CY 8 C 27 xxx-SPxx Package Type P = PDIP S = SOIC PV = SSOP LF = MLF A = TQFP PX = PDIP Pb Free SX = SOIC Pb Free PVX = SSOP Pb Free LFX = MLF Pb Free AX = TQFP Pb Free Speed 24 MHz Family Code Technology Code C = CMOS Marketing Code 8 = Cypress MicroSystems Company ID CY = Cypress Thermal Rating C = Commercial I = Industrial E = Extended August 3, 2004 Sales and Service Information To obtain information about Cypress MicroSystems or PSoC sales and technical support, reference the following information or go to the section titled “Getting Started” on page 4 in this document. Cypress MicroSystems 2700 162nd Street SW Building D Lynnwood, WA 98037 Phone: Facsimile: Web Sites: Company Information Sales Technical Support Document Title: CY8C27143, CY8C27243, CY8C27443, CY8C27543, and CY8C27643 PSoC Mixed Signal Array Final Data Sheet Document Number 38-12012 ECN # Issue Date Origin of Change Description of Change 127087 7/01/2003 New Silicon. 128780 7/29/2003 Engineering and New electrical spec additions, fix of Core Architecture links, corrections to some text, tables, draw- NWJ. ings, and format. 128992 8/14/2003 NWJ Interrupt controller table fixed, refinements to Electrical Spec section and Register chapter. 129283 8/28/2003 NWJ Significant changes to the Electrical Specifications section. 129442

PDF Datasheet Preview

PSoC Mixed Signal Array

CY8C27143, CY8C27243, CY8C27443, CY8C27543, and CY8C27643

Final Data Sheet
• Powerful Harvard Architecture Processor M8C Processor Speeds to 24 MHz 8x8 Multiply, 32-Bit Accumulate Low Power at High Speed to V Operating Voltage Operating Voltages Down to 1.0V Using OnChip Switch Mode Pump SMP Industrial Temperature Range -40°C to +85°C
• Advanced Peripherals PSoC Blocks 12 Rail-to-Rail Analog PSoC Blocks Provide:
- Up to 14-Bit ADCs - Up to 9-Bit DACs - Programmable Gain Amplifiers - Programmable Filters and Comparators 8 Digital PSoC Blocks Provide:
- 8- to 32-Bit Timers, Counters, and PWMs - CRC and PRS Modules - Up to 2 Full-Duplex UARTs - Multiple SPI Masters or Slaves - Connectable to all GPIO Pins Complex Peripherals by Combining Blocks
• Precision, Programmable Clocking Internal 24/48 MHz Oscillator 24/48 MHz with Optional 32 kHz Crystal Optional External Oscillator, up to 24 MHz Internal Oscillator for Watchdog and Sleep
• Flexible On-Chip Memory 16K Bytes Flash Program Storage 50,000 Erase/Write Cycles 256 Bytes SRAM Data Storage In-System Serial Programming ISSP Partial Flash Updates Flexible Protection Modes EEPROM Emulation in Flash
• Programmable Pin Configurations 25 mA Sink on all GPIO Pull up, Pull down, High Z, Strong, or Open Drain Drive Modes on all GPIO Up to 12 Analog Inputs on GPIO Four 30 mA Analog Outputs on GPIO Configurable Interrupt on all GPIO
• Additional System Resources

I2C Slave, Master, and Multi-Master to 400 kHz

Watchdog and Sleep Timers User-Configurable Low Voltage Detection Integrated Supervisory Circuit On-Chip Precision Voltage Reference
• Complete Development Tools Free Development Software PSoC Designer Full-Featured, In-Circuit Emulator and Programmer Full Speed Emulation Complex Breakpoint Structure 128K Bytes Trace Memory

PSoC CORE

Port 5

Port 4

Port 3

Port 2

Port 1

Port 0

Analog Drivers

System Bus

Global Digital Interconnect

Global Analog Interconnect

SRAM 256 Bytes

SROM Flash 16K

Interrupt Controller

CPU Core M8C

Sleep and Watchdog

Multiple Clock Sources Includes IMO, ILO, PLL, and ECO

DIGITAL SYSTEM

Digital Block Array
2 Rows, 8 Blocks

ANALOG SYSTEM

Analog Block Array

Analog Ref
4 Columns, 12 Blocks

Analog Input Muxing

Digital Clocks

Multiply Accum.
For up-to-date Ordering, Packaging, and Electrical Specification information, reference the latest PSoC device data sheets on the web at

Development Kits

Development Kits are available from the following distributors Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store at contains development kits, C compilers, and all accessories for PSoC development. Click on PSoC Programmable System-on-Chip to view a current list of available items.

Tele-Training

Free PSoC "Tele-training" is available for beginners and taught by a live marketing or application engineer over the phone. Five training classes are available to accelerate the learning curve including introduction, designing, debugging, advanced design, advanced analog, as well as application-specific classes covering topics like PSoC and the LIN bus. For days and times of the tele-training, see

Consultants

Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant, go to the following Cypress support web site:

Technical Support

PSoC application engineers take pride in fast and accurate response. They can be reached with a 4-hour guaranteed response at

Application Notes

A long list of application notes will assist you in every aspect of your design effort. To locate the PSoC application notes, go to

Development Tools

The Cypress MicroSystems PSoC Designer is a Windows-based, integrated development environment for the Programmable System-on-Chip PSoC devices. The PSoC Designer IDE and application runs on Windows NT Windows 2000, Windows Millennium Me , or Windows XP. Reference the PSoC Designer Functional Flow diagram below.

PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the PSoC, and debug the application. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and the CYASM macro assembler for the CPUs.

PSoC Designer also supports a high-level C language compiler developed specifically for the devices in the family.

PSoCTM Designer

Graphical Designer Interface

Context Sensitive

Help

Commands

Results

Importable Design

Database

Device Database

Application Database

Project Database

User Modules Library

PSoCTM Designer

Core Engine

PSoC Configuration

Sheet

Manufacturing Information File

Emulation Pod

In-Circuit Emulator

Device Programmer

PSoC Designer Subsystems

August 3, 2004

CY8C27x43 Final Data Sheet

PSoC Overview

PSoC Designer Software Subsystems

Device Editor
Ordering Information 42 Ordering Code Definitions 43

Sales and Service Information 44

August 3, 2004

Pin Information

This chapter describes, lists, and illustrates the CY8C27x43 PSoC device pins and pinout configurations.

Pinouts

The CY8C27x43 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin labeled with a “P” is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.
8-Pin Part Pinout

Table 8-Pin Part Pinout PDIP

Type

No. Digital Analog Name

IO P0[5] Analog column mux input and column output.

IO P0[3] Analog column mux input and column output.

P1[1] Crystal Input XTALin , I2C Serial Clock SCL

Power

Ground connection.

P1[0]

Crystal Output XTALout , I2C Serial Data SDA

IO P0[2] Analog column mux input and column output.

IO P0[4] Analog column mux input and column output.

Power

Supply voltage.

LEGEND A = Analog, I = Input, and O = Output.

CY8C27143 8-Pin PSoC Device

AIO, P0[5] AIO, P0[3] I2C SCL, XTALin, P1[1]
2PDIP7
36 45

Vdd P0[4], AIO P0[2], AIO P1[0], XTALout, I2C SDA

August 3, 2004

CY8C27x43 Final Data Sheet
20-Pin Part Pinout

Table 20-Pin Part Pinout SSOP, SOIC

Type

No. Digital Analog Name

I P0[7] Analog column mux input.

IO P0[5] Analog column mux input and column output.

IO P0[3] Analog column mux input and column output.

I P0[1] Analog column mux input.

Power

SMP Switch Mode Pump SMP connection to
external components required.
b. Refer to the Ordering Information chapter on page

DC General Purpose IO Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges 4.75V to 5.25V and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only.

Table DC GPIO Specifications

Symbol RPU RPD VOH

Pull up Resistor Pull down Resistor High Output Level

Low Output Level

VIL VIH VH IIL CIN COUT

Input Low Level Input High Level Input Hysterisis Input Leakage Absolute Value Capacitive Load on Pins as Input Capacitive Load on Pins as Output

Min 4

Vdd -

Max 8

Units V

V mV nA pF

Notes

IOH = 10 mA, Vdd = to 5.25V 8 total loads, 4 on even port pins for example, P0[2], P1[4] , 4 on odd port pins for example, P0[3], P1[5] . IOL = 25 mA, Vdd = to 5.25V 8 total loads, 4 on even port pins for example, P0[2], P1[4] , 4 on odd port pins for example, P0[3], P1[5] . Vdd = to Vdd = to

Gross tested to 1 µA. Package and pin dependent. Temp = 25oC. Package and pin dependent. Temp = 25oC.

August 3, 2004

CY8C27x43 Final Data Sheet

Electrical Specifications

DC Operational Amplifier Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges 4.75V to 5.25V and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only.

The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 5V DC Operational Amplifier Specifications

Symbol VOSOA

TCVOSOA IEBOA CINOA VCMOA

Description Input Offset Voltage absolute value Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Average Input Offset Voltage Drift

Input Leakage Current Port 0 Analog Pins Input Capacitance Port 0 Analog Pins

Common Mode Voltage Range Common Mode Voltage Range high power or high opamp bias

CMRROA GOLOA VOHIGHOA VOLOWOA ISOA

PSRROA

Common Mode Rejection Ratio Power = Low Power = Medium Power = High Open Loop Gain Power = Low Power = Medium Power = High Output Voltage Swing internal signals Power = Low Power = Medium Power = High Low Output Voltage Swing internal signals Power = Low Power = Medium Power = High Supply Current including associated AGND buffer Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High Supply Voltage Rejection Ratio
60 80

Vdd - Vdd - Vdd -
1200
2400
4600

Units

Notes
µV/oC

Vdd -
a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz 42 ns nominal period . b. Refer to the Ordering Information chapter on page

Notes 4.75V < Vdd < 5.25V. 3.0V < Vdd < 4.75V.
4.75V < Vdd < 5.25V.
4.75V < Vdd < 5.25V.
4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V.

Maximum data rate at MHz due to 2 x over clocking.

Maximum data rate at MHz due to 8 x over clocking. Maximum data rate at MHz due to 8 x over clocking. Maximum data rate at MHz due to 8 x over clocking. Maximum data rate at MHz due to 8 x over clocking.

August 3, 2004

CY8C27x43 Final Data Sheet

Electrical Specifications

AC Analog Output Buffer Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges 4.75V to 5.25V and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only.

Table 5V AC Analog Output Buffer Specifications

Symbol TROB TSOB SRROB SRFOB BWOB

Description Rising Settling Time to 1V Step, 100pF Load

Power = Low Power = High Falling Settling Time to 1V Step, 100pF Load Power = Low Power = High Rising Slew Rate 20% to 80% , 1V Step, 100pF Load Power = Low Power = High Falling Slew Rate 80% to 20% , 1V Step, 100pF Load Power = Low Power = High Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load Power = Low Power = High Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load Power = Low Power = High

Units
µs µs
µs µs

V/µs V/µs

V/µs V/µs

Notes

Table 3.3V AC Analog Output Buffer Specifications

Symbol TROB TSOB SRROB SRFOB BWOB

Description Rising Settling Time to 1V Step, 100pF Load

Power = Low Power = High Falling Settling Time to 1V Step, 100pF Load Power = Low Power = High Rising Slew Rate 20% to 80% , 1V Step, 100pF Load Power = Low Power = High Falling Slew Rate 80% to 20% , 1V Step, 100pF Load Power = Low Power = High Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load Power = Low Power = High Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load Power = Low Power = High

Units
µs µs
µs µs

V/µs V/µs

V/µs V/µs

Notes

August 3, 2004

CY8C27x43 Final Data Sheet

Electrical Specifications

AC External Clock Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges 4.75V to 5.25V and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only.

Table 5V AC External Clock Specifications

Symbol FOSCEXT

Description Frequency High Period Low Period Power Up IMO to Switch

Min 150
Ordering Information
The following table lists the CY8C27x43 PSoC device family’s key package features and ordering codes. Table CY8C27x43 PSoC Device Family Key Features and Ordering Information

Flash Kbytes

RAM Bytes Switch Mode Pump Temperature Range Digital Blocks Rows of 4 Analog Blocks Columns of 3 Digital IO

Pins Analog Inputs Analog Outputs XRES Pin

Package
Ordering Code

CY8C27x43 Silicon B These parts are lead free and offer the following improvements. The DEC_CR1 register selections are enhanced to allow any digital block to be the decimator clock source, the ECO EX and ECO EXW bits in the CPU_SCR1 register are readable, and the accuracy of the analog reference is enhanced see the Electrical Specifications chapter . All silicon A errata are fixed in silicon B.
8 Pin 300 Mil DIP

CY8C27143-24PXI
16 256 No -40C to +85C 8
20 Pin 210 Mil SSOP

CY8C27243-24PVXI
16 256 Yes -40C to +85C 8
12 16
4 Yes
20 Pin 210 Mil SSOP Tape and Reel

CY8C27243-24PVXIT 16 256 Yes -40C to +85C 8
12 16 8
4 Yes
20 Pin 300 Mil SOIC

CY8C27243-24SXI
16 256 Yes -40C to +85C 8
12 16 8
4 Yes
20 Pin 300 Mil SOIC Tape and Reel

CY8C27243-24SXIT
16 256 Yes -40C to +85C 8
12 16 8
4 Yes
28 Pin 300 Mil DIP

CY8C27443-24PXI
16 256 Yes -40C to +85C 8
12 24 12
4 Yes
28 Pin 210 Mil SSOP

CY8C27443-24PVXI
16 256 Yes -40C to +85C 8
12 24 12
4 Yes
28 Pin 210 Mil SSOP Tape and Reel

CY8C27443-24PVXIT 16 256 Yes -40C to +85C 8
12 24 12
4 Yes
28 Pin 300 Mil SOIC

CY8C27443-24SXI
16 256 Yes -40C to +85C 8
Ordering Information
Table CY8C27x43 PSoC Device Family Key Features and Ordering Information continued

Flash Kbytes

RAM Bytes Switch Mode Pump Temperature Range Digital Blocks Rows of 4 Analog Blocks Columns of 3 Digital IO

Pins Analog Inputs Analog Outputs XRES Pin

Package
28 Pin 210 Mil SSOP Tape and Reel 28 Pin 300 Mil SOIC 28 Pin 300 Mil SOIC Tape and Reel 44 Pin TQFP 44 Pin TQFP Tape and Reel 48 Pin 300 Mil SSOP 48 Pin 300 Mil SSOP Tape and Reel 48 Pin 7x7 MLF 48 Pin 7x7 MLF Tape and Reel
Ordering Code

CY8C27443-24PVIT CY8C27443-24SI CY8C27443-24SIT CY8C27543-24AI CY8C27543-24AIT CY8C27643-24PVI CY8C27643-24PVIT CY8C27643-24LFI CY8C27643-24LFIT
16 256 Yes -40C to +85C 8 16 256 Yes -40C to +85C 8 16 256 Yes -40C to +85C 8 16 256 Yes -40C to +85C 8 16 256 Yes -40C to +85C 8 16 256 Yes -40C to +85C 8 16 256 Yes -40C to +85C 8 16 256 Yes -40C to +85C 8 16 256 Yes -40C to +85C 8
12 24 12 24 12 24 12 40 12 40 12 44 12 44 12 44 12 44 12
4 Yes 4 Yes 4 Yes 4 Yes 4 Yes 4 Yes 4 Yes 4 Yes 4 Yes
Ordering Code Definitions

CY 8 C 27 xxx-SPxx

Package Type P = PDIP S = SOIC PV = SSOP LF = MLF A = TQFP

PX = PDIP Pb Free SX = SOIC Pb Free PVX = SSOP Pb Free LFX = MLF Pb Free AX = TQFP Pb Free

Speed 24 MHz

Family Code

Technology Code C = CMOS

Marketing Code 8 = Cypress MicroSystems

Company ID CY = Cypress

Thermal Rating C = Commercial I = Industrial E = Extended

August 3, 2004

Sales and Service Information

To obtain information about Cypress MicroSystems or PSoC sales and technical support, reference the following information or go to the section titled “Getting Started” on page 4 in this document.

Cypress MicroSystems
2700 162nd Street SW

Building D

Lynnwood, WA 98037

Phone:

Facsimile:

Web Sites:

Company Information Sales

Technical Support

Document Title:

CY8C27143, CY8C27243, CY8C27443, CY8C27543, and CY8C27643 PSoC Mixed Signal Array Final Data Sheet

Document Number 38-12012

ECN # Issue Date Origin of Change

Description of Change
127087
7/01/2003 New Silicon.
128780
7/29/2003 Engineering and

New electrical spec additions, fix of Core Architecture links, corrections to some text, tables, draw-

NWJ.
ings, and format.
128992
8/14/2003 NWJ

Interrupt controller table fixed, refinements to Electrical Spec section and Register chapter.
129283
8/28/2003 NWJ

Significant changes to the Electrical Specifications section.
129442

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY8C27643-24PVIT Datasheet file may be downloaded here without warranties.

Datasheet ID: CY8C27643-24PVIT 508163