CY8C24033-24PVXI

CY8C24033-24PVXI Datasheet

CY8C24633

Part	Datasheet
CY8C24033-24PVXI	CY8C24033-24PVXI (pdf)

PDF Datasheet Preview
CY8C24633 Programmable System-on-Chip • Powerful Harvard Architecture Processor M8C Processor Speeds to 24 MHz 8x8 Multiply, 32-Bit Accumulate Low Power at High Speed to 5.25V Operating Voltage Industrial Temperature Range -40°C to +85°C • Advanced Peripherals Blocks 4 Rail-to-Rail Analog PSoC Blocks Provide • Up to 14-Bit ADCs • Up to 8-Bit DACs • Programmable Gain Amplifiers • Programmable Filters and Comparators 4 Digital PSoC Blocks Provide • 8 to 32-Bit Timers, Counters, and PWMs • CRC and PRS Modules • Full-Duplex UART • Multiple SPI Masters or Slaves • Connectable to all GPIO Pins Complex Peripherals by Combining Blocks High speed 8-bit SAR ADC optimized for motor control • Precision, Programmable Clocking Internal ±5% 24/48 MHz Oscillator High Accuracy 24 MHz with Optional 32 kHz Crystal and PLL Optional External Oscillator, up to 24 MHz Internal Oscillator for Watchdog and Sleep • Flexible On-Chip Memory 8K Bytes Flash Program Storage 50,000 Erase/Write Cycles 256 Bytes SRAM Data Storage In-System Serial Programming ISSP Partial Flash Updates Flexible Protection Modes EEPROM Emulation in Flash • Programmable Pin Configurations 25 mA Sink on all GPIO Pull Up, Pull Down, High Z, Strong, or Open Drain Drive Modes on all GPIO Up to 10 Analog Inputs on GPIO Two 30 mA Analog Outputs on GPIO Configurable Interrupt on all GPIO • Additional System Resources I2C Slave, Master, and Multi-Master to 400 kHz Watchdog and Sleep Timers User-Configurable Low Voltage Detection Integrated Supervisory Circuit On-Chip Precision Voltage Reference • Complete Development Tools Free development Software PSoC Designer Full-Featured In-Circuit Emulator and Programmer Full Speed Emulation Complex Breakpoint Structure 128K Bytes Trace Memory • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Block Diagram PSoC CORE Port 3 Port 2 Port 1 Port 0 Analog Drivers System Bus Global Digital Interconnect Global Analog Interconnect SRAM 256 Bytes Interrupt Controller SROM Flash 8K CPUCore M 8C Sleep and Watchdog Multiple ClockSources Includes IMO, ILO, PLL, and ECO DIGITAL SYSTEM Digital Block Array 1 Row 4 Blocks ANALOG SYSTEM Analog Block Array 2 Columns 4 Blocks SAR8 ADC Analog Ref Analog Input Muxing Digital Clocks Multiply Accum Decim ator POR and LVD System Resets Internal Voltage Ordering 36 Document History Page 37 Sales, Solutions, and Legal Information 38 Worldwide Sales and Design Support....................... 38 Products 38 Solutions 38 Page 3 of 38 [+] Feedback CY8C24633 PSoC Functional Overview The PSoC family consists of many programmable system-on-chip with on-chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one, low cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, as well as programmable interconnects. This architecture allows the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts and packages. The PSoC architecture, as illustrated in the Block Diagram, is comprised of four main areas PSoC Core, Digital System, Analog System, and System Resources. Configurable global buses allows all the device resources to be combined into a complete custom system. The PSoC CY8C24x33 family can have up to three I/O ports that connect to the global digital and analog interconnects, providing access to four digital blocks and four analog blocks. The PSoC Core The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO General Purpose I/O . The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU utilizes an interrupt controller with 11 vectors, to simplify programming of real time embedded events. Program execution is timed and protected using the included Sleep and Watch Dog Timers WDT . Memory encompasses 8 KB of Flash for program storage, 256 bytes of SRAM for data storage, and up to 2 KB of EEPROM emulated using the Flash. Program Flash uses four protection levels on blocks of 64 bytes, allowing customized software IP protection. The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO internal main oscillator accurate to ±5% over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz ILO internal low speed oscillator is provided for the Sleep timer and WDT. If crystal accuracy is desired, the ECO kHz external crystal oscillator is available for use as a Real Time Clock RTC and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers as a System Resource , provide the flexibility to integrate almost any timing requirement into the PSoC device. PSoC GPIOs provide connection to the CPU, digital and analog resources of the device. Each pin’s drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read. The Digital System The Digital System is composed of four digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Figure Digital System Block Diagram Port 3 Port 2 Port 1 Port 0 DigitalClocks To System Bus FromCore ToAnalog System DIGITAL SYSTEM Digital PSoC Block Array Row 0 DBB00 DBB01 DCB02 DCB03 4 Row Input Configuration Row Output Configuration GIE[7:0] GIO[7:0] Global Digital Interconnect GOE[7:0] GOO[7:0] Digital peripheral configurations include those listed below. • PWMs 8 to 32 bit • PWMs with Dead Band 8 to 32 bit • Counters 8 to 32 bit • Timers 8 to 32 bit • UART 8 bit with selectable parity up to 1 • SPI master and slave up to 1 For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device data sheets on the web at Application Notes Application notes are an excellent introduction to the wide variety of possible PSoC designs. They are located here Select Application Notes under the Documentation tab. Development Kits PSoC Development Kits are available online from Cypress at and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. Training Free PSoC technical training on demand, webinars, and workshops is available online at The training covers a wide variety of topics and skill levels to assist you in your designs. CYPros Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to Solutions Library Visit our growing library of solution focused designs at Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. Technical Support For assistance with technical issues, search KnowledgeBase articles and forums at If you cannot find an answer to your question, call technical support at Notes Limited analog functionality. Two analog blocks and one Page 6 of 38 [+] Feedback CY8C24633 Development Tools PSoC Designer is a Windows-based, integrated development environment for the Programmable System-on-Chip PSoC devices. The PSoC Designer IDE runs on Windows XP or Windows Vista. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and built-in support for third-party assemblers and C compilers. PSoC Designer also supports C language compilers developed specifically for the devices in the PSoC family. PSoC Designer Software Subsystems System-Level View A drag-and-drop visual embedded system design environment based on PSoC Express. In the system level view you create a model of your system inputs, outputs, and communication interfaces. You define when and how an output device changes state based upon any or all other system devices. Based upon the design, PSoC Designer automatically selects one or more PSoC On-Chip Controllers that match your system requirements. PSoC Designer generates all embedded code, then compiles and links it into a programming file for a specific PSoC device. Chip-Level View The chip-level view is a more traditional integrated development environment IDE based on PSoC Designer Choose a base device to work with and then select different onboard analog and digital components called user modules that use the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time. Hybrid Designs You can begin in the system-level view, allow it to choose and configure your user modules, routing, and generate code, then switch to the chip-level view to gain complete control over on-chip resources. All views of the project share a common code editor, builder, and common debug, emulation, and programming tools. Code Generation Tools PSoC Designer supports multiple third party C compilers and assemblers. The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. The choice is yours. Assemblers. The assemblers allow assembly code to merge seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all the features of C tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write I/O registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. Ordering Information The following table lists the CY8C24633 PSoC device family key package features and ordering codes. Table CY8C24x33 PSoC Device Family Key Features and Ordering Information Flash Kbytes RAM Bytes Temperature Range Digital Blocks Rows of 4 Analog Blocks Columns of 3 Digital I/O Pins Analog Inputs Analog Outputs XRES Pin Package Ordering Code 28-Pin 210 Mil SSOP 28-Pin 210 Mil SSOP Tape and Reel 56-Pin OCD SSOP CY8C24633-24PVXI CY8C24633-24PVXIT CY8C24033-24PVXI[23] 8 256 -40oC to +85oC 4 8 256 -40oC to +85oC 4 8 256 -40oC to +85oC 4 4 25 12 2 Yes 4 25 12 2 Yes 4 24 12 2 Yes Notes TJ = TA + POWER x Higher temperatures required based solder melting point. Typical temperatures solder with Sn-Pb with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications. This part may be used for in-circuit debugging. It is NOT available for production. Page 36 of 38 [+] Feedback CY8C24633 Document History Page Document Title CY8C24633 Programmable-System-on-Chip Document Number 001-20160 ECN No. Orig. of Change Submission Date Description of Change ** 1411003 HMT See ECN New spec. Separate device from A 1648723 HMT See ECN Update SAR ADC electrical specs. Update INL, DNL, and VOL specs. Finetune specs. Add 56 SSOP package capacitance data. Change title. Make data sheet Final. B 2763970 POA/AESA 09/16/2009 Update Getting Started, Development Tools, and Designing with PSoC Designer sections. *C 2871212 JHU/HMT 02/04/2010 • Add Table of Contents. • Update DC GPIO, AC Chip-Level, and AC Programming Specifications as follows:

PDF Datasheet Preview

CY8C24633

Programmable System-on-Chip
• Powerful Harvard Architecture Processor M8C Processor Speeds to 24 MHz 8x8 Multiply, 32-Bit Accumulate Low Power at High Speed to 5.25V Operating Voltage Industrial Temperature Range -40°C to +85°C
• Advanced Peripherals Blocks 4 Rail-to-Rail Analog PSoC Blocks Provide
• Up to 14-Bit ADCs
• Up to 8-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators 4 Digital PSoC Blocks Provide
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Full-Duplex UART
• Multiple SPI Masters or Slaves
• Connectable to all GPIO Pins Complex Peripherals by Combining Blocks High speed 8-bit SAR ADC optimized for motor control
• Precision, Programmable Clocking Internal ±5% 24/48 MHz Oscillator High Accuracy 24 MHz with Optional 32 kHz Crystal and PLL Optional External Oscillator, up to 24 MHz Internal Oscillator for Watchdog and Sleep
• Flexible On-Chip Memory 8K Bytes Flash Program Storage 50,000 Erase/Write Cycles 256 Bytes SRAM Data Storage In-System Serial Programming ISSP Partial Flash Updates Flexible Protection Modes EEPROM Emulation in Flash
• Programmable Pin Configurations 25 mA Sink on all GPIO Pull Up, Pull Down, High Z, Strong, or Open Drain Drive Modes on all GPIO Up to 10 Analog Inputs on GPIO Two 30 mA Analog Outputs on GPIO Configurable Interrupt on all GPIO
• Additional System Resources I2C Slave, Master, and Multi-Master to 400 kHz Watchdog and Sleep Timers User-Configurable Low Voltage Detection Integrated Supervisory Circuit On-Chip Precision Voltage Reference
• Complete Development Tools Free development Software PSoC Designer Full-Featured In-Circuit Emulator and Programmer Full Speed Emulation Complex Breakpoint Structure 128K Bytes Trace Memory
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

Block Diagram

PSoC CORE

Port 3

Port 2

Port 1

Port 0

Analog Drivers

System Bus

Global Digital Interconnect

Global Analog Interconnect

SRAM 256 Bytes

Interrupt Controller

SROM Flash 8K

CPUCore M 8C

Sleep and Watchdog

Multiple ClockSources Includes IMO, ILO, PLL, and ECO

DIGITAL SYSTEM

Digital Block Array
1 Row 4 Blocks

ANALOG SYSTEM

Analog Block Array
2 Columns 4 Blocks

SAR8 ADC

Analog Ref

Analog Input Muxing

Digital Clocks

Multiply Accum

Decim ator

POR and LVD System Resets

Internal Voltage
Ordering 36 Document History Page 37 Sales, Solutions, and Legal Information 38

Worldwide Sales and Design Support....................... 38 Products 38 Solutions 38

Page 3 of 38 [+] Feedback

CY8C24633

PSoC Functional Overview

The PSoC family consists of many programmable system-on-chip with on-chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one, low cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, as well as programmable interconnects. This architecture allows the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts and packages.

The PSoC architecture, as illustrated in the Block Diagram, is comprised of four main areas PSoC Core, Digital System, Analog System, and System Resources. Configurable global buses allows all the device resources to be combined into a complete custom system. The PSoC CY8C24x33 family can have up to three I/O ports that connect to the global digital and analog interconnects, providing access to four digital blocks and four analog blocks.

The PSoC Core

The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO General Purpose I/O .

The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU utilizes an interrupt controller with 11 vectors, to simplify programming of real time embedded events. Program execution is timed and protected using the included Sleep and Watch Dog Timers WDT .

Memory encompasses 8 KB of Flash for program storage, 256 bytes of SRAM for data storage, and up to 2 KB of EEPROM emulated using the Flash. Program Flash uses four protection levels on blocks of 64 bytes, allowing customized software IP protection.

The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO internal main oscillator accurate to ±5% over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz ILO internal low speed oscillator is provided for the Sleep timer and WDT. If crystal accuracy is desired, the ECO kHz external crystal oscillator is available for use as a Real Time Clock RTC and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers as a System Resource , provide the flexibility to integrate almost any timing requirement into the PSoC device.

PSoC GPIOs provide connection to the CPU, digital and analog resources of the device. Each pin’s drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read.

The Digital System

The Digital System is composed of four digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references.

Figure Digital System Block Diagram

Port 3

Port 2

Port 1

Port 0

DigitalClocks To System Bus FromCore

ToAnalog System

DIGITAL SYSTEM

Digital PSoC Block Array

Row 0

DBB00

DBB01

DCB02

DCB03 4

Row Input Configuration

Row Output Configuration

GIE[7:0] GIO[7:0]

Global Digital Interconnect

GOE[7:0] GOO[7:0]

Digital peripheral configurations include those listed below.
• PWMs 8 to 32 bit
• PWMs with Dead Band 8 to 32 bit
• Counters 8 to 32 bit
• Timers 8 to 32 bit
• UART 8 bit with selectable parity up to 1
• SPI master and slave up to 1
For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device data sheets on the web at

Application Notes

Application notes are an excellent introduction to the wide variety of possible PSoC designs. They are located here Select Application Notes under the Documentation tab.

Development Kits

PSoC Development Kits are available online from Cypress at and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark.

Training

Free PSoC technical training on demand, webinars, and workshops is available online at The
training covers a wide variety of topics and skill levels to assist you in your designs.

CYPros Consultants

Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to

Solutions Library

Visit our growing library of solution focused designs at Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly.

Technical Support

For assistance with technical issues, search KnowledgeBase articles and forums at If you cannot find an answer to your question, call technical support at

Notes

Limited analog functionality.

Two analog blocks and one

Page 6 of 38 [+] Feedback

CY8C24633

Development Tools

PSoC Designer is a Windows-based, integrated development environment for the Programmable System-on-Chip PSoC devices. The PSoC Designer IDE runs on Windows XP or Windows Vista.

This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and built-in support for third-party assemblers and C compilers.

PSoC Designer also supports C language compilers developed specifically for the devices in the PSoC family.

PSoC Designer Software Subsystems

System-Level View

A drag-and-drop visual embedded system design environment based on PSoC Express. In the system level view you create a model of your system inputs, outputs, and communication interfaces. You define when and how an output device changes state based upon any or all other system devices. Based upon the design, PSoC Designer automatically selects one or more PSoC On-Chip Controllers that match your system requirements.

PSoC Designer generates all embedded code, then compiles and links it into a programming file for a specific PSoC device.

Chip-Level View

The chip-level view is a more traditional integrated development environment IDE based on PSoC Designer Choose a base device to work with and then select different onboard analog and digital components called user modules that use the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application.

The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time.

Hybrid Designs

You can begin in the system-level view, allow it to choose and configure your user modules, routing, and generate code, then switch to the chip-level view to gain complete control over on-chip resources. All views of the project share a common code editor, builder, and common debug, emulation, and programming tools.

Code Generation Tools

PSoC Designer supports multiple third party C compilers and assemblers. The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. The choice is yours.

Assemblers. The assemblers allow assembly code to merge seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing.

C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices.

The optimizing C compilers provide all the features of C tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality.

Debugger

The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write I/O registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest.

Online Help System

The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started.
Ordering Information
The following table lists the CY8C24633 PSoC device family key package features and ordering codes.
Table CY8C24x33 PSoC Device Family Key Features and Ordering Information

Flash Kbytes

RAM Bytes Temperature Range Digital Blocks Rows of 4 Analog Blocks Columns of 3 Digital I/O Pins Analog Inputs Analog Outputs XRES Pin

Package
Ordering Code
28-Pin 210 Mil SSOP
28-Pin 210 Mil SSOP Tape and Reel
56-Pin OCD SSOP

CY8C24633-24PVXI CY8C24633-24PVXIT

CY8C24033-24PVXI[23]
8 256 -40oC to +85oC 4 8 256 -40oC to +85oC 4
8 256 -40oC to +85oC 4
4 25 12 2 Yes 4 25 12 2 Yes
4 24 12 2 Yes

Notes

TJ = TA + POWER x Higher temperatures
required
based
solder
melting
point.

Typical
temperatures
solder
with

Sn-Pb
with

Sn-Ag-Cu
paste. Refer to the solder manufacturer specifications.

This part may be used for in-circuit debugging. It is NOT available for production.

Page 36 of 38
[+] Feedback

CY8C24633

Document History Page

Document Title CY8C24633 Programmable-System-on-Chip Document Number 001-20160

ECN No.

Orig. of Change

Submission Date

Description of Change
** 1411003 HMT

See ECN New spec. Separate device from
*A 1648723 HMT

See ECN Update SAR ADC electrical specs. Update INL, DNL, and VOL specs. Finetune specs. Add 56 SSOP package capacitance data. Change title. Make data sheet Final.
*B 2763970 POA/AESA 09/16/2009 Update Getting Started, Development Tools, and Designing with PSoC Designer sections.
*C 2871212 JHU/HMT 02/04/2010
• Add Table of Contents.
• Update DC GPIO, AC Chip-Level, and AC Programming Specifications as follows:

More datasheets: 44228 | 8314S | 8374 | 8312S | 8394 | 8398 | DZT658-13 | BCM84848A1KFSBG | FQPF9N15 | DFR0329

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY8C24033-24PVXI Datasheet file may be downloaded here without warranties.

Datasheet ID: CY8C24033-24PVXI 508156