CY7C68001-56LFXC

CY7C68001-56LFXC Datasheet

CY7C68001

Part	Datasheet
CY7C68001-56LFXC	CY7C68001-56LFXC (pdf)

Related Parts	Information
CY3682	CY3682

PDF Datasheet Preview
CY7C68001 EZ-USB SX2 High Speed USB Interface Device • USB 2.0-Certified Compliant On the USB-IF Integrators List Test ID Number 40000713 • Operates at High 480 Mbps or Full 12 Mbps Speed • Supports Control Endpoint 0 Used for handling USB device requests • Supports Four Configurable Endpoints that share a 4-KB FIFO Space Endpoints 2, 4, 6, 8 for application-specific control and data • Standard 8- or 16-bit External Master Interface Glueless interface to most standard microprocessors DSPs, ASICs, and FPGAs Synchronous or Asynchronous interface • Integrated Phase-locked Loop PLL • 3.3V Operation, 5V Tolerant I/Os • 56-pin SSOP and QFN Package • Complies with most Device Class Specifications • DSL modems • ATA interface • Memory card readers • Legacy conversion devices • Cameras • Scanners • Home PNA • Wireless LAN • MP3 players • Networking • Printers The “Reference Designs” section of the Cypress web site, provides additional tools for typical USB applications. Each reference design comes complete with firmware source code and object code, schematics, and documentation. Logic Block Diagram SCL SDA 24 MHz XTAL DPLUS DMINUS VCC 1.5K USB XCVR RESET# WAKEUP* I2C Bus Controller Master Only SX2 Internal Logic IFCLK* Read, Write, OE, PKTEND, CS# Interrupt#, Ready Flags 3/4 Address 3 Control CY Smart USB FS/HS Engine 4 KB FIFO Data FIFO Data Bus 8/16-Bit Data • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7C68001 Introduction The EZ-USB SX2 USB interface device is designed to work with any external master, such as standard microprocessors, DSPs, ASICs, and FPGAs to enable USB support for any peripheral design. SX2 has a built in USB transceiver and Serial Interface Engine SIE , along with a command decoder for sending and receiving USB data. The controller has four endpoints that share a 4 KB FIFO space for maximum flexibility and throughput, and Control Endpoint SX2 has three address pins and a selectable 8- or 16- bit data bus for command and data input or output. Figure Example USB System Diagram W indows/USB Capable Host USB Cable USB Connection Cypress SX2 Device CPU EEPROM R A M /R O M A p lic a tio n Functional Overview Ordering Information Ordering Code CY7C68001-56PVC CY7C68001-56LFC CY7C68001-56PVXC CY7C68001-56LFXC CY3682 CY7C68001-56LTXC Package Type 56 SSOP 56 QFN 56 SSOP, Pb-free 56 QFN, Pb-free EZ-USB SX2 Development Kit 56 QFN, Pb-free Package Diagrams Figure 56-Pin Shrunk Small Outline Package 056 CY7C68001 51-85062-C Page 41 of 45 [+] Feedback Figure 56-Pin QFN 8X8 mm CY7C68001 Figure 56-Pin Sawn QFN 8X8X1.00 mm 51-85144 G 51-85187 D Page 42 of 45 [+] Feedback CY7C68001 Document History Page Description Title CY7C68001 EZ-USB SX2 High Speed USB Interface Device Document Number 38-08013 Submission Date Origin of Change Description of Change * 111807 06/07/02 BHA New Data Sheet A 123155 02/07/03 Minor clean-up and clarification Removed references to IRQ Register and replaced them with references to Interrupt Status Byte Modified pin-out description for XTALIN and XTALOUT Added CS# timing to Figure , Figure , and Figure Changed Command Protocol example to IFCONFIG 0x01 Edited PCB Layout Recommendations Added AR#10691 Added USB high speed logo B 126324 07/02/03 Default state of registers specified in section where the register bits are defined Reorganized timing diagram presentation First all timing related to synchronous interface, followed by timing related to asynchronous interface, followed by timing diagrams common to both interfaces Provided further information in section regarding boot methods Provided timing diagram that encapsulates ALL relevant signals for a synchronous and asynchronous slave read and write interface Added section on QFN Package Design Notes FIFOADR[2:0] Hold Time tFAH for Asynchronous FIFO Interface has been updated as follows SLRD/PKTEND to FIFOADR[2:0] Hold Time 20 ns SLWR to FIFOADR[2:0] Hold Time:70 ns recommended Added information on the polarity of the programmable flag Fixed the Command Synchronous Write Timing Diagram Fixed the Command Asynchronous Write Timing Diagram Added information on the delay required when endpoint configuration registers are changed after SX2 has already enumerated C 129463 10/07/03 Added Test ID for the USB Compliance Test Added information on the fact that the SX2 does not automatically respond to Set/Clear Feature Endpoint Stall request, external master intervention required Added information on accessing undocumented register which are not indexed for resetting data toggle Added information on requirement of clock stability before releasing reset Added information on configuration of PF register for full speed Updated confirmed timing on FIFOADR[2:0] Hold Time tFAH for Asynchronous FIFO Interface has been updated Corrected the default bit settings of EPxxFLAGS register Added information on how to change SLWR/SLRD/SLOE polarities Added further information on buffering interrupt on initiation of a command read request Change the default state of the FNADDR to 0x00 Added further labels on the sequence diagram for synchronous and asynchronous read and write in single and burst mode Added information on the maximum delay allowed between each descriptor byte write once a command write request to register 0x30 has been initiated by the external master Page 43 of 45 [+] Feedback CY7C68001 Description Title CY7C68001 EZ-USB SX2 High Speed USB Interface Device Document Number 38-08013 D 130447 12/17/03 E 243316 See ECN Reformatted data sheet to latest format Added Lead-free parts numbers Updated default value for address 0x07 and 0x09 Added Footnote Removed requirement of less then 360 nsec period between nibble writes in command Changed PKTEND to FLAGS output propagation delay in table 11-16 from a max value of 70 ns to 110 ns F 329238 See ECN Provided additional timing restrictions and requirement regarding the use of PKTEND pin to commit a short one byte/word packet subsequent to committing a packet automatically when in auto mode Miscellaneous grammar corrections. Added section header. Fixed command sequence step 3 to say register value instead of High Byte of Register Address upper and lower nibble in two places . Removed statement that programmable flag polarity is set to active low and cannot be altered. Programmable flag relies on DECIS bit settings. Updated Amkor application note URL. Changed TXINT in Figure 11-3 to be from deassertion edge of SLRD. Changed TRDY in Figure 11-4 to be from deassertion edge of SLWR. Changed FLAGS Interrupt from empty to not-empty to both empty to not-empty and from not-empty to empty conditions for triggering this interrupt. G 392570 See ECN Modified Figure to fit across columns. It was getting cropped in half. Changed corporate address to 198 Champion Court. H 411515 See ECN Added information in section USB Signaling Speed on page 2 on Full Speed only enumeration. I 2665531 02/26/2009 DPT/PYRS Added package diagram 51-85187 and updated Ordering Information table. Updated template J 2733374 07/08/2009 ANTG/AESA Updated cross-references on pages 2 and 3 Updated section numbers Page 44 of 45 [+] Feedback CY7C68001 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General psoc.cypress.com/solutions Low Power/Low Voltage psoc.cypress.com/low-power Precision Analog psoc.cypress.com/precision-analog LCD Drive psoc.cypress.com/lcd-drive CAN 2.0b psoc.cypress.com/can psoc.cypress.com/usb Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 45 of 45 PSoC Designer is a trademark and is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback

PDF Datasheet Preview

CY7C68001

EZ-USB SX2 High Speed USB Interface Device
• USB 2.0-Certified Compliant On the USB-IF Integrators List Test ID Number 40000713
• Operates at High 480 Mbps or Full 12 Mbps Speed
• Supports Control Endpoint 0 Used for handling USB device requests
• Supports Four Configurable Endpoints that share a 4-KB FIFO Space Endpoints 2, 4, 6, 8 for application-specific control and data
• Standard 8- or 16-bit External Master Interface Glueless interface to most standard microprocessors DSPs, ASICs, and FPGAs Synchronous or Asynchronous interface
• Integrated Phase-locked Loop PLL
• 3.3V Operation, 5V Tolerant I/Os
• 56-pin SSOP and QFN Package
• Complies with most Device Class Specifications
• DSL modems
• ATA interface
• Memory card readers
• Legacy conversion devices
• Cameras
• Scanners
• Home PNA
• Wireless LAN
• MP3 players
• Networking
• Printers The “Reference Designs” section of the Cypress web site, provides additional tools for typical USB applications. Each reference design comes complete with firmware source code and object code, schematics, and documentation.

Logic Block Diagram

SCL SDA
24 MHz XTAL

DPLUS DMINUS

VCC 1.5K USB XCVR

RESET# WAKEUP*

I2C Bus Controller Master Only

SX2 Internal Logic

IFCLK* Read*, Write*, OE*, PKTEND*, CS#

Interrupt#, Ready

Flags 3/4 Address 3 Control

CY Smart USB FS/HS Engine
4 KB FIFO

Data

FIFO Data Bus
8/16-Bit Data
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY7C68001

Introduction

The EZ-USB SX2 USB interface device is designed to work with any external master, such as standard microprocessors, DSPs, ASICs, and FPGAs to enable USB support for any peripheral design. SX2 has a built in USB transceiver and Serial Interface Engine SIE , along with a command decoder for sending and receiving USB data. The controller has four endpoints that share a 4 KB FIFO space for maximum flexibility and throughput, and Control Endpoint SX2 has three address pins and a selectable 8- or 16- bit data bus for command and data input or output.

Figure Example USB System Diagram

W indows/USB Capable Host

USB Cable USB Connection

Cypress SX2

Device CPU

EEPROM R A M /R O M

A p lic a tio n

Functional Overview
Ordering Information
Ordering Code CY7C68001-56PVC CY7C68001-56LFC CY7C68001-56PVXC CY7C68001-56LFXC CY3682 CY7C68001-56LTXC

Package Type 56 SSOP 56 QFN 56 SSOP, Pb-free 56 QFN, Pb-free EZ-USB SX2 Development Kit 56 QFN, Pb-free

Package Diagrams

Figure 56-Pin Shrunk Small Outline Package 056

CY7C68001
51-85062-*C

Page 41 of 45 [+] Feedback

Figure 56-Pin QFN 8X8 mm

CY7C68001

Figure 56-Pin Sawn QFN 8X8X1.00 mm
51-85144 *G
51-85187 *D

Page 42 of 45 [+] Feedback

CY7C68001

Document History Page

Description Title CY7C68001 EZ-USB SX2 High Speed USB Interface Device Document Number 38-08013

Submission Date

Origin of Change

Description of Change
** 111807 06/07/02

BHA New Data Sheet
*A 123155 02/07/03

Minor clean-up and clarification Removed references to IRQ Register and replaced them with references to Interrupt Status Byte Modified pin-out description for XTALIN and XTALOUT Added CS# timing to Figure , Figure , and Figure Changed Command Protocol example to IFCONFIG 0x01 Edited PCB Layout Recommendations Added AR#10691 Added USB high speed logo
*B 126324 07/02/03

Default state of registers specified in section where the register bits are defined Reorganized timing diagram presentation First all timing related to synchronous interface, followed by timing related to asynchronous interface, followed by timing diagrams common to both interfaces Provided further information in section regarding boot methods Provided timing diagram that encapsulates ALL relevant signals for a synchronous and asynchronous slave read and write interface Added section on QFN Package Design Notes FIFOADR[2:0] Hold Time tFAH for Asynchronous FIFO Interface has been updated as follows SLRD/PKTEND to FIFOADR[2:0] Hold Time 20 ns SLWR to FIFOADR[2:0] Hold Time:70 ns recommended Added information on the polarity of the programmable flag Fixed the Command Synchronous Write Timing Diagram Fixed the Command Asynchronous Write Timing Diagram Added information on the delay required when endpoint configuration registers are changed after SX2 has already enumerated
*C 129463 10/07/03

Added Test ID for the USB Compliance Test Added information on the fact that the SX2 does not automatically respond to Set/Clear Feature Endpoint Stall request, external master intervention required Added information on accessing undocumented register which are not indexed for resetting data toggle Added information on requirement of clock stability before releasing reset Added information on configuration of PF register for full speed Updated confirmed timing on FIFOADR[2:0] Hold Time tFAH for Asynchronous FIFO Interface has been updated Corrected the default bit settings of EPxxFLAGS register Added information on how to change SLWR/SLRD/SLOE polarities Added further information on buffering interrupt on initiation of a command read request Change the default state of the FNADDR to 0x00 Added further labels on the sequence diagram for synchronous and asynchronous read and write in single and burst mode Added information on the maximum delay allowed between each descriptor byte write once a command write request to register 0x30 has been initiated by the external master

Page 43 of 45 [+] Feedback

CY7C68001

Description Title CY7C68001 EZ-USB SX2 High Speed USB Interface Device Document Number 38-08013
*D 130447 12/17/03 *E 243316 See ECN

Reformatted data sheet to latest format Added Lead-free parts numbers Updated default value for address 0x07 and 0x09 Added Footnote Removed requirement of less then 360 nsec period between nibble writes in command Changed PKTEND to FLAGS output propagation delay in table 11-16 from a max value of 70 ns to 110 ns
*F 329238 See ECN

Provided additional timing restrictions and requirement regarding the use of PKTEND pin to commit a short one byte/word packet subsequent to committing a packet automatically when in auto mode Miscellaneous grammar corrections. Added section header. Fixed command sequence step 3 to say register value instead of High Byte of Register Address upper and lower nibble in two places . Removed statement that programmable flag polarity is set to active low and cannot be altered. Programmable flag relies on DECIS bit settings. Updated Amkor application note URL. Changed TXINT in Figure 11-3 to be from deassertion edge of SLRD. Changed TRDY in Figure 11-4 to be from deassertion edge of SLWR. Changed FLAGS Interrupt from empty to not-empty to both empty to not-empty and from not-empty to empty conditions for triggering this interrupt.
*G 392570 See ECN

Modified Figure to fit across columns. It was getting cropped in half. Changed corporate address to 198 Champion Court.
*H 411515 See ECN

Added information in section USB Signaling Speed on page 2 on Full Speed only enumeration.
*I 2665531 02/26/2009 DPT/PYRS Added package diagram 51-85187 and updated Ordering Information table. Updated template
*J 2733374 07/08/2009 ANTG/AESA Updated cross-references on pages 2 and 3 Updated section numbers

Page 44 of 45 [+] Feedback

CY7C68001

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products PSoC Clocks & Buffers Wireless Memories Image Sensors
psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com

PSoC Solutions

General
psoc.cypress.com/solutions

Low Power/Low Voltage
psoc.cypress.com/low-power

Precision Analog
psoc.cypress.com/precision-analog

LCD Drive
psoc.cypress.com/lcd-drive

CAN 2.0b
psoc.cypress.com/can
psoc.cypress.com/usb

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 45 of 45

PSoC Designer is a trademark and is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

All products and company names mentioned in this document may be the trademarks of their respective holders.
[+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C68001-56LFXC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C68001-56LFXC 508139