CY7C65640A-LFXCT

CY7C65640A-LFXCT Datasheet

CY7C65640A

Part	Datasheet
CY7C65640A-LFXCT	CY7C65640A-LFXCT (pdf)

Related Parts	Information
CY7C65640A-LFXC	CY7C65640A-LFXC

PDF Datasheet Preview
CY7C65640A TetraHub High Speed USB Hub Controller • USB hub • Four downstream ports • Multiple transaction translators - one per downstream port for maximum performance • VID, PID, and DID configured from external SPI EEPROM • 24 MHz external crystal • Small package - Quad Flat Pack, no leads QFN • Integrated upstream pull up resistor • Integrated downstream pull down resistors for all downstream ports Logic Block Diagram 24 MHz Crystal USB PHY PLL USB Upstream • Integrated upstream and downstream series termination resistors • Configurable with external SPI EEPROM Number of Active Ports Number of Removable Ports Maximum Power Hub Controller Power-On Timer Overcurrent Timer Disable Overcurrent Timer Enable Full Speed Only Disable Port Indicators Gang Power Switching Enable Single TT Mode Only Enable NoEOPatEOF1 Serial Interface Engine High speed USB Control Logic SPI Communication Block SPI_SCK SPI_SD SPI_CS Hub Repeater Transaction Translator X4 TT RAM Routing Logic USB Downstream USB Port Pow- Port er Control Sta- USB Downstream USB Port Pow- Port er Control Sta- USB Downstream USB Port Pow- Port er Control Sta- USB Downstream USB Port Pow- Port er Control Sta- D+ PWR#[1 OVR#[1LED D+ PWR#[2 OVR#[2LED D+ PWR#[3 OVR#[3LED D+ PWR#[4 OVR#[4LED • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7C65640A Introduction Cypress’s TetraHub is a high-performance self-powered Universal Serial Bus USB hub. The Tetra architecture provides four downstream USB ports, with a Transaction Translator TT for each port, making it the highest-performance hub possible. This single-chip device incorporates one upstream and four downstream USB transceivers, a Serial Interface Engine SIE , USB Hub Controller and Repeater, and four TTs. It is suitable for standalone hubs, motherboard hubs, and monitor hub applications. Being a fixed-function USB device, there is no risk or added engineering effort required for firmware development. The developer does not need to write any firmware for their design. The CY4602 Tetrahub USB 4-port Hub Reference Design Kit provides all materials and documents needed to move rapidly into production. The reference design kit includes board schematics, bill of materials, Gerber files, Orcad files, key application notes, and product description. TetraHub Architecture The Logic Block Diagram on page 1 shows the TetraHub Architecture. USB Serial Interface Engine SIE The SIE allows the CY7C65640A to communicate with the USB host through the USB repeater component of the hub. The SIE handles the following USB bus activity independently of the Hub Control Block: Ordering Information Ordering Code CY7C65640A-LFXC CY7C65640A-LTXC CY7C65640A-LTXCT CY4602 Package Type 56-pin QFN Pb-free Package 56-pin QFN Sawn type 56-pin QFN Sawn type TetraHub USB 4 port Hub Reference Design Kit Package Diagram The TetraHub is available in a space-saving 56-pin QFN 8 x 8 mm Figure 56-Pin QFN 8 x 8 MM LF56A 51-85144 G Page 19 of 23 [+] Feedback Figure 56-Pin Sawn QFN 8X8X0.90 MM CY7C65640A 51-85187 C Note. The bottom metal pad size varies by product due to die size variable. If metal pad design or dimension are critical with your board designs, please contact a Cypress Sales office to get the specific outline option. Quad Flat Package No Leads QFN Package Design Notes The QFN Quad Flatpack No Leads , being a lead free package, the electrical contact of the part to the Printed Circuit Board PCB is made by soldering the lands on the bottom surface of the package to the PCB. Hence special attention is required to the heat transfer area below the package to provide a good thermal bond to the circuit board. A Copper Cu fill should be designed into the PCB as a thermal pad under the package. Heat is transferred from the TetraHub through the device’s metal paddle on the bottom side of the package. Heat from here is conducted to the PCB at the thermal pad. It is then conducted from the thermal pad to the PCB inner ground plane by a 5 x 5 array of via. A via is a plated through-hole in the PCB with a finished diameter of 13 mil. The QFN’s metal die paddle must be soldered to the PCB’s thermal pad. Solder mask is placed on the board top side over each via to resist solder flow into the via. The mask on the top side also minimizes outgassing during the solder reflow process. Please follow the layout guidelines provided in the PCB layout files accompanied with the CY4602 TetraHub Reference Design Kit. The information in this section was derived from the original application note by the package vendor. For further information on this package design please refer to the application note “Surface Mount Assembly of AMKOR’s MicroLeadFrame MLF Technology”. This application note can be downloaded from AMKOR’s website from the following URL 0301.pdf. This application note provides detailed information on board mounting guidelines, soldering flow, rework process, etc. Figure 9 below displays a cross-sectional area underneath the package. The cross section is of only one via. The solder Paste template needs to be designed to allow at least 50% solder coverage. The thickness of the solder paste template should be 5 mil. It is recommended that “No Clean”, type 3 solder paste is used for mounting the part. Nitrogen purge is recommended during reflow. Page 20 of 23 [+] Feedback CY7C65640A Figure Cross section of the Area Underneath the QFN Package Cu Fill Solder Mask Cu Fill PCB Material PCB Material Via hole for thermally connecting the QFN to the circuit board ground plane. This figure only shows the top three layers of the circuit board Top Solder, PCB Dielectric, and the Ground Plane. Figure 10 is a plot of the solder mask pattern and Figure 11 displays an X-Ray image of the assembly darker areas indicate solder . Figure Plot of the Solder Mask White Area Figure X-Ray Image of the Assembly Page 21 of 23 [+] Feedback CY7C65640A Document History Page Document Title CY7C65640A TetraHub High Speed USB Hub Controller Document Number 38-08019 ECN NO. Submission Date Orig. of Change Description of Change 113506 04/25/02 BHA New Data Sheet preliminary *J 2657415 02/10/09 DPT/PYRS Added package diagram spec 51-85187, updated package diagram spec 51-85144 and updated Ordering Information table Page 22 of 23 [+] Feedback CY7C65640A Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General psoc.cypress.com/solutions Low Power/Low Voltage psoc.cypress.com/low-power Precision Analog psoc.cypress.com/precision-analog LCD Drive psoc.cypress.com/lcd-drive CAN 2.0b psoc.cypress.com/can psoc.cypress.com/usb Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 23 of 23 PSoC Designer and Programmable System-on-Chip are trademarks and is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback

PDF Datasheet Preview

CY7C65640A

TetraHub High Speed USB Hub Controller
• USB hub
• Four downstream ports
• Multiple transaction translators - one per downstream port for maximum performance
• VID, PID, and DID configured from external SPI EEPROM
• 24 MHz external crystal
• Small package - Quad Flat Pack, no leads QFN
• Integrated upstream pull up resistor
• Integrated downstream pull down resistors for all downstream ports

Logic Block Diagram
24 MHz Crystal

USB PHY PLL USB Upstream
• Integrated upstream and downstream series termination resistors
• Configurable with external SPI EEPROM Number of Active Ports Number of Removable Ports Maximum Power Hub Controller Power-On Timer Overcurrent Timer Disable Overcurrent Timer Enable Full Speed Only Disable Port Indicators Gang Power Switching Enable Single TT Mode Only Enable NoEOPatEOF1

Serial Interface Engine

High speed USB Control Logic

SPI Communication Block

SPI_SCK SPI_SD SPI_CS

Hub Repeater

Transaction Translator X4 TT RAM

Routing Logic

USB Downstream

USB Port Pow- Port er Control Sta-

USB Downstream

USB Port Pow- Port er Control Sta-

USB Downstream

USB Port Pow- Port er Control Sta-

USB Downstream

USB Port Pow- Port er Control Sta-

D+ PWR#[1 OVR#[1LED D+ PWR#[2 OVR#[2LED D+ PWR#[3 OVR#[3LED D+ PWR#[4 OVR#[4LED
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY7C65640A

Introduction

Cypress’s TetraHub is a high-performance self-powered Universal Serial Bus USB hub. The Tetra architecture provides four downstream USB ports, with a Transaction Translator TT for each port, making it the highest-performance hub possible. This single-chip device incorporates one upstream and four downstream USB transceivers, a Serial Interface Engine SIE , USB Hub Controller and Repeater, and four TTs. It is suitable for standalone hubs, motherboard hubs, and monitor hub applications.

Being a fixed-function USB device, there is no risk or added engineering effort required for firmware development. The developer does not need to write any firmware for their design. The CY4602 Tetrahub USB 4-port Hub Reference Design Kit provides all materials and documents needed to move rapidly into production. The reference design kit includes board schematics, bill of materials, Gerber files, Orcad files, key application notes, and product description.

TetraHub Architecture

The Logic Block Diagram on page 1 shows the TetraHub Architecture.

USB Serial Interface Engine SIE

The SIE allows the CY7C65640A to communicate with the USB host through the USB repeater component of the hub. The SIE handles the following USB bus activity independently of the Hub Control Block:
Ordering Information
Ordering Code CY7C65640A-LFXC CY7C65640A-LTXC CY7C65640A-LTXCT CY4602

Package Type 56-pin QFN Pb-free Package 56-pin QFN Sawn type 56-pin QFN Sawn type TetraHub USB 4 port Hub Reference Design Kit

Package Diagram

The TetraHub is available in a space-saving 56-pin QFN 8 x 8 mm Figure 56-Pin QFN 8 x 8 MM LF56A
51-85144 *G

Page 19 of 23 [+] Feedback

Figure 56-Pin Sawn QFN 8X8X0.90 MM

CY7C65640A
51-85187 *C

Note. The bottom metal pad size varies by product due to die size variable. If metal pad design or dimension are critical with your board designs, please contact a Cypress Sales office to get the specific outline option.

Quad Flat Package No Leads QFN Package Design Notes

The QFN Quad Flatpack No Leads , being a lead free package, the electrical contact of the part to the Printed Circuit Board PCB is made by soldering the lands on the bottom surface of the package to the PCB. Hence special attention is required to the heat transfer area below the package to provide a good thermal bond to the circuit board. A Copper Cu fill should be designed into the PCB as a thermal pad under the package. Heat is transferred from the TetraHub through the device’s metal paddle on the bottom side of the package. Heat from here is conducted to the PCB at the thermal pad. It is then conducted from the thermal pad to the PCB inner ground plane by a 5 x 5 array of via. A via is a plated through-hole in the PCB with a finished diameter of 13 mil. The QFN’s metal die paddle must be soldered to the PCB’s thermal pad. Solder mask is placed on the board top side over each via to resist solder flow into the via. The
mask on the top side also minimizes outgassing during the solder reflow process.

Please follow the layout guidelines provided in the PCB layout files accompanied with the CY4602 TetraHub Reference Design Kit. The information in this section was derived from the original application note by the package vendor. For further information on this package design please refer to the application note “Surface Mount Assembly of AMKOR’s MicroLeadFrame MLF Technology”. This application note can be downloaded from AMKOR’s website from the following URL
0301.pdf.

This application note provides detailed information on board mounting guidelines, soldering flow, rework process, etc.

Figure 9 below displays a cross-sectional area underneath the package. The cross section is of only one via. The solder Paste template needs to be designed to allow at least 50% solder coverage. The thickness of the solder paste template should be 5 mil. It is recommended that “No Clean”, type 3 solder paste is used for mounting the part. Nitrogen purge is recommended during reflow.

Page 20 of 23 [+] Feedback

CY7C65640A

Figure Cross section of the Area Underneath the QFN Package

Cu Fill

Solder Mask

Cu Fill

PCB Material

PCB Material

Via hole for thermally connecting the QFN to the circuit board ground plane.

This figure only shows the top three layers of the circuit board Top Solder, PCB Dielectric, and the Ground Plane.

Figure 10 is a plot of the solder mask pattern and Figure 11 displays an X-Ray image of the assembly darker areas indicate solder .

Figure Plot of the Solder Mask White Area

Figure X-Ray Image of the Assembly

Page 21 of 23 [+] Feedback

CY7C65640A

Document History Page

Document Title CY7C65640A TetraHub High Speed USB Hub Controller Document Number 38-08019

ECN NO.

Submission Date

Orig. of Change

Description of Change
113506
04/25/02

BHA New Data Sheet preliminary
*J 2657415 02/10/09 DPT/PYRS Added package diagram spec 51-85187, updated package diagram spec 51-85144 and updated Ordering Information table

Page 22 of 23 [+] Feedback

CY7C65640A

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products PSoC Clocks & Buffers Wireless Memories Image Sensors
psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com

PSoC Solutions

General
psoc.cypress.com/solutions

Low Power/Low Voltage
psoc.cypress.com/low-power

Precision Analog
psoc.cypress.com/precision-analog

LCD Drive
psoc.cypress.com/lcd-drive

CAN 2.0b
psoc.cypress.com/can
psoc.cypress.com/usb

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 23 of 23

PSoC Designer and Programmable System-on-Chip are trademarks and is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

All products and company names mentioned in this document may be the trademarks of their respective holders.
[+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C65640A-LFXCT Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C65640A-LFXCT 508135