CY7C64215-56LFXC

CY7C64215-56LFXC Datasheet

CY7C64215

Part	Datasheet
CY7C64215-56LFXC	CY7C64215-56LFXC (pdf)

Related Parts	Information
CY7C64215-56LFXCT	CY7C64215-56LFXCT

PDF Datasheet Preview
CY7C64215 enCoRe III Full Speed USB Controller • Powerful Harvard Architecture Processor M8C Processor Speeds to 24 MHz Two 8x8 Multiply, 32-Bit Accumulate to 5.25V Operating Voltage USB-IF Certified. TID# 40000110 Commercial Operating Temperature Range 0°C to +70°C Industrial Operating Temperature Range to +85°C • Advanced Peripherals enCoRe III Blocks 6 Analog enCoRe III Blocks provide • Up to 14-Bit Incremental and Delta Sigma ADCs Programmable Threshold Comparator Four Digital enCoRe III Blocks Provide • 8-Bit and 16-Bit PWMs, Timers, and Counters • I2C Master • SPI Master or Slave • Full Duplex UART • CYFISNP and CYFISPI Modules to Talk to Cypress CYFI Radio • Complex Peripherals by Combining Blocks • Full Speed USB 12 Mbps Four Unidirectional Endpoints One Bidirectional Control Endpoint Dedicated 256 Byte Buffer No External Crystal Required Operational at 3.15V to 3.5V or 4.35V to 5.25V • Flexible On-Chip Memory 16K Flash Program Storage 50,000 Erase/Write Cycles 1K SRAM Data Storage In-System Serial Programming ISSP Partial Flash Updates Flexible Protection Modes EEPROM Emulation in Flash • Programmable Pin Configurations 25 mA Sink on all GPIO Pull Up, Pull Down, High Z, Strong, or Open Drain Drive Modes on all GPIO Configurable Interrupt on all GPIO • Precision, Programmable Clocking Internal ±4% 24 and 48 MHz Oscillator with Support for External Clock Oscillator Internal Oscillator for Watchdog and Sleep Accuracy for USB with no External Components • Additional System Resources I2C Slave, Master, and Multi-Master to 400 kHz Watchdog and Sleep Timers User-Configurable Low Voltage Detection Integrated Supervisory Circuit On-Chip Precision Voltage Reference • Complete Development Tools Free Development Software PSoC Designer Full Featured, In-Circuit Emulator and Programmer Full Speed Emulation Complex Breakpoint Structure 128K Bytes Trace Memory Block Diagram enCoRe III Core • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Contents Features 1 Block Diagram 1 Contents 2 Applications 3 enCoRe III Functional Overview 3 enCoRe III Core 3 The Digital System 3 The Analog System 4 Additional System Resources 4 enCoRe III Device Characteristics 4 Getting Started 5 Development Kits 5 Technical Training Modules 5 Consultants 5 Technical Support 5 Application Notes 5 Development Tools 5 PSoC Designer Software Subsystems 5 Hardware Tools 6 Designing with User Modules 6 Document Conventions 7 Acronyms Used 7 Units of Measure 7 Numeric Naming 7 CY7C64215 Pin Information 8 56-Pin Part Pinout 8 28-Pin Part Pinout 9 Register Reference 10 Register Mapping Tables 10 Register Map Bank 0 Table User Space 11 Register Map Bank 1 Table Configuration Space 12 Electrical Specifications 13 Absolute Maximum Ratings 14 Operating Temperature 14 DC Electrical Characteristics 15 AC Electrical Characteristics 22 Packaging Information 28 Package Diagrams 28 Thermal Impedance 30 Solder Reflow Peak Temperature 30 Package Handling 30 Ordering Information 31 Document History Page 32 Sales, Solutions, and Legal Information 33 Worldwide Sales and Design Support 33 Products 33 Solutions 33 Page 2 of 33 [+] Feedback CY7C64215 • PC HID devices Mouse Optomechanical, Optical, Trackball Keyboards Joysticks • Gaming Game Pads Console Keyboards • General Purpose Barcode Scanners POS Terminal Consumer Electronics Toys Remote Controls USB to Serial enCoRe III Functional Overview The enCoRe III is based on flexible PSoC architecture and is a full featured, full speed 12 Mbps USB part. Configurable analog, digital, and interconnect circuitry enable a high level of integration in a host of consumer, and communication applications. This architecture enables the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in both 28-pin SSOP and 56-pin QFN packages. enCoRe III architecture, as illustrated in the “Block Diagram” on page 1, is comprised of four main areas enCoRe III Core, Digital System, Analog System, and System Resources including a full speed USB port. Configurable global busing enables all the device resources to combine into a complete custom system. The enCoRe III CY7C64215 can have up to seven I/O ports that connect to the global digital and analog interconnects, providing access to 4 digital blocks and 6 analog blocks. enCoRe III Core The enCoRe III Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO General Purpose I/O . The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU uses an interrupt controller with up to 20 vectors, to simplify programming of real-time embedded events. Program execution is timed and protected using the included Sleep and Watch Dog Timers WDT . Memory encompasses 16K of Flash for program storage, 1K of SRAM for data storage, and up to 2K of EEPROM emulated using the Flash. Program Flash uses four protection levels on blocks of 64 bytes, enabling customized software IP protection. enCoRe III incorporates flexible internal clock generators, including a 24 MHz IMO internal main oscillator accurate to 8% over temperature and voltage as well as an option for an external clock oscillator. USB operation requires the OSC LOCK bit of the USB_CR0 register to be set to obtain IMO accuracy to The 24 MHz IMO is doubled to 48 MHz for use by the digital system, if needed. The 48 MHz clock is required to clock the USB block and must be enabled for communication. A low power 32 kHz ILO internal low speed oscillator is provided for the Sleep Timer and WDT. The clocks, together with programmable clock dividers System Resource , provide flexibility to integrate almost any timing requirement into enCoRe III. In USB systems, the IMO self-tunes to accuracy for USB communication. The extended temperature range for the Industrial operating range to +85°C requires the use of an external clock oscillator, which is only available on the 56-pin QFN package. enCoRe III GPIOs provide connection to the CPU, digital and analog resources of the device. Each pin’s drive mode may be selected from eight options, enabling great flexibility in external interfacing. Every pin also has capability to generate a system interrupt on high level, low level, and change from last read. The Digital System The Digital System is composed of four digital enCoRe III blocks. Each block is an 8-bit resource that is used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Figure Digital System Block Diagram Port 7 Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Digital Clocks From Core To System Bus To Analog System DIGITAL SYSTEM Digital enCoRe III Block Array Row 0 DBB00 DBB01 DCB02 DCB03 4 Row Input Configuration Row Output Configuration GIE[7:0] GIO[7:0] GlobalDigital Interconnect GOE[7:0] GOO[7:0] The following digital configurations can be built from the blocks: For up-to-date Ordering, Packaging, and Electrical Specification information, reference the latest enCoRe V device data sheets on the web at Development Kits Development Kits are available online from Cypress at and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. Under Product Categories, click USB Universal Serial Bus to view a current list of available items. Technical Training Modules Free technical training on demand, webinars, and workshops is available online at The training covers a wide variety of topics and skill levels to assist you in your designs. Consultants Certified USB consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to Technical Support For assistance with technical issues, search KnowledgeBase articles and forums at If you cannot find an answer to your question, call technical support at Application Notes Application notes are an excellent introduction to the wide variety of possible PSoC designs. They are located here Select Application Notes under the Documentation tab. Development Tools PSoC Designer is a based, integrated development environment for enCoRe III. The PSoC Designer IDE and application runs on Windows XP or Vista. PSoC Designer helps the customer to select an operating configuration for the enCoRe III, write application code that uses the enCoRe III, and debug the application. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and the CYASM macro assembler for the CPUs. PSoC Designer also supports a high-level C language compiler developed specifically for the devices in the family. PSoC Designer Software Subsystems Device Editor The Device Editor subsystem enables the user to select different onboard analog and digital components called user modules using the enCoRe III blocks. Examples of user modules are ADCs, SPIM, UART, and PWMs. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration enables changing configurations at run time. PSoC Designer sets up power on initialization tables for selected enCoRe III block configurations and creates source code for an application framework. The framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of enCoRe III block configurations at run time. PSoC Designer can print out a configuration sheet for a given project configuration for use during application programming in conjunction with the Device Data Sheet. Once the framework is generated, the user can add application-specific code to flesh out the framework. It is also possible to change the selected components and regenerate the framework. Application Editor In the Application Editor you can edit your C language and Assembly language source code. You can also assemble, compile, link, and build. Assembler. The macro assembler enables the assembly code to merge seamlessly with C code. The link libraries automatically use absolute addressing or is compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compiler. A C language compiler is available that supports the enCoRe III family of devices. Even if you have never worked in the C language before, the product quickly enables you to create complete C programs for the enCoRe III devices. The embedded, optimizing C compiler provides all the features of C tailored to the enCoRe III architecture. It comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Page 5 of 33 [+] Feedback CY7C64215 Debugger The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, enabling the designer to test the program in a physical system while providing an internal view of the enCoRe III device. Debugger commands enable the designer to read and program and read and write data memory, read and write I/O registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also enables the designer to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. Hardware Tools In-Circuit Emulator A low cost, high functionality ICE Cube is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal which operates with all enCoRe III devices. Designing with User Modules The development process for the enCoRe III device differs from that of a traditional fixed-function microprocessor. The configurable analog and digital hardware blocks give the enCoRe III architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called enCoRe III Blocks, have the ability to implement a wide variety of user-selectable functions. Each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses and to the I/O pins. Iterative development cycles permit you to adapt the hardware and software. This substantially lowers the risk of having to select a different part to meet the final design requirements. To speed the development process, the PSoC Designer Integrated Development Environment IDE provides a library of pre-built, pre-tested hardware peripheral functions, called “User Modules.” User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. The user module library contains the following digital and analog module designs: • Analog Blocks Incremental ADC ADCINC Delta Sigma ADC DelSig Programmable Threshold Comparator CMPPRG • Digital Blocks Ordering Information Package 56-Pin QFN-MLF Punch 56-Pin QFN-MLF Punch Tape and Reel 28-Pin SSOP 28-Pin SSOP Tape and Reel 56-Pin QFN Sawn Commercial 56-Pin QFN Sawn Commercial Tape and Reel 56-Pin QFN Sawn Industrial 56-Pin QFN Sawn Industrial Tape and Reel Ordering Code CY7C64215-56LFXC CY7C64215-56LFXCT CY7C64215-28PVXC CY7C64215-28PVXCT CY7C64215-56LTXC CY7C64215-56LTXCT CY7C64215-56LTXI CY7C64215-56LTXIT CY7C64215 Flash Size 16K SRAM Bytes 1K Temperature Range 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C to 85°C to 85°C Page 31 of 33 [+] Feedback CY7C64215 Document History Page Description Title CY7C64215, enCoRe III Full Speed USB Controller Document Number 38-08036 ECN No. Submission Date Orig. of Change Description of Change 131325 See ECN XGR New data sheet. 385256 See ECN Changed from Advance Information to Preliminary. Added standard data sheet items. Changed Part number from CY7C642xx to CY7C64215. B 2547630 08/04/08 AZIEL/PYRS Operational voltage range for USB specified under "Full Speed USB 12Mbps ". CMP_GO_EN1 register removed as it has no functionality on Radon. Figure "CPU Frequency" adjusted to show invalid operating region for USB with footnote describing reason. DC electrical characteristic, Vdd. Note added describing where USB hardware is non-functional. C 2620679 12/12/08 CMCC/PYRS Added Package Handling information. Deleted note regarding link to amkor.com for MLF package dimensions. D 2717887 06/11/2009 Added 56 -Pin Sawn QFN 8 X 8 mm package diagram and added CY7C64215-56LTXC part information in the Ordering Information table. E 2852393 01/15/2010 BHA/XUT • Added Table of Contents. • Added external clock oscillator option and Industrial Temperature information to the Features, Pin Information, Electrical Specifications, Operating Temperature, DC Electrical Characteristics, AC Electrical Characteristics, and Ordering Information sections. • Updated DC GPIO, AC Chip, and AC Programming Specifications follows: Replaced TRAMP time with SRPOWER_UP slew rate specification. Added IOH, IOL, DCILO, F32K_U, TPOWERUP, TERASEALL, TPROGRAM_HOT, and TPROGRAM_COLD specifications. Updated Vdd ranges on Figure 5 and Table Added notes for VM and VDI on Table Removed TR/TF from Table • Update Ordering Information for CY7C64215-56LFXCT, CY7C64215-28PVXCT, CY7C64215-56LTXIT Tape and Reel. • Updated 28-Pin SSOP and 56-Pin QFN PUNCH and SAWN package diagrams. • Updated copyright and Sales, Solutions, and Legal Information URLs. Page 32 of 33 [+] Feedback CY7C64215 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, 2007-2009, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 33 of 33 PSoC Designer and enCoRe are trademarks and is a registered trademark of Cypress Semiconductor Corporation. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback

PDF Datasheet Preview

CY7C64215
enCoRe III Full Speed USB Controller
• Powerful Harvard Architecture Processor M8C Processor Speeds to 24 MHz Two 8x8 Multiply, 32-Bit Accumulate to 5.25V Operating Voltage USB-IF Certified. TID# 40000110 Commercial Operating Temperature Range 0°C to +70°C Industrial Operating Temperature Range to +85°C
• Advanced Peripherals enCoRe III Blocks 6 Analog enCoRe III Blocks provide
• Up to 14-Bit Incremental and Delta Sigma ADCs Programmable Threshold Comparator Four Digital enCoRe III Blocks Provide
• 8-Bit and 16-Bit PWMs, Timers, and Counters
• I2C Master
• SPI Master or Slave
• Full Duplex UART
• CYFISNP and CYFISPI Modules to Talk to Cypress CYFI Radio
• Complex Peripherals by Combining Blocks
• Full Speed USB 12 Mbps Four Unidirectional Endpoints One Bidirectional Control Endpoint Dedicated 256 Byte Buffer No External Crystal Required Operational at 3.15V to 3.5V or 4.35V to 5.25V
• Flexible On-Chip Memory 16K Flash Program Storage 50,000 Erase/Write Cycles 1K SRAM Data Storage In-System Serial Programming ISSP Partial Flash Updates Flexible Protection Modes EEPROM Emulation in Flash
• Programmable Pin Configurations 25 mA Sink on all GPIO Pull Up, Pull Down, High Z, Strong, or Open Drain Drive Modes on all GPIO Configurable Interrupt on all GPIO
• Precision, Programmable Clocking Internal ±4% 24 and 48 MHz Oscillator with Support for External Clock Oscillator Internal Oscillator for Watchdog and Sleep Accuracy for USB with no External Components
• Additional System Resources I2C Slave, Master, and Multi-Master to 400 kHz Watchdog and Sleep Timers User-Configurable Low Voltage Detection Integrated Supervisory Circuit On-Chip Precision Voltage Reference
• Complete Development Tools Free Development Software PSoC Designer Full Featured, In-Circuit Emulator and Programmer Full Speed Emulation Complex Breakpoint Structure 128K Bytes Trace Memory

Block Diagram
enCoRe III Core
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

Contents

Features 1 Block Diagram 1 Contents 2 Applications 3 enCoRe III Functional Overview 3
enCoRe III Core 3 The Digital System 3 The Analog System 4 Additional System Resources 4 enCoRe III Device Characteristics 4 Getting Started 5 Development Kits 5 Technical Training Modules 5 Consultants 5 Technical Support 5 Application Notes 5 Development Tools 5 PSoC Designer Software Subsystems 5 Hardware Tools 6 Designing with User Modules 6 Document Conventions 7 Acronyms Used 7 Units of Measure 7 Numeric Naming 7

CY7C64215

Pin Information 8 56-Pin Part Pinout 8 28-Pin Part Pinout 9

Register Reference 10 Register Mapping Tables 10 Register Map Bank 0 Table User Space 11 Register Map Bank 1 Table Configuration Space 12

Electrical Specifications 13 Absolute Maximum Ratings 14 Operating Temperature 14
DC Electrical Characteristics 15 AC Electrical Characteristics 22 Packaging Information 28 Package Diagrams 28 Thermal Impedance 30 Solder Reflow Peak Temperature 30 Package Handling 30 Ordering Information 31 Document History Page 32 Sales, Solutions, and Legal Information 33 Worldwide Sales and Design Support 33 Products 33 Solutions 33

Page 2 of 33 [+] Feedback

CY7C64215
• PC HID devices Mouse Optomechanical, Optical, Trackball Keyboards Joysticks
• Gaming Game Pads Console Keyboards
• General Purpose Barcode Scanners POS Terminal Consumer Electronics Toys Remote Controls USB to Serial
enCoRe III Functional Overview

The enCoRe III is based on flexible PSoC architecture and is a full featured, full speed 12 Mbps USB part. Configurable analog, digital, and interconnect circuitry enable a high level of integration in a host of consumer, and communication applications.

This architecture enables the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in both 28-pin SSOP and 56-pin QFN packages.
enCoRe III architecture, as illustrated in the “Block Diagram” on page 1, is comprised of four main areas enCoRe III Core, Digital System, Analog System, and System Resources including a full speed USB port. Configurable global busing enables all the device resources to combine into a complete custom system. The enCoRe III CY7C64215 can have up to seven I/O ports that connect to the global digital and analog interconnects, providing access to 4 digital blocks and 6 analog blocks.
enCoRe III Core

The enCoRe III Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO General Purpose I/O .

The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU uses an interrupt controller with up to 20 vectors, to simplify programming of real-time embedded events. Program execution is timed and protected using the included Sleep and Watch Dog Timers WDT .

Memory encompasses 16K of Flash for program storage, 1K of SRAM for data storage, and up to 2K of EEPROM emulated using the Flash. Program Flash uses four protection levels on blocks of 64 bytes, enabling customized software IP protection.
enCoRe III incorporates flexible internal clock generators, including a 24 MHz IMO internal main oscillator accurate to 8% over temperature and voltage as well as an option for an external clock oscillator. USB operation requires the OSC LOCK bit of the USB_CR0 register to be set to obtain IMO accuracy to

The 24 MHz IMO is doubled to 48 MHz for use by the digital system, if needed. The 48 MHz clock is required to clock the USB block and must be enabled for communication. A low power 32 kHz ILO internal low speed oscillator is provided for the Sleep Timer and WDT. The clocks, together with programmable clock dividers System Resource , provide flexibility to integrate almost any timing requirement into enCoRe III. In USB systems, the IMO self-tunes to accuracy for USB communication.

The extended temperature range for the Industrial operating range to +85°C requires the use of an external clock oscillator, which is only available on the 56-pin QFN package.
enCoRe III GPIOs provide connection to the CPU, digital and analog resources of the device. Each pin’s drive mode may be selected from eight options, enabling great flexibility in external interfacing. Every pin also has capability to generate a system interrupt on high level, low level, and change from last read.

The Digital System

The Digital System is composed of four digital enCoRe III blocks. Each block is an 8-bit resource that is used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references.

Figure Digital System Block Diagram

Port 7

Port 5

Port 4

Port 3

Port 2

Port 1

Port 0

Digital Clocks From Core

To System Bus

To Analog System

DIGITAL SYSTEM

Digital enCoRe III Block Array

Row 0

DBB00 DBB01 DCB02 DCB03 4

Row Input Configuration

Row Output Configuration

GIE[7:0] GIO[7:0]

GlobalDigital Interconnect

GOE[7:0] GOO[7:0]

The following digital configurations can be built from the blocks:
For up-to-date Ordering, Packaging, and Electrical Specification information, reference the latest enCoRe V device data sheets on the web at

Development Kits

Development Kits are available online from Cypress at and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. Under Product Categories, click USB Universal Serial Bus to view a current list of available items.

Technical Training Modules

Free technical training on demand, webinars, and workshops is available online at The training covers a wide variety of topics and skill levels to assist you in your designs.

Consultants

Certified USB consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to

Technical Support

For assistance with technical issues, search KnowledgeBase articles and forums at If you cannot find an answer to your question, call technical support at

Application Notes

Application notes are an excellent introduction to the wide variety of possible PSoC designs. They are located here Select Application Notes under the Documentation tab.

Development Tools

PSoC Designer is a based, integrated development environment for enCoRe III. The PSoC Designer IDE and application runs on Windows XP or Vista.

PSoC Designer helps the customer to select an operating configuration for the enCoRe III, write application code that uses the enCoRe III, and debug the application. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and the CYASM macro assembler for the CPUs. PSoC Designer also supports a high-level C language compiler developed specifically for the devices in the family.

PSoC Designer Software Subsystems

Device Editor

The Device Editor subsystem enables the user to select different onboard analog and digital components called user modules using the enCoRe III blocks. Examples of user modules are ADCs, SPIM, UART, and PWMs.

The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration enables changing configurations at run time.

PSoC Designer sets up power on initialization tables for selected enCoRe III block configurations and creates source code for an application framework. The framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of enCoRe III block configurations at run time. PSoC Designer can print out a configuration sheet for a given project configuration for use during application programming in conjunction with the Device Data Sheet. Once the framework is generated, the user can add application-specific code to flesh out the framework. It is also possible to change the selected components and regenerate the framework.

Application Editor

In the Application Editor you can edit your C language and Assembly language source code. You can also assemble, compile, link, and build.

Assembler. The macro assembler enables the assembly code to merge seamlessly with C code. The link libraries automatically use absolute addressing or is compiled in relative mode, and linked with other software modules to get absolute addressing.

C Language Compiler. A C language compiler is available that supports the enCoRe III family of devices. Even if you have never worked in the C language before, the product quickly enables you to create complete C programs for the enCoRe III devices.

The embedded, optimizing C compiler provides all the features of C tailored to the enCoRe III architecture. It comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality.

Page 5 of 33 [+] Feedback

CY7C64215

Debugger

The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, enabling the designer to test the program in a physical system while providing an internal view of the enCoRe III device. Debugger commands enable the designer to read and program and read and write data memory, read and write I/O registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also enables the designer to create a trace buffer of registers and memory locations of interest.

Online Help System

The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started.

Hardware Tools

In-Circuit Emulator

A low cost, high functionality ICE Cube is available for development support. This hardware has the capability to program single devices.

The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal which operates with all enCoRe III devices.

Designing with User Modules

The development process for the enCoRe III device differs from that of a traditional fixed-function microprocessor. The configurable analog and digital hardware blocks give the enCoRe III architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called enCoRe III Blocks, have the ability to implement a wide variety of user-selectable functions. Each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses and to the I/O pins. Iterative development cycles permit you to adapt the hardware and software. This substantially lowers the risk of having to select a different part to meet the final design requirements.

To speed the development process, the PSoC Designer Integrated Development Environment IDE provides a library of pre-built, pre-tested hardware peripheral functions, called “User Modules.” User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties.

The user module library contains the following digital and analog module designs:
• Analog Blocks

Incremental ADC ADCINC Delta Sigma ADC DelSig Programmable Threshold Comparator CMPPRG
• Digital Blocks
Ordering Information

Package 56-Pin QFN-MLF Punch 56-Pin QFN-MLF Punch Tape and Reel 28-Pin SSOP 28-Pin SSOP Tape and Reel 56-Pin QFN Sawn Commercial 56-Pin QFN Sawn Commercial Tape and Reel 56-Pin QFN Sawn Industrial 56-Pin QFN Sawn Industrial Tape and Reel
Ordering Code CY7C64215-56LFXC CY7C64215-56LFXCT

CY7C64215-28PVXC CY7C64215-28PVXCT

CY7C64215-56LTXC CY7C64215-56LTXCT

CY7C64215-56LTXI CY7C64215-56LTXIT

CY7C64215

Flash Size 16K

SRAM Bytes 1K

Temperature Range 0°C to 70°C 0°C to 70°C
0°C to 70°C 0°C to 70°C
0°C to 70°C 0°C to 70°C
to 85°C to 85°C

Page 31 of 33 [+] Feedback

CY7C64215

Document History Page

Description Title CY7C64215, enCoRe III Full Speed USB Controller Document Number 38-08036

ECN No.

Submission Date

Orig. of Change

Description of Change
131325 See ECN

XGR New data sheet.
385256 See ECN

Changed from Advance Information to Preliminary. Added standard data sheet items. Changed Part number from CY7C642xx to CY7C64215.
*B 2547630 08/04/08 AZIEL/PYRS Operational voltage range for USB specified under "Full Speed USB 12Mbps ". CMP_GO_EN1 register removed as it has no functionality on Radon. Figure "CPU Frequency" adjusted to show invalid operating region for USB with footnote describing reason. DC electrical characteristic, Vdd. Note added describing where USB hardware is non-functional.
*C 2620679 12/12/08 CMCC/PYRS Added Package Handling information. Deleted note regarding link to amkor.com for MLF package dimensions.
*D 2717887 06/11/2009
Added 56 -Pin Sawn QFN 8 X 8 mm package diagram and added CY7C64215-56LTXC part information in the Ordering Information table.
*E 2852393 01/15/2010 BHA/XUT
• Added Table of Contents.
• Added external clock oscillator option and Industrial Temperature information to the Features, Pin Information, Electrical Specifications, Operating Temperature, DC Electrical Characteristics, AC Electrical Characteristics, and Ordering Information sections.
• Updated DC GPIO, AC Chip, and AC Programming Specifications follows:

Replaced TRAMP time with SRPOWER_UP slew rate specification.

Added IOH, IOL, DCILO, F32K_U, TPOWERUP, TERASEALL, TPROGRAM_HOT, and TPROGRAM_COLD specifications.

Updated Vdd ranges on Figure 5 and Table

Added notes for VM and VDI on Table
Removed TR/TF from Table
• Update Ordering Information for CY7C64215-56LFXCT,

CY7C64215-28PVXCT, CY7C64215-56LTXIT Tape and Reel.
• Updated 28-Pin SSOP and 56-Pin QFN PUNCH and SAWN package
diagrams.
• Updated copyright and Sales, Solutions, and Legal Information URLs.

Page 32 of 33 [+] Feedback

CY7C64215

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, 2007-2009, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 33 of 33

PSoC Designer and enCoRe are trademarks and is a registered trademark of Cypress Semiconductor Corporation. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.

All products and company names mentioned in this document may be the trademarks of their respective holders.
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Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C64215-56LFXC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C64215-56LFXC 508128