CY7C64113C-PVXC

CY7C64113C-PVXC Datasheet


CY7C64013C CY7C64113C

Part Datasheet
CY7C64113C-PVXC CY7C64113C-PVXC CY7C64113C-PVXC (pdf)
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CY7C64013C CY7C64113C

Full-Speed USB 12-Mbps Function

Full-Speed USB 12-Mbps Function

Cypress Semiconductor Corporation
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600

TABLE OF CONTENTS

CY7C64013C CY7C64113C

FUNCTIONAL OVERVIEW

PIN CONFIGURATIONS

PRODUCT SUMMARY TABLES

Pin Assignments I/O Register Summary Instruction Set Summary

PROGRAMMING MODEL
14-Bit Program Counter PC

Program Memory Organization
8-Bit Accumulator A 8-Bit Temporary Register X 8-Bit Program Stack Pointer PSP

Data Memory Organization
8-Bit Data Stack Pointer DSP Address Modes

Data Immediate Direct Indexed

CLOCKING

RESET

Power-On Reset POR Watchdog Reset WDR

SUSPEND MODE

GENERAL-PURPOSE I/O GPIO PORTS

GPIO Configuration Port GPIO Interrupt Enable Ports

DAC PORT

DAC Isink Registers DAC Port Interrupts
12-BIT FREE-RUNNING TIMER I2C AND HAPI CONFIGURATION REGISTER I2C-COMPATIBLE CONTROLLER

HARDWARE ASSISTED PARALLEL INTERFACE HAPI

PROCESSOR STATUS AND CONTROL REGISTER

INTERRUPTS

Interrupt Vectors Interrupt Latency USB Bus Reset Interrupt Timer Interrupt USB Endpoint Interrupts

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CY7C64013C CY7C64113C

TABLE OF CONTENTS
DAC Interrupt GPIO/HAPI Interrupt I2C Interrupt USB OVERVIEW USB Serial Interface Engine SIE USB Enumeration USB Upstream Port Status and Control USB SERIAL INTERFACE ENGINE OPERATION USB Device Address USB Device Endpoints USB Control Endpoint Mode Register USB Non-Control Endpoint Mode Registers USB Endpoint Counter Registers Endpoint Mode/Count Registers Update and Locking Mechanism USB MODE TABLES REGISTER SUMMARY SAMPLE SCHEMATIC ABSOLUTE MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS FOSC = 6 MHZ OPERATING TEMPERATURE = 0 TO 70°C, VCC = 4.0V TO 5.25V SWITCHING CHARACTERISTICS fOSC = MHz 46 ORDERING INFORMATION PACKAGE DIAGRAMS

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CY7C64013C

CY7C64113C

LIST OF FIGURES

Figure Clock Oscillator On-Chip Circuit Figure Watchdog Reset WDR Figure Block Diagram of a GPIO Pin Figure Port 0 Data Figure Port 1 Data Figure Port 2 Data Figure Port 3 Data Figure GPIO Configuration Register Figure Port 0 Interrupt Figure Port 1 Interrupt Figure Port 2 Interrupt Figure Port 3 Interrupt Figure Block Diagram of a DAC Figure DAC Port Data Figure DAC Sink Figure DAC Port Interrupt Enable Figure DAC Port Interrupt Polarity Figure Timer LSB Register Figure Timer MSB Register Figure Timer Block Diagram Figure HAPI/I2C Configuration Register Figure I2C Data Figure I2C Status and Control Register Figure Processor Status and Control Register Figure Global Interrupt Enable Register Figure USB Endpoint Interrupt Enable Register Figure Interrupt Controller Function Diagram Figure GPIO Interrupt Figure USB Status and Control Register Figure USB Device Address Registers Figure USB Device Endpoint Zero Mode Figure USB Non-Control Device Endpoint Mode Figure USB Endpoint Counter Registers Figure Token/Data Packet Flow Diagram Figure Clock Timing Figure USB Data Signal Timing Figure HAPI Read by External Interface from USB Figure HAPI Write by External Device to USB Microcontroller

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CY7C64013C CY7C64113C

LIST OF TABLES

Table Pin Assignments Table I/O Register Summary Table Instruction Set Summary Table GPIO Port Output Control Truth Table and Interrupt Polarity Table HAPI Port Configuration Table I2C Port Configuration Table I2C Status and Control Register Bit Definitions Table Port 2 Pin and HAPI Configuration Bit Definitions Table Interrupt Vector Assignments Table Control Bit Definition for Upstream Port Table Memory Allocation for Endpoints Table USB Register Mode Encoding Table Details of Modes for Differing Traffic Conditions see Table 19-1 for the decode legend 41

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CY7C64013C CY7C64113C
• Full-speed USB Microcontroller
• 8-bit USB Optimized Microcontroller

Harvard architecture 6-MHz external clock source
12-MHz internal CPU clock 48-MHz internal clock
• Internal memory 256 bytes of RAM
8 KB of PROM CY7C64013C, CY7C64113C
• Integrated Master/Slave I2C-compatible Controller 100 kHz enabled through General-Purpose I/O GPIO pins
• Hardware Assisted Parallel Interface HAPI for data transfer to external devices
• I/O ports

Three GPIO ports Port 0 to 2 capable of sinking 7 mA per pin typical An additional GPIO port 3 capable of sinking 12 mA per pin typical for high current requirements LEDs

Higher current drive achievable by connecting multiple GPIO pins together to drive a common output Each GPIO port can be configured as inputs with internal pull-ups or open drain outputs or traditional CMOS outputs A Digital to Analog Conversion DAC port with programmable current sink outputs is available on the CY7C64113C
devices Maskable interrupts on all I/O pins
• 12-bit free-running timer with one microsecond clock ticks
• Watchdog Timer WDT
• Internal Power-On Reset POR
• USB Specification Compliance Conforms to USB Specification, Version Conforms to USB HID Specification, Version Supports up to five user configured endpoints

Up to four 8-byte data endpoints Up to two 32-byte data endpoints Integrated USB transceivers
• Improved output drivers to reduce EMI
• Operating voltage from 4.0V to 5.5V DC
• Operating temperature from 0 to 70 degrees Celsius CY7C64013C available in 28-pin SOIC and 28-pin PDIP packages CY7C64113C available in 48-pin SSOP packages
• Industry-standard programmer support

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CY7C64013C CY7C64113C

Functional Overview

The CY7C64013C and CY7C64113C are 8-bit One Time Programmable microcontrollers that are designed for full-speed USB applications. The instruction set has been optimized specifically for USB operations, although the microcontrollers can be used for a variety of non-USB embedded applications.

GPIO

The CY7C64013C features 19 GPIO pins to support USB and other applications. The I/O pins are grouped into three ports P0[7:0], P1[2:0], P2[6:2], P3[2:0] where each port can be configured as inputs with internal pull-ups, open drain outputs, or traditional CMOS outputs. There are 16 GPIO pins Ports 0 and 1 which are rated at 7 mA typical sink current. Port 3 pins are rated at 12 mA typical sink current, a current sufficient to drive LEDs. Multiple GPIO pins can be connected together to drive a single output for more drive current capacity. Additionally, each GPIO can be used to generate a GPIO interrupt to the microcontroller. All of the GPIO interrupts share the same “GPIO” interrupt vector.

The CY7C64113C has 32 GPIO pins P0[7:0], P1[7:0], P2[7:0], P3[7:0]

The CY7C64113C has four programmable sink current I/O pins DAC pins P4[7,2:0] . Every DAC pin includes an integrated 14k pull-up resistor. When a ‘1’ is written to a DAC I/O pin, the output current sink is disabled and the output pin is driven HIGH by the internal pull-up resistor. When a ‘0’ is written to a DAC I/O pin, the internal pull-up resistor is disabled and the output pin provides the programmed amount of sink current. A DAC I/O pin can be used as an input with an internal pull-up by writing a ‘1’ to the pin.

The sink current for each DAC I/O pin can be individually programmed to one of 16 values using dedicated Isink registers. DAC bits P4[1:0] can be used as high-current outputs with a programmable sink current range of to 16 mA typical . DAC bits P4[7,2] have a programmable current sink range of to mA typical . Multiple DAC pins can be connected together to drive a single output that requires more sink current capacity. Each I/O pin can be used to generate a DAC interrupt to the microcontroller. Also, the interrupt polarity for each DAC I/O pin is individually programmable.

Clock

The microcontroller uses an external 6-MHz crystal and an internal oscillator to provide a reference to an internal PLL-based clock generator. This technology allows the customer application to use an inexpensive 6-MHz fundamental crystal that reduces the clock-related noise emissions EMI . A PLL clock generator provides the 6-, 12-, and 48-MHz clock signals for distribution within the microcontroller.

Memory

The CY7C64013C and CY7C64113C have 8 KB of PROM.

Power on Reset, Watchdog and Free running Time

These parts include power-on reset logic, a Watchdog timer, and a 12-bit free-running timer. The power-on reset POR logic detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at PROM address 0x0000. The Watchdog timer is used to ensure the microcontroller recovers after a period of inactivity. The firmware may become inactive for a variety of reasons, including errors in the code or a hardware failure such as waiting for an interrupt that never occurs.

I2C and HAPI Interface The microcontroller can communicate with external electronics through the GPIO pins. An I2C-compatible interface accommodates a 100-kHz serial link with an external device. There is also a Hardware Assisted Parallel Interface HAPI which can be used to transfer data to an external device.

Timer

The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources, 128-us and 1.024-ms. The timer can be used to measure the duration of an event under firmware control by reading the timer at the start of the event and after the event is complete. The difference between the two readings indicates the duration of the event in microseconds. The upper four bits of the timer are latched into an internal register when the firmware reads the lower eight bits. A read from the upper four bits actually reads data from the internal register, instead of the timer. This feature eliminates the need for firmware to try to compensate if the upper four bits increment immediately after the lower eight bits are read.

Interrupts

The microcontroller supports 11 maskable interrupts in the vectored interrupt controller. Interrupt sources include the USB Bus Reset interrupt, the 128-us bit 6 and 1.024-ms bit 9 outputs from the free-running timer, five USB endpoints, the DAC port, the GPIO ports, and the I2C-compatible master mode interface. The timer bits cause an interrupt if enabled when the bit toggles from LOW ‘0’ to HIGH The USB endpoints interrupt after the USB host has written data to the endpoint FIFO or after the USB controller sends a packet to the USB host. The DAC ports have an additional level of masking that allows the user to select which DAC inputs can cause a DAC interrupt. The GPIO ports also have a level of masking to select which GPIO inputs can cause a GPIO interrupt. For additional flexibility, the input transition polarity that causes an interrupt is programmable for each pin of the DAC port. Input transition polarity can be programmed for each GPIO port as part of the port configuration. The interrupt polarity can be rising edge ‘0’ to ‘1’ or falling edge ‘1’ to

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Ordering Information
Ordering Code CY7C64013C-SXC CY7C64013C-PXC CY7C64013C-SXCT CY7C64113C-PVXC

PROM Size 8 KB 8 KB 8 KB 8 KB

Package Type 28-Pin 300-Mil SOIC 28-Pin 300-Mil PDIP 28-Pin 300-Mil SOIC - Tape Reel 48-Pin 300-Mil SSOP

Operating Range

Commercial

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Package Diagrams
48-Lead Shrunk Small Outline Package

CY7C64013C CY7C64113C
28-Lead 300-Mil PDIP

SEE LEAD END OPTION 1

DIMENSIONS IN INCHES [MM] MIN. MAX.

REFERENCE JEDEC MO-095 PACKAGE WEIGHT gms

LEAD END OPTION LEAD #1, 14, 15 & 28

SEATING PLANE

SEE LEAD END OPTION
3° MIN.
51-85061-*C 51-85014-*D

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Package Diagrams continued
28-Lead 300-Mil Molded SOIC

CY7C64013C CY7C64113C

PIN 1 ID

NOTE JEDEC STD REF MO-119

BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH,BUT

DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE.

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED in mm PER SIDE

DIMENSIONS IN INCHES PACKAGE WEIGHT 0.85gms

MIN. MAX.

PART # S28.3 STANDARD PKG. SZ28.3 LEAD FREE PKG.

SEATING PLANE

TYP.
51-85026-*D

All product and company names mentioned in this document are the trademarks of their respective holders.

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Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

CY7C64013C CY7C64113C

Document History Page

Document Title CY7C64013C, CY7C64113C Full-Speed USB 12 Mbps Function Document Number 38-08001

Issue Date

Orig. of Change
Updated part numbers in the Ordering section.

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Datasheet ID: CY7C64113C-PVXC 508126