CY7C63613-SC

CY7C63613-SC Datasheet

CY7C63612/13

Part	Datasheet
CY7C63613-SC	CY7C63613-SC (pdf)

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CY7C63612/13 CY7C63612/13 Low-Speed, Low I/O Mbps USB Controller Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 March 26, 1999 FO R FO R CY7C63612/13 TABLE OF CONTENTS FEATURES 5 FUNCTIONAL OVERVIEW 6 PIN ASSIGNMENTS 8 PROGRAMMING MODEL 8 14-bit Program Counter PC 8-bit Accumulator A 8-bit Index Register X 8-bit Program Stack Pointer PSP 8-bit Data Stack Pointer DSP 9 Address Modes 9 Data 9 Direct 9 Indexed 9 INSTRUCTION SET SUMMARY MEMORY ORGANIZATION Program Memory Organization 11 Data Memory Organization 12 I/O Register Summary 13 CLOCKING RESET Power-On Reset POR 14 Watch Dog Reset WDR 15 GENERAL PURPOSE I/O PORTS GPIO Interrupt Enable Ports GPIO Configuration Port 17 USB SERIAL INTERFACE ENGINE SIE USB Enumeration 18 PS/2 Operation 18 USB Port Status and Control USB DEVICE 19 USB Ports Device Endpoints 3 19 12-BIT FREE-RUNNING TIMER 20 Timer LSB 20 Timer MSB PROCESSOR STATUS AND CONTROL REGISTER 21 INTERRUPTS 21 Interrupt Vectors 22 Interrupt Latency 22 USB Bus Reset Interrupt Timer Interrupt 23 FO R FO R CY7C63612/13 TABLE OF CONTENTS continued USB Endpoint Interrupts 23 DAC Interrupt 23 GPIO Interrupt 23 TRUTH TABLES ABSOLUTE MAXIMUM RATINGS 26 DC CHARACTERISTICS 27 SWITCHING CHARACTERISTICS 28 ORDERING INFORMATION PACKAGE DIAGRAM 30 FO R FO R CY7C63612/13 LIST OF FIGURES Figure Program Memory Space with Interrupt Vector Table 11 Figure Clock Oscillator On-chip Circuit 14 Figure Watch Dog Reset WDR 15 Figure Block Diagram of a GPIO Line 15 Figure Port 0 Data 0x00h read/write 16 Figure Port 1 Data 0x01h read/write 16 Figure Port 2 Data 0x02h read/write 16 Figure Port 3 Data 0x03h read/write 16 Figure DAC Port Data 0x30h read/write 16 Figure Port 0 Interrupt Enable 0x04h write only 16 Figure Port 1 Interrupt Enable 0x05h write only 16 Figure Port 2 Interrupt Enable 0x06h write only 16 Figure Port 3 Interrupt Enable 0x07h write only 16 Figure GPIO Configuration Register 0x08h write only 17 Figure USB Status and Control Register 0x1Fh 18 Figure USB Device Address Register 0x10h read/write 19 Figure USB Device EPA0 Mode Register 0x12h read/write 19 Figure USB Device Endpoint Mode Registers 0x14h, 0x16h read/write 19 Figure USB Device Counter Registers 0x11h, 0x13h, 0x15h read/write 20 Figure Timer Register 0x24h read only 20 Figure Timer Register 0x25h read only 20 Figure Timer Block Diagram 20 Figure Processor Status and Control Register 0xFFh 21 Figure Global Interrupt Enable Register 0x20h read/write 21 Figure USB End Point Interrupt Enable Register 0x21h read/write 22 Figure Clock Timing 28 Figure USB Data Signal Timing 29 Figure Receiver Jitter Tolerance 29 Figure Differential to EOP Transition Skew and EOP Width 29 Figure Differential Data Jitter 30 LIST OF TABLES Table I/O Register Summary 13 Table Interrupt Vector Assignments 22 Table USB Register Mode Encoding 23 Table Decode table forTable 15-3 “Details of Modes for Differing Traffic Conditions” Table Details of Modes for Differing Traffic Conditions 25 FO R FO R CY7C63612/13 • Low-cost solution for low-speed applications with low I/O requirements such as mice, gamepads, and joystick applications • USB Specification Compliance Conforms to USB Specification, Version Conforms to USB HID Specification, Version Supports 1 device address and 3 data endpoints Integrated USB transceiver • 8-bit RISC microcontroller Harvard architecture 6-MHz external ceramic resonator 12-MHz internal CPU clock • Internal memory 256 bytes of RAM 6 Kbytes of EPROM CY7C63612 8 Kbytes of EPROM CY7C63613 • Interface can auto-configure to operate as PS2 or USB • I/O port 12 General-Purpose I/O GPIO pins Port 0 to 2 capable of sinking 7 mA per pin typical Four GPIO pins Port 3 capable of sinking 12 mA per pin typical which can drive LEDs Higher current drive is available by connecting multiple GPIO pins together to drive an common output Each GPIO port can be configured as inputs with internal pull-ups or open drain outputs or traditional CMOS outputs Maskable interrupts on all I/O pins • 12-bit free-running timer with one microsecond clock ticks • Watch Dog Timer WDT • Internal Power-On Reset POR • Improved output drivers to reduce EMI • Operating voltage from 4.0V to 5.5V DC • Operating temperature from 0 to 70 degrees Celsius • CY7C63612/13 available in 24-pin SOIC packages for production • Industry-standard programmer support FO R FO R CY7C63612/13 Functional Overview The CY7C63612/13 are 8-bit RISC One Time Programmable OTP microcontrollers. The instruction set has been optimized specifically for USB operations, although the microcontrollers can be used for a variety of non-USB embedded applications. The CY7C63612/13 features 16 General-Purpose I/O GPIO pins to support USB and other applications. The I/O pins are grouped into three ports Port 0, 1, and 3 where each port can be configured as inputs with internal pull-ups, open drain outp uts, or traditional CMOS outputs. 12 GPIO pins Ports 0 and 1 are rated at 7 mA typical sink current. There are 4 GPIO pins Port 3 which are rated at 12 mA typical sink current, which allows these pins to drive LEDs. Multiple GPIO pins can be connected together to drive a single output for more drive current capacity. Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcontroller. Note the GPIO interrupts all share the same “GPIO” interrupt vector. The Cypress microcontrollers use an external 6-MHz ceramic resonator to provide a reference to an internal clock generator. This clock generator reduces the clock-related noise emissions EMI . The clock generator provides the 6- and 12-MHz clocks that remain internal to the microcontroller. The CY7C63612/13 are offered with two EPROM options to maximize flexibility and minimize cost. The CY7C63612 has 6 Kbytes of EPROM. The CY7C63613 has 8 Kbytes of EPROM. These parts include power-on reset logic, a watch dog timer, a vectored interrupt controller, and a 12-bit free-running timer. The Power-On Reset POR logic detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at EPROM address 0x0000h. The watch dog timer can be used to ensure the firmware never gets stalled for more than approximately 8 ms. The firmware can get stalled for a variety of reasons, including errors in the code or a hardware failure such as waiting for an interrupt that never occurs. The firmware should clear the watchdog timer periodically. If the watch dog timer is not cleared for approximately 8 ms, the microcontroller will generate a hardware watch dog reset. The microcontroller supports eight maskable interrupts in the vectored interrupt controller. Interrupt sources include the USB BusReset, the 128-µs and 1.024-ms outputs from the free-running timer, three USB endpoints, the DAC port, and the GPIO ports. The timer bits cause an interrupt if enabled when the bit toggles from LOW “0” to HIGH The USB endpoints interrupt after either the USB host or the USB controller sends a packet to the USB. The DAC ports have an additional level of masking that allows the user to select which DAC inputs can cause a DAC interrupt. The GPIO ports also have a level of masking to select which GPIO inputs can cause a GPIO interrupt. For additional flexibility, the input transition polarity that causes an interrupt is programmable for each pin of the DAC port. Input transition polarity can be programmed for each GPIO port as part of the port configuration. The interrupt polarity can be either rising edge “0” to “1” or falling edge “1” to The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources as noted above 128-µs and 1.024-ms . The timer can be used to measure the duration of an event under firmware control by reading the timer twice once at the start of the event, and once after the event is complete. The difference between the two readings indicates the duration of the event measured in microseconds. The upper four bits of the timer are latched into an internal register when the firmware reads the lower eight bits. A read from the upper four bits actually reads data from the internal register, instead of the timer. This feature eliminates the need for firmware to attempt to compensate if the upper four bits happened to increment right after the lower 8 bits are read. The CY7C63612/13 include an integrated USB serial interface engine SIE that supports the integrated peripherals. The hardware supports one USB device address with three endpoints. The SIE allows the USB host to communicate with the function integrated into the microcontroller. Finally, the CY7C63612/13 support PS/2 operation. With appropriate firmware the D+ and USB pins can also be used as PS/ 2 clock and data signals. Products utilizing these devices can be used for USB and/or PS/2 operation with appropriate firmware. FO R FO R Logic Block Diagram 6-MHz ceramic resonator 12 MHz 6 MHz 12-MHz 8-bit CPU USB Transceiver D+ USB PS/2 PORT EPROM 4/6/8 Kbyte USB SIE 8-bit Bus RAM 256 byte 12-bit Timer Watch Dog Timer Ordering Information Ordering Code EPROM Package Size Name CY7C63612-SC CY7C63613-SC Package Type 24-Pin 300-Mil SOIC 24-Pin 300-Mil SOIC Document # 38-00754 Package Diagram 24-Lead 300-Mil Molded SOIC S13 Operating Range Commercial Commercial 51-85025-A Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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CY7C63612/13

CY7C63612/13 Low-Speed, Low I/O Mbps USB Controller

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose
• CA 95134
• 408-943-2600 March 26, 1999

FO R FO R

CY7C63612/13

TABLE OF CONTENTS

FEATURES 5

FUNCTIONAL OVERVIEW 6

PIN ASSIGNMENTS 8

PROGRAMMING MODEL 8 14-bit Program Counter PC 8-bit Accumulator A 8-bit Index Register X 8-bit Program Stack Pointer PSP 8-bit Data Stack Pointer DSP 9 Address Modes 9

Data 9 Direct 9 Indexed 9

INSTRUCTION SET SUMMARY

MEMORY ORGANIZATION Program Memory Organization 11 Data Memory Organization 12 I/O Register Summary 13

CLOCKING

RESET Power-On Reset POR 14 Watch Dog Reset WDR 15

GENERAL PURPOSE I/O PORTS GPIO Interrupt Enable Ports GPIO Configuration Port 17

USB SERIAL INTERFACE ENGINE SIE USB Enumeration 18 PS/2 Operation 18 USB Port Status and Control

USB DEVICE 19 USB Ports Device Endpoints 3 19
12-BIT FREE-RUNNING TIMER 20 Timer LSB 20 Timer MSB

PROCESSOR STATUS AND CONTROL REGISTER 21

INTERRUPTS 21 Interrupt Vectors 22 Interrupt Latency 22

USB Bus Reset Interrupt Timer Interrupt 23

FO R FO R

CY7C63612/13

TABLE OF CONTENTS continued
USB Endpoint Interrupts 23 DAC Interrupt 23 GPIO Interrupt 23 TRUTH TABLES ABSOLUTE MAXIMUM RATINGS 26 DC CHARACTERISTICS 27 SWITCHING CHARACTERISTICS 28 ORDERING INFORMATION PACKAGE DIAGRAM 30

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CY7C63612/13

LIST OF FIGURES

Figure Program Memory Space with Interrupt Vector Table 11 Figure Clock Oscillator On-chip Circuit 14 Figure Watch Dog Reset WDR 15 Figure Block Diagram of a GPIO Line 15 Figure Port 0 Data 0x00h read/write 16 Figure Port 1 Data 0x01h read/write 16 Figure Port 2 Data 0x02h read/write 16 Figure Port 3 Data 0x03h read/write 16 Figure DAC Port Data 0x30h read/write 16 Figure Port 0 Interrupt Enable 0x04h write only 16 Figure Port 1 Interrupt Enable 0x05h write only 16 Figure Port 2 Interrupt Enable 0x06h write only 16 Figure Port 3 Interrupt Enable 0x07h write only 16 Figure GPIO Configuration Register 0x08h write only 17 Figure USB Status and Control Register 0x1Fh 18 Figure USB Device Address Register 0x10h read/write 19 Figure USB Device EPA0 Mode Register 0x12h read/write 19 Figure USB Device Endpoint Mode Registers 0x14h, 0x16h read/write 19 Figure USB Device Counter Registers 0x11h, 0x13h, 0x15h read/write 20 Figure Timer Register 0x24h read only 20 Figure Timer Register 0x25h read only 20 Figure Timer Block Diagram 20 Figure Processor Status and Control Register 0xFFh 21 Figure Global Interrupt Enable Register 0x20h read/write 21 Figure USB End Point Interrupt Enable Register 0x21h read/write 22 Figure Clock Timing 28 Figure USB Data Signal Timing 29 Figure Receiver Jitter Tolerance 29 Figure Differential to EOP Transition Skew and EOP Width 29 Figure Differential Data Jitter 30

LIST OF TABLES

Table I/O Register Summary 13 Table Interrupt Vector Assignments 22 Table USB Register Mode Encoding 23 Table Decode table forTable 15-3 “Details of Modes for Differing Traffic Conditions” Table Details of Modes for Differing Traffic Conditions 25

FO R FO R

CY7C63612/13
• Low-cost solution for low-speed applications with low I/O requirements such as mice, gamepads, and joystick applications
• USB Specification Compliance Conforms to USB Specification, Version Conforms to USB HID Specification, Version Supports 1 device address and 3 data endpoints Integrated USB transceiver
• 8-bit RISC microcontroller Harvard architecture 6-MHz external ceramic resonator 12-MHz internal CPU clock
• Internal memory 256 bytes of RAM 6 Kbytes of EPROM CY7C63612 8 Kbytes of EPROM CY7C63613
• Interface can auto-configure to operate as PS2 or USB
• I/O port
12 General-Purpose I/O GPIO pins Port 0 to 2 capable of sinking 7 mA per pin typical Four GPIO pins Port 3 capable of sinking 12 mA per pin typical which can drive LEDs Higher current drive is available by connecting multiple GPIO pins together to drive an common output Each GPIO port can be configured as inputs with internal pull-ups or open drain outputs or traditional CMOS outputs Maskable interrupts on all I/O pins
• 12-bit free-running timer with one microsecond clock ticks
• Watch Dog Timer WDT
• Internal Power-On Reset POR
• Improved output drivers to reduce EMI
• Operating voltage from 4.0V to 5.5V DC
• Operating temperature from 0 to 70 degrees Celsius
• CY7C63612/13 available in 24-pin SOIC packages for production
• Industry-standard programmer support

FO R FO R

CY7C63612/13

Functional Overview

The CY7C63612/13 are 8-bit RISC One Time Programmable OTP microcontrollers. The instruction set has been optimized specifically for USB operations, although the microcontrollers can be used for a variety of non-USB embedded applications.

The CY7C63612/13 features 16 General-Purpose I/O GPIO pins to support USB and other applications. The I/O pins are grouped into three ports Port 0, 1, and 3 where each port can be configured as inputs with internal pull-ups, open drain outp uts, or traditional CMOS outputs. 12 GPIO pins Ports 0 and 1 are rated at 7 mA typical sink current. There are 4 GPIO pins Port 3 which are rated at 12 mA typical sink current, which allows these pins to drive LEDs. Multiple GPIO pins can be connected together to drive a single output for more drive current capacity. Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcontroller. Note the GPIO interrupts all share the same “GPIO” interrupt vector.

The Cypress microcontrollers use an external 6-MHz ceramic resonator to provide a reference to an internal clock generator. This clock generator reduces the clock-related noise emissions EMI . The clock generator provides the 6- and 12-MHz clocks that remain internal to the microcontroller.

The CY7C63612/13 are offered with two EPROM options to maximize flexibility and minimize cost. The CY7C63612 has 6 Kbytes of EPROM. The CY7C63613 has 8 Kbytes of EPROM.

These parts include power-on reset logic, a watch dog timer, a vectored interrupt controller, and a 12-bit free-running timer. The Power-On Reset POR logic detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at EPROM address 0x0000h. The watch dog timer can be used to ensure the firmware never gets stalled for more than approximately 8 ms. The firmware can get stalled for a variety of reasons, including errors in the code or a hardware failure such as waiting for an interrupt that never occurs. The firmware should clear the watchdog timer periodically. If the watch dog timer is not cleared for approximately 8 ms, the microcontroller will generate a hardware watch dog reset.

The microcontroller supports eight maskable interrupts in the vectored interrupt controller. Interrupt sources include the USB BusReset, the 128-µs and 1.024-ms outputs from the free-running timer, three USB endpoints, the DAC port, and the GPIO ports. The timer bits cause an interrupt if enabled when the bit toggles from LOW “0” to HIGH The USB endpoints interrupt after either the USB host or the USB controller sends a packet to the USB. The DAC ports have an additional level of masking that allows the user to select which DAC inputs can cause a DAC interrupt. The GPIO ports also have a level of masking to select which GPIO inputs can cause a GPIO interrupt. For additional flexibility, the input transition polarity that causes an interrupt is programmable for each pin of the DAC port. Input transition polarity can be programmed for each GPIO port as part of the port configuration. The interrupt polarity can be either rising edge “0” to “1” or falling edge “1” to

The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources as noted above 128-µs and 1.024-ms . The timer can be used to measure the duration of an event under firmware control by reading the timer twice once at the start of the event, and once after the event is complete. The difference between the two readings indicates the duration of the event measured in microseconds. The upper four bits of the timer are latched into an internal register when the firmware reads the lower eight bits. A read from the upper four bits actually reads data from the internal register, instead of the timer. This feature eliminates the need for firmware to attempt to compensate if the upper four bits happened to increment right after the lower 8 bits are read.

The CY7C63612/13 include an integrated USB serial interface engine SIE that supports the integrated peripherals. The hardware supports one USB device address with three endpoints. The SIE allows the USB host to communicate with the function integrated into the microcontroller.

Finally, the CY7C63612/13 support PS/2 operation. With appropriate firmware the D+ and USB pins can also be used as PS/ 2 clock and data signals. Products utilizing these devices can be used for USB and/or PS/2 operation with appropriate firmware.

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Logic Block Diagram
6-MHz ceramic resonator
12 MHz 6 MHz
12-MHz 8-bit CPU

USB Transceiver

D+ USB

PS/2 PORT

EPROM 4/6/8 Kbyte

USB SIE
8-bit Bus

RAM 256 byte
12-bit Timer

Watch Dog Timer
Ordering Information
Ordering Code

EPROM Package

Size

Name

CY7C63612-SC

CY7C63613-SC

Package Type 24-Pin 300-Mil SOIC 24-Pin 300-Mil SOIC

Document # 38-00754

Package Diagram
24-Lead 300-Mil Molded SOIC S13

Operating Range

Commercial

Commercial
51-85025-A

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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Datasheet ID: CY7C63613-SC 508124