CY7C63903-PVXC

CY7C63903-PVXC Datasheet

CY7C63310 CY7C638xx CY7C639xx

Part	Datasheet
CY7C63903-PVXC	CY7C63903-PVXC (pdf)

Related Parts	Information
CY7C63923-PVXC	CY7C63923-PVXC
CY7C63913-PXC	CY7C63913-PXC

PDF Datasheet Preview
CY7C63310 CY7C638xx CY7C639xx enCoRe II Low-Speed USB Peripheral Controller • II Component Reduction” Crystalless oscillator with support for an external crystal or resonator. The internal oscillator eliminates the need for an external crystal or resonator Internal 3.3V regulator and internal USB pull-up resistor Configurable IO for real-world interface without external components • USB Specification Compliance Conforms to USB Specification, Version Conforms to USB HID Specification, Version Supports one Low-Speed USB device address Supports one control endpoint and two data endpoints Integrated USB transceiver • Enhanced 8-bit microcontroller Harvard architecture M8C CPU speed can be up to 24 MHz or sourced by an external crystal, resonator, or signal • Internal memory Up to 256 bytes of RAM Up to eight Kbytes of Flash including EEROM emulation • Interface can auto-configure to operate as PS/2 or USB No external components for switching between PS/2 and USB modes No GPIO pins needed to manage dual-mode capability • Low power consumption Typically 10 mA at 6 MHz 10-µA sleep • In-system re-programmability Allows easy firmware update • General-purpose I/O ports Up to 36 General Purpose I/O GPIO pins High current drive on GPIO pins. Configurable 8- or 50-mA/pin current sink on designated pins Each GPIO port supports high-impedance inputs, configurable pull-up, open drain output, CMOS/TTL inputs, and CMOS output Maskable interrupts on all I/O pins • 125-mA 3.3V voltage regulator can power external 3.3V devices • 3.3V I/O pins 4 I/O pins with 3.3V logic levels Each 3.3V pin supports high-impedance input, internal pull-up, open drain output or traditional CMOS output • SPI serial communication Master or slave operation Configurable up to 2-Mbit/second transfers Supports half duplex single data line mode for optical sensors • 2-channel 8-bit or 1-channel 16-bit capture timer. Capture timers registers store both rising and falling edge times Two registers each for two input pins Separate registers for rising and falling edge capture Simplifies interface to RF inputs for wireless applications • Internal low-power wake-up timer during suspend mode Periodic wake-up with no external components • Programmable Interval Timer interrupts • Reduced RF emissions at 27 MHz and 96 MHz • Advanced development tools based on Cypress MicroSystems PSoC tools • Watchdog timer WDT • Low-voltage detection with user-configurable threshold voltages • Improved output drivers to reduce EMI • Operating voltage from 4.0V to 5.25VDC • Operating temperature from • Available in 16/18/24/40-pin PDIP, 16/18/24-pin SOIC, 24- pin QSOP, 28/48-pin SSOP, and DIE form • Industry standard programmer support The CY7C633xx/CY7C638xx/CY7C639xx is targeted for the following applications • PC HID devices Mice optomechanical, optical, trackball Keyboards • Gaming Joysticks Game pads Ordering Information Ordering Code CY7C63923-PVXC CY7C63913-PXC CY7C63903-PVXC CY7C63923-XWC CY7C63823-PXC CY7C63823-SXC CY7C63823-QXC CY7C63813-PXC CY7C63813-SXC CY7C63803-SXC CY7C63801-PXC CY7C63801-SXC CY7C63310-PXC CY7C63310-SXC Package Diagrams CY7C63310 CY7C638xx CY7C639xx FLASH Size 8K 4K 3K RAM Size 256 128 48-SSOP 40-PDIP 28-SSOP Die 24-PDIP 24-SOIC 24-QSOP 18-PDIP 18-SOIC 16-SOIC 16-PDIP 16-SOIC 16-PDIP 16-SOIC Package Type 16-Lead 300-Mil Molded DIP P1 51-85009-A Page 62 of 68 CY7C63310 CY7C638xx CY7C639xx Package Diagrams continued 16 Lead 150 Mil SOIC 16-Lead 150-Mil SOIC S16.15 PIN 1 ID DIMENSIONS IN INCHES[MM] MIN. REFERENCE JEDEC MS-012 PACKAGE WEIGHT 0.15gms PART # S16.15 STANDARD PKG. SZ16.15 LEAD FREE PKG. MAX. SEATING PLANE 0° ~8° 18-Lead 300-Mil Molded DIP P3 X 45° 51-85068-B 51-85010-A Page 63 of 68 Package Diagrams continued 18 Lead 30108-MLeiald S 3O00IC-M-il SM3olded SOIC S3 PIN 1 ID CY7C63310 CY7C638xx CY7C639xx DIMENSIONS IN INCHES[MM] REFERENCE JEDEC MO-119 MIN. MAX. PART # S18.3 STANDARD PKG. SZ18.3 LEAD FREE PKG. SEATING PLANE TYP. TYP. 24 Lead 3002M4-Lile aSdO 3I0C0--MSil1 S3OIC S13 PIN 1 ID 51-85023-B

PDF Datasheet Preview

CY7C63310 CY7C638xx CY7C639xx
enCoRe II Low-Speed USB Peripheral Controller
• II Component Reduction” Crystalless oscillator with support for an external crystal or resonator. The internal oscillator eliminates the need for an external crystal or resonator

Internal 3.3V regulator and internal USB pull-up resistor

Configurable IO for real-world interface without external components
• USB Specification Compliance Conforms to USB Specification, Version

Conforms to USB HID Specification, Version

Supports one Low-Speed USB device address

Supports one control endpoint and two data endpoints

Integrated USB transceiver
• Enhanced 8-bit microcontroller

Harvard architecture

M8C CPU speed can be up to 24 MHz or sourced by an external crystal, resonator, or signal
• Internal memory Up to 256 bytes of RAM

Up to eight Kbytes of Flash including EEROM emulation
• Interface can auto-configure to operate as PS/2 or USB No external components for switching between PS/2 and USB modes

No GPIO pins needed to manage dual-mode capability
• Low power consumption Typically 10 mA at 6 MHz
10-µA sleep
• In-system re-programmability

Allows easy firmware update
• General-purpose I/O ports

Up to 36 General Purpose I/O GPIO pins

High current drive on GPIO pins. Configurable 8- or 50-mA/pin current sink on designated pins

Each GPIO port supports high-impedance inputs, configurable pull-up, open drain output, CMOS/TTL inputs, and CMOS output

Maskable interrupts on all I/O pins
• 125-mA 3.3V voltage regulator can power external 3.3V
devices
• 3.3V I/O pins
4 I/O pins with 3.3V logic levels

Each 3.3V pin supports high-impedance input, internal pull-up, open drain output or traditional CMOS output
• SPI serial communication Master or slave operation

Configurable up to 2-Mbit/second transfers

Supports half duplex single data line mode for optical sensors
• 2-channel 8-bit or 1-channel 16-bit capture timer. Capture timers registers store both rising and falling edge times Two registers each for two input pins Separate registers for rising and falling edge capture

Simplifies interface to RF inputs for wireless applications
• Internal low-power wake-up timer during suspend mode Periodic wake-up with no external components
• Programmable Interval Timer interrupts
• Reduced RF emissions at 27 MHz and 96 MHz
• Advanced development tools based on Cypress

MicroSystems PSoC tools
• Watchdog timer WDT
• Low-voltage detection with user-configurable
threshold voltages
• Improved output drivers to reduce EMI
• Operating voltage from 4.0V to 5.25VDC
• Operating temperature from
• Available in 16/18/24/40-pin PDIP, 16/18/24-pin SOIC, 24-
pin QSOP, 28/48-pin SSOP, and DIE form
• Industry standard programmer support

The CY7C633xx/CY7C638xx/CY7C639xx is targeted for the following applications
• PC HID devices

Mice optomechanical, optical, trackball

Keyboards
• Gaming

Joysticks

Game pads
Ordering Information
Ordering Code CY7C63923-PVXC CY7C63913-PXC CY7C63903-PVXC CY7C63923-XWC CY7C63823-PXC CY7C63823-SXC CY7C63823-QXC CY7C63813-PXC CY7C63813-SXC CY7C63803-SXC CY7C63801-PXC CY7C63801-SXC CY7C63310-PXC CY7C63310-SXC

Package Diagrams

CY7C63310 CY7C638xx CY7C639xx

FLASH Size 8K 4K 3K

RAM Size 256 128
48-SSOP 40-PDIP 28-SSOP Die 24-PDIP 24-SOIC 24-QSOP 18-PDIP 18-SOIC 16-SOIC 16-PDIP 16-SOIC 16-PDIP 16-SOIC

Package Type
16-Lead 300-Mil Molded DIP P1
51-85009-*A

Page 62 of 68

CY7C63310 CY7C638xx CY7C639xx

Package Diagrams continued
16 Lead 150 Mil SOIC
16-Lead 150-Mil SOIC S16.15

PIN 1 ID

DIMENSIONS IN INCHES[MM] MIN.

REFERENCE JEDEC MS-012

PACKAGE WEIGHT 0.15gms PART #

S16.15 STANDARD PKG.

SZ16.15 LEAD FREE PKG.

MAX.

SEATING PLANE
0° ~8°
18-Lead 300-Mil Molded DIP P3

X 45°
51-85068-*B
51-85010-*A

Page 63 of 68

Package Diagrams continued
18 Lead 30108-MLeiald S 3O00IC-M-il SM3olded SOIC S3

PIN 1 ID

CY7C63310 CY7C638xx CY7C639xx

DIMENSIONS IN INCHES[MM] REFERENCE JEDEC MO-119

MIN. MAX.

PART # S18.3 STANDARD PKG. SZ18.3 LEAD FREE PKG.

SEATING PLANE

TYP.

TYP.
24 Lead 3002M4-Lile aSdO 3I0C0--MSil1 S3OIC S13

PIN 1 ID
51-85023-*B

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C63903-PVXC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C63903-PVXC 508122