CY7C4215-15AXI

CY7C4215-15AXI Datasheet

CY7C4425/4205/4215 CY7C4225/4235/4245

Part	Datasheet
CY7C4215-15AXI	CY7C4215-15AXI (pdf)

Related Parts	Information
CY7C4225-15AXC	CY7C4225-15AXC
CY7C4215-15AXIT	CY7C4215-15AXIT
CY7C4225-10AXI	CY7C4225-10AXI
CY7C4225-15ASXC	CY7C4225-15ASXC
CY7C4225-15AXCT	CY7C4225-15AXCT

PDF Datasheet Preview
CY7C4425/4205/4215 CY7C4225/4235/4245 64/256/512/1K/2K/4K x 18 Synchronous FIFOs • High speed, low power, first-in first-out FIFO memories • 64 x 18 CY7C4425 • 256 x 18 CY7C4205 • 512 x 18 CY7C4215 • 1K x 18 CY7C4225 • 2K x 18 CY7C4235 • 4K x 18 CY7C4245 • High speed 100 MHz operation 10 ns read/write cycle time • Low power ICC = 45 mA • Fully asynchronous and simultaneous read and write operation • Empty, Full, Half Full, and Programmable Almost Empty/Almost Full status flags • TTL compatible • Retransmit function • Output Enable OE pin • Independent read and write enable pins • Center power and ground for reduced noise • Supports free running 50% duty cycle clock inputs • Width Expansion Capability • Depth Expansion Capability • Available in 64 pin 14 x 14 TQFP, 64 pin 10 x 10 TQFP, and 68-pin PLCC Functional Description The CY7C42X5 are high speed, low power, first-in first-out FIFO memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to IDT722X5. The CY7C42X5 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high speed data acquisition, multiprocessor interfaces, and communications buffering. These FIFOs have 18-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock WCLK and a write enable pin WEN . When WEN is asserted, data is written into the FIFO on the rising edge of the WCLK signal. While WEN is held active, data is continually written into the FIFO on each cycle. The output port is controlled in a similar manner by a free-running read clock RCLK and a read enable pin REN . In addition, the CY7C42X5 have an output enable pin OE . The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable. Retransmit and Synchronous Almost Full/Almost Empty flag features are available on these devices. Depth expansion is possible using the cascade input WXI, RXI , cascade output WXO, RXO , and First Load FL pins. The WXO and RXO pins are connected to the WXI and RXI pins of the next device, and the WXO and RXO pins of the last device should be connected to the WXI and RXI pins of the first device. The FL pin of the first device is tied to VSS and the FL pin of all the remaining devices should be tied to VCC. The CY7C42X5 provides five status pins. These pins are decoded to determine one of five states Empty, Almost Empty, Half Full, Almost Full, and Full see Table The Half Full flag shares the WXO pin. This flag is valid in the standalone and width-expansion configurations. In the depth expansion, this pin provides the expansion out WXO information that is used to signal the next FIFO when it will be activated. The Empty and Full flags are synchronous, i.e., they change state relative to either the read clock RCLK or the write clock WCLK . When entering or exiting the Empty states, the flag is updated exclusively by the RCLK. The flag denoting Full states is updated exclusively by WCLK. The synchronous flag architecture guarantees that the flags will remain valid from one clock cycle to the next. As mentioned previously, the Almost Empty/Almost Full flags become synchronous if the VCC/SMODE is tied to VSS. All configurations are fabricated using an advanced 0.65m N-Well CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Logic Block Diagram WCLK WRITE CONTROL FL/RT WXI WXO/HF RXI RXO WRITE POINTER RESET LOGIC EXPANSION LOGIC Pin Configuration Figure TQFP Top View CY7C4425/4205/4215 CY7C4225/4235/4245 INPUT REGISTER RAM ARRAY 64 x 18 256 x 18 512 x 18 1K x 18 2K x 18 4K x 18 FLAG PROGRAM REGISTER FLAG LOGIC READ POINTER FF EF PAF SMODE OUTPUT REGISTER READ CONTROL RCLK Figure PLCC Top View D15 D16 D17 GND RCLK REN LD OE RS VCC GND EF VCC Q17 Q16 GND Q15 VCC/SMODE RCLK CY7C4425 CY7C4205 CY7C4215 CY7C4225 CY7C4235 CY7C4245 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 Ordering Information 256 x 18 Synchronous FIFO Speed ns Ordering Code CY7C4205-10AXC 512 x 18 Synchronous FIFO Speed ns Ordering Code CY7C4215-15AXI 1K x 18 Synchronous FIFO Speed ns Ordering Code CY7C4225-10AXI CY7C4225-15AXC CY7C4225-15ASXC 4K x 18 Synchronous FIFO Speed ns Ordering Code CY7C4245-10AXI CY7C4245-15AXC CY7C4245-15ASXC Package Name 51-85046 Package Type 64-Pin 14 x 14 Thin Quad Flatpack Pb-Free Package Name 51-85046 Package Type 64-Pin 14 x 14 Thin Quad Flatpack Pb-Free Package Name 51-85046 51-85046 51-85051 Package Type 64-Pin 14 x 14 Thin Quad Flatpack Pb-Free 64-Pin 14 x 14 Thin Quad Flatpack Pb-Free 64-Pin 10 x 10 Thin Quad Flatpack Pb-Free Package Name 51-85046 51-85046 51-85051 Package Type 64-Pin 14 x 14 Thin Quad Flatpack Pb-Free 64-Pin 14 x 14 Thin Quad Flatpack Pb-Free 64-Pin 10 x 10 Thin Quad Flatpack Pb-Free Ordering Code Definitions CY 7 C 4 2X 5 XX X C, I Temperature Grade C = Commercial, I = Industrial Pb-free RoHS Compliant Package A = TQFP, AS = STQFP, J = PLCC Speed grade 10 ns or 15 ns x18 Depth 20 = 256 b 21 = 512 b 22 = 1 K 23 = 2 K 24 = 4 K FIFO Technology CMOS Family Dual-port SRAM Company ID CY = Cypress Operating Range Commercial Operating Range Industrial Operating Range Industrial Commercial Operating Range Industrial Commercial Page 19 of 22 [+] Feedback CY7C4425/4205/4215 CY7C4225/4235/4245 Package Diagrams Figure 64-Pin Thin Plastic Quad Flat Pack 14 x 14 x mm , 51-85046 51-85046 D Page 20 of 22 [+] Feedback CY7C4425/4205/4215 CY7C4225/4235/4245 Package Diagrams continued Figure 64-Pin Thin Plastic Quad Flat Pack 10 x 10 x mm , 51-85051 Figure 68-Pin Plastic Leaded Chip Carrier, 51-85005 51-85051 B 51-85005 *B Page 21 of 22 [+] Feedback CY7C4425/4205/4215 CY7C4225/4235/4245 Document History Page Document Title 64/256/512/1K/2K/4K x 18 Synchronous FIFOs Document Number 001-45652 Orig. of ECN NO. Issue Date Change Description of Change 2489087 See ECN VKN This document is recreated from the existing pdf file on web. This is provided a new spec number. 3094407 11/24/10 ADMU Removed following invalid parts from the ordering information table. CY7C4205-15AC CY7C4205-15AXC CY7C4215-15AI CY7C4225-10AI CY7C4225-15ASC CY7C4235-15AXC CY7C4245-10AI CY7C4245-10AXC CY7C4245-10ASXC CY7C4245-15JXC Added ordering code definitions. Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. All product and company names mentioned in this document are the trademarks of their respective holders. Page 22 of 22 [+] Feedback

PDF Datasheet Preview

CY7C4425/4205/4215 CY7C4225/4235/4245
64/256/512/1K/2K/4K x 18 Synchronous FIFOs
• High speed, low power, first-in first-out FIFO memories
• 64 x 18 CY7C4425
• 256 x 18 CY7C4205
• 512 x 18 CY7C4215
• 1K x 18 CY7C4225
• 2K x 18 CY7C4235
• 4K x 18 CY7C4245
• High speed 100 MHz operation 10 ns read/write cycle time
• Low power ICC = 45 mA
• Fully asynchronous and simultaneous read and write operation
• Empty, Full, Half Full, and Programmable Almost Empty/Almost

Full status flags
• TTL compatible
• Retransmit function
• Output Enable OE pin
• Independent read and write enable pins
• Center power and ground for reduced noise
• Supports free running 50% duty cycle clock inputs
• Width Expansion Capability
• Depth Expansion Capability
• Available in 64 pin 14 x 14 TQFP, 64 pin 10 x 10 TQFP, and
68-pin PLCC

Functional Description

The CY7C42X5 are high speed, low power, first-in first-out FIFO memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to IDT722X5. The CY7C42X5 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high speed data acquisition, multiprocessor interfaces, and communications buffering.

These FIFOs have 18-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock WCLK and a write enable pin WEN . When WEN is asserted, data is written into the FIFO on the rising edge of the WCLK signal. While WEN is held active, data is continually written into the FIFO on each cycle. The output port is controlled in a similar manner by a free-running read clock RCLK and a read enable pin REN . In addition, the CY7C42X5 have an output enable pin OE . The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable.

Retransmit and Synchronous Almost Full/Almost Empty flag features are available on these devices.

Depth expansion is possible using the cascade input WXI, RXI , cascade output WXO, RXO , and First Load FL pins. The WXO and RXO pins are connected to the WXI and RXI pins of the next device, and the WXO and RXO pins of the last device should be connected to the WXI and RXI pins of the first device. The FL pin of the first device is tied to VSS and the FL pin of all the remaining devices should be tied to VCC.

The CY7C42X5 provides five status pins. These pins are decoded to determine one of five states Empty, Almost Empty, Half Full, Almost Full, and Full see Table The Half Full flag shares the WXO pin. This flag is valid in the standalone and width-expansion configurations. In the depth expansion, this pin provides the expansion out WXO information that is used to signal the next FIFO when it will be activated.

The Empty and Full flags are synchronous, i.e., they change state relative to either the read clock RCLK or the write clock WCLK . When entering or exiting the Empty states, the flag is updated exclusively by the RCLK. The flag denoting Full states is updated exclusively by WCLK. The synchronous flag architecture guarantees that the flags will remain valid from one clock cycle to the next. As mentioned previously, the Almost Empty/Almost Full flags become synchronous if the VCC/SMODE is tied to VSS. All configurations are fabricated using an advanced 0.65m N-Well CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings.
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

Logic Block Diagram

WCLK

WRITE CONTROL

FL/RT WXI

WXO/HF RXI RXO

WRITE POINTER

RESET LOGIC

EXPANSION LOGIC

Pin Configuration

Figure TQFP Top View

CY7C4425/4205/4215 CY7C4225/4235/4245

INPUT REGISTER

RAM ARRAY 64 x 18 256 x 18 512 x 18 1K x 18 2K x 18 4K x 18

FLAG PROGRAM REGISTER

FLAG LOGIC

READ POINTER

FF EF

PAF SMODE

OUTPUT REGISTER

READ CONTROL

RCLK

Figure PLCC Top View

D15 D16 D17 GND RCLK REN LD OE RS VCC GND EF VCC Q17 Q16 GND Q15

VCC/SMODE

RCLK

CY7C4425 CY7C4205 CY7C4215 CY7C4225 CY7C4235 CY7C4245
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
Ordering Information
256 x 18 Synchronous FIFO

Speed ns
Ordering Code

CY7C4205-10AXC
512 x 18 Synchronous FIFO

Speed ns
Ordering Code

CY7C4215-15AXI
1K x 18 Synchronous FIFO

Speed ns
Ordering Code

CY7C4225-10AXI

CY7C4225-15AXC

CY7C4225-15ASXC
4K x 18 Synchronous FIFO

Speed ns
Ordering Code

CY7C4245-10AXI

CY7C4245-15AXC

CY7C4245-15ASXC

Package Name
51-85046

Package Type
64-Pin 14 x 14 Thin Quad Flatpack Pb-Free

Package Name
51-85046

Package Type
64-Pin 14 x 14 Thin Quad Flatpack Pb-Free

Package Name
51-85046
51-85046
51-85051

Package Type
64-Pin 14 x 14 Thin Quad Flatpack Pb-Free
64-Pin 14 x 14 Thin Quad Flatpack Pb-Free
64-Pin 10 x 10 Thin Quad Flatpack Pb-Free

Package Name
51-85046
51-85046
51-85051

Package Type
64-Pin 14 x 14 Thin Quad Flatpack Pb-Free
64-Pin 14 x 14 Thin Quad Flatpack Pb-Free
64-Pin 10 x 10 Thin Quad Flatpack Pb-Free
Ordering Code Definitions

CY 7 C 4 2X 5 XX X C, I Temperature Grade C = Commercial, I = Industrial

Pb-free RoHS Compliant

Package A = TQFP, AS = STQFP, J = PLCC Speed grade 10 ns or 15 ns x18 Depth 20 = 256 b 21 = 512 b 22 = 1 K 23 = 2 K 24 = 4 K FIFO Technology CMOS

Family Dual-port SRAM

Company ID CY = Cypress

Operating Range

Commercial

Operating Range Industrial

Operating Range Industrial

Commercial

Operating Range Industrial

Commercial

Page 19 of 22 [+] Feedback

CY7C4425/4205/4215 CY7C4225/4235/4245

Package Diagrams

Figure 64-Pin Thin Plastic Quad Flat Pack 14 x 14 x mm , 51-85046
51-85046 *D

Page 20 of 22 [+] Feedback

CY7C4425/4205/4215 CY7C4225/4235/4245

Package Diagrams continued

Figure 64-Pin Thin Plastic Quad Flat Pack 10 x 10 x mm , 51-85051

Figure 68-Pin Plastic Leaded Chip Carrier, 51-85005
51-85051 *B
51-85005 *B

Page 21 of 22 [+] Feedback

CY7C4425/4205/4215 CY7C4225/4235/4245

Document History Page

Document Title 64/256/512/1K/2K/4K x 18 Synchronous FIFOs Document Number 001-45652

Orig. of ECN NO. Issue Date Change

Description of Change
2489087 See ECN

VKN This document is recreated from the existing pdf file on web. This is provided a
new spec number.
3094407 11/24/10 ADMU Removed following invalid parts from the ordering information table.

CY7C4205-15AC

CY7C4205-15AXC

CY7C4215-15AI

CY7C4225-10AI

CY7C4225-15ASC

CY7C4235-15AXC

CY7C4245-10AI

CY7C4245-10AXC

CY7C4245-10ASXC

CY7C4245-15JXC
Added ordering code definitions.

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

All product and company names mentioned in this document are the trademarks of their respective holders.

Page 22 of 22
[+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C4215-15AXI Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C4215-15AXI 508114