CY7C4245-10AXCT

CY7C4245-10AXCT Datasheet

CY7C4425/4205/4215 CY7C4225/4235/4245

Part	Datasheet
CY7C4245-10AXCT	CY7C4245-10AXCT (pdf)

Related Parts	Information
CY7C4205-10AXC	CY7C4205-10AXC
CY7C4235-15AXC	CY7C4235-15AXC
CY7C4245-10ASXC	CY7C4245-10ASXC
CY7C4235-15AXCT	CY7C4235-15AXCT
CY7C4205-10AXCT	CY7C4205-10AXCT
CY7C4205-15AXC	CY7C4205-15AXC
CY7C4205-15AXCT	CY7C4205-15AXCT
CY7C4245-15JXCT	CY7C4245-15JXCT
CY7C4245-15AXCT	CY7C4245-15AXCT
CY7C4245-10AXI	CY7C4245-10AXI
CY7C4245-15ASXC	CY7C4245-15ASXC
CY7C4245-15AXC	CY7C4245-15AXC
CY7C4245-10AXC	CY7C4245-10AXC
CY7C4245-10ASXCT	CY7C4245-10ASXCT
CY7C4235-15AC	CY7C4235-15AC
CY7C4245-15JXC	CY7C4245-15JXC

PDF Datasheet Preview
CY7C4425/4205/4215 CY7C4225/4235/4245 64/256/512/1K/2K/4K x 18 Synchronous FIFOs • High speed, low power, first-in first-out FIFO memories • 64 x 18 CY7C4425 • 256 x 18 CY7C4205 • 512 x 18 CY7C4215 • 1K x 18 CY7C4225 • 2K x 18 CY7C4235 • 4K x 18 CY7C4245 • High speed 100 MHz operation 10 ns read/write cycle time • Low power ICC = 45 mA • Fully asynchronous and simultaneous read and write operation • Empty, Full, Half Full, and Programmable Almost Empty/Almost Full status flags • TTL compatible • Retransmit function • Output Enable OE pin • Independent read and write enable pins • Center power and ground for reduced noise • Supports free running 50% duty cycle clock inputs • Width Expansion Capability • Depth Expansion Capability • Available in 64 pin 14 x 14 TQFP, 64 pin 10 x 10 TQFP, and 68-pin PLCC Functional Description The CY7C42X5 are high speed, low power, first-in first-out FIFO memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to IDT722X5. The CY7C42X5 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high speed data acquisition, multiprocessor interfaces, and communications buffering. These FIFOs have 18-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock WCLK and a write enable pin WEN . When WEN is asserted, data is written into the FIFO on the rising edge of the WCLK signal. While WEN is held active, data is continually written into the FIFO on each cycle. The output port is controlled in a similar manner by a free-running read clock RCLK and a read enable pin REN . In addition, the CY7C42X5 have an output enable pin OE . The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable. Retransmit and Synchronous Almost Full/Almost Empty flag features are available on these devices. Depth expansion is possible using the cascade input WXI, RXI , cascade output WXO, RXO , and First Load FL pins. The WXO and RXO pins are connected to the WXI and RXI pins of the next device, and the WXO and RXO pins of the last device should be connected to the WXI and RXI pins of the first device. The FL pin of the first device is tied to VSS and the FL pin of all the remaining devices should be tied to VCC. The CY7C42X5 provides five status pins. These pins are decoded to determine one of five states Empty, Almost Empty, Half Full, Almost Full, and Full see Table The Half Full flag shares the WXO pin. This flag is valid in the standalone and width-expansion configurations. In the depth expansion, this pin provides the expansion out WXO information that is used to signal the next FIFO when it will be activated. The Empty and Full flags are synchronous, i.e., they change state relative to either the read clock RCLK or the write clock WCLK . When entering or exiting the Empty states, the flag is updated exclusively by the RCLK. The flag denoting Full states is updated exclusively by WCLK. The synchronous flag architecture guarantees that the flags will remain valid from one clock cycle to the next. As mentioned previously, the Almost Empty/Almost Full flags become synchronous if the VCC/SMODE is tied to VSS. All configurations are fabricated using an advanced 0.65m N-Well CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Logic Block Diagram WCLK WRITE CONTROL FL/RT WXI WXO/HF RXI RXO WRITE POINTER RESET LOGIC EXPANSION LOGIC Pin Configuration Figure TQFP Top View CY7C4425/4205/4215 CY7C4225/4235/4245 INPUT REGISTER RAM ARRAY 64 x 18 256 x 18 512 x 18 1K x 18 2K x 18 4K x 18 FLAG PROGRAM REGISTER FLAG LOGIC READ POINTER FF EF PAF SMODE OUTPUT REGISTER READ CONTROL RCLK Figure PLCC Top View D15 D16 D17 GND RCLK REN LD OE RS VCC GND EF VCC Q17 Q16 GND Q15 VCC/SMODE RCLK CY7C4425 CY7C4205 CY7C4215 CY7C4225 CY7C4235 CY7C4245 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 Ordering Information 256 x 18 Synchronous FIFO Speed ns Ordering Code CY7C4205-10AXC CY7C4205-15AC CY7C4205-15AXC 512 x 18 Synchronous FIFO Speed ns Ordering Code CY7C4215-15AI CY7C4215-15AXI 1K x 18 Synchronous FIFO Speed ns Ordering Code CY7C4225-10AI CY7C4225-10AXI CY7C4225-15AXC CY7C4225-15ASC CY7C4225-15ASXC 2K x 18 Synchronous FIFO Speed ns Ordering Code CY7C4235-15AC CY7C4235-15AXC 4K x 18 Synchronous FIFO Speed ns Ordering Code CY7C4245-10AXC CY7C4245-10ASXC CY7C4245-10AI CY7C4245-10AXI CY7C4245-15AXC CY7C4245-15ASXC CY7C4245-15JXC CY7C4425/4205/4215 CY7C4225/4235/4245 Package Name 51-85046 51-85046 Package Type 64-Pin 14 x 14 Thin Quad Flatpack Pb-Free 64-Pin 14 x 14 Thin Quad Flatpack 64-Pin 14 x 14 Thin Quad Flatpack Pb-Free Package Name 51-85046 Package Type 64-Pin 14 x 14 Thin Quad Flatpack 64-Pin 14 x 14 Thin Quad Flatpack Pb-Free Package Name 51-85046 51-85046 51-85051 Package Type 64-Pin 14 x 14 Thin Quad Flatpack 64-Pin 14 x 14 Thin Quad Flatpack Pb-Free 64-Pin 14 x 14 Thin Quad Flatpack Pb-Free 64-Pin 10 x 10 Thin Quad Flatpack 64-Pin 10 x 10 Thin Quad Flatpack Pb-Free Package Name 51-85046 Package Type 64-Pin 14 x 14 Thin Quad Flatpack 64-Pin 14 x 14 Thin Quad Flatpack Pb-Free Package Name 51-85046 51-85051 51-85046 51-85046 51-85051 51-85005 Package Type 64-Pin 14 x 14 Thin Quad Flatpack Pb-Free 64-Pin 10 x 10 Thin Quad Flatpack Pb-Free 64-Pin 14 x 14 Thin Quad Flatpack 64-Pin 14 x 14 Thin Quad Flatpack Pb-Free 64-Pin 14 x 14 Thin Quad Flatpack Pb-Free 64-Pin 10 x 10 Thin Quad Flatpack Pb-Free 68-Pin Plastic Leaded Chip Carrier Pb-Free Operating Range Commercial Operating Range Industrial Operating Range Industrial Commercial

PDF Datasheet Preview

CY7C4425/4205/4215 CY7C4225/4235/4245
64/256/512/1K/2K/4K x 18 Synchronous FIFOs
• High speed, low power, first-in first-out FIFO memories
• 64 x 18 CY7C4425
• 256 x 18 CY7C4205
• 512 x 18 CY7C4215
• 1K x 18 CY7C4225
• 2K x 18 CY7C4235
• 4K x 18 CY7C4245
• High speed 100 MHz operation 10 ns read/write cycle time
• Low power ICC = 45 mA
• Fully asynchronous and simultaneous read and write operation
• Empty, Full, Half Full, and Programmable Almost Empty/Almost

Full status flags
• TTL compatible
• Retransmit function
• Output Enable OE pin
• Independent read and write enable pins
• Center power and ground for reduced noise
• Supports free running 50% duty cycle clock inputs
• Width Expansion Capability
• Depth Expansion Capability
• Available in 64 pin 14 x 14 TQFP, 64 pin 10 x 10 TQFP, and
68-pin PLCC

Functional Description

The CY7C42X5 are high speed, low power, first-in first-out FIFO memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to IDT722X5. The CY7C42X5 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high speed data acquisition, multiprocessor interfaces, and communications buffering.

These FIFOs have 18-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock WCLK and a write enable pin WEN . When WEN is asserted, data is written into the FIFO on the rising edge of the WCLK signal. While WEN is held active, data is continually written into the FIFO on each cycle. The output port is controlled in a similar manner by a free-running read clock RCLK and a read enable pin REN . In addition, the CY7C42X5 have an output enable pin OE . The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable.

Retransmit and Synchronous Almost Full/Almost Empty flag features are available on these devices.

Depth expansion is possible using the cascade input WXI, RXI , cascade output WXO, RXO , and First Load FL pins. The WXO and RXO pins are connected to the WXI and RXI pins of the next device, and the WXO and RXO pins of the last device should be connected to the WXI and RXI pins of the first device. The FL pin of the first device is tied to VSS and the FL pin of all the remaining devices should be tied to VCC.

The CY7C42X5 provides five status pins. These pins are decoded to determine one of five states Empty, Almost Empty, Half Full, Almost Full, and Full see Table The Half Full flag shares the WXO pin. This flag is valid in the standalone and width-expansion configurations. In the depth expansion, this pin provides the expansion out WXO information that is used to signal the next FIFO when it will be activated.

The Empty and Full flags are synchronous, i.e., they change state relative to either the read clock RCLK or the write clock WCLK . When entering or exiting the Empty states, the flag is updated exclusively by the RCLK. The flag denoting Full states is updated exclusively by WCLK. The synchronous flag architecture guarantees that the flags will remain valid from one clock cycle to the next. As mentioned previously, the Almost Empty/Almost Full flags become synchronous if the VCC/SMODE is tied to VSS. All configurations are fabricated using an advanced 0.65m N-Well CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings.
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

Logic Block Diagram

WCLK

WRITE CONTROL

FL/RT WXI

WXO/HF RXI RXO

WRITE POINTER

RESET LOGIC

EXPANSION LOGIC

Pin Configuration

Figure TQFP Top View

CY7C4425/4205/4215 CY7C4225/4235/4245

INPUT REGISTER

RAM ARRAY 64 x 18 256 x 18 512 x 18 1K x 18 2K x 18 4K x 18

FLAG PROGRAM REGISTER

FLAG LOGIC

READ POINTER

FF EF

PAF SMODE

OUTPUT REGISTER

READ CONTROL

RCLK

Figure PLCC Top View

D15 D16 D17 GND RCLK REN LD OE RS VCC GND EF VCC Q17 Q16 GND Q15

VCC/SMODE

RCLK

CY7C4425 CY7C4205 CY7C4215 CY7C4225 CY7C4235 CY7C4245
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
Ordering Information
256 x 18 Synchronous FIFO

Speed ns
Ordering Code

CY7C4205-10AXC

CY7C4205-15AC

CY7C4205-15AXC
512 x 18 Synchronous FIFO

Speed ns
Ordering Code

CY7C4215-15AI

CY7C4215-15AXI
1K x 18 Synchronous FIFO

Speed ns
Ordering Code

CY7C4225-10AI

CY7C4225-10AXI

CY7C4225-15AXC

CY7C4225-15ASC

CY7C4225-15ASXC
2K x 18 Synchronous FIFO

Speed ns
Ordering Code

CY7C4235-15AC

CY7C4235-15AXC
4K x 18 Synchronous FIFO

Speed ns
Ordering Code

CY7C4245-10AXC

CY7C4245-10ASXC

CY7C4245-10AI

CY7C4245-10AXI

CY7C4245-15AXC

CY7C4245-15ASXC

CY7C4245-15JXC

CY7C4425/4205/4215 CY7C4225/4235/4245

Package Name
51-85046
51-85046

Package Type
64-Pin 14 x 14 Thin Quad Flatpack Pb-Free
64-Pin 14 x 14 Thin Quad Flatpack
64-Pin 14 x 14 Thin Quad Flatpack Pb-Free

Package Name
51-85046

Package Type
64-Pin 14 x 14 Thin Quad Flatpack
64-Pin 14 x 14 Thin Quad Flatpack Pb-Free

Package Name
51-85046
51-85046 51-85051

Package Type
64-Pin 14 x 14 Thin Quad Flatpack 64-Pin 14 x 14 Thin Quad Flatpack Pb-Free 64-Pin 14 x 14 Thin Quad Flatpack Pb-Free 64-Pin 10 x 10 Thin Quad Flatpack 64-Pin 10 x 10 Thin Quad Flatpack Pb-Free

Package Name
51-85046

Package Type
64-Pin 14 x 14 Thin Quad Flatpack
64-Pin 14 x 14 Thin Quad Flatpack Pb-Free

Package Name
51-85046 51-85051 51-85046
51-85046 51-85051 51-85005

Package Type
64-Pin 14 x 14 Thin Quad Flatpack Pb-Free 64-Pin 10 x 10 Thin Quad Flatpack Pb-Free 64-Pin 14 x 14 Thin Quad Flatpack 64-Pin 14 x 14 Thin Quad Flatpack Pb-Free 64-Pin 14 x 14 Thin Quad Flatpack Pb-Free 64-Pin 10 x 10 Thin Quad Flatpack Pb-Free 68-Pin Plastic Leaded Chip Carrier Pb-Free

Operating Range

Commercial

Operating Range Industrial

Operating Range Industrial

Commercial

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Datasheet ID: CY7C4245-10AXCT 508109