CY7C4261V-10JC

CY7C4261V-10JC Datasheet

CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V

Part	Datasheet
CY7C4261V-10JC	CY7C4261V-10JC (pdf)

Related Parts	Information
CY7C4291V-15JC	CY7C4291V-15JC

PDF Datasheet Preview
CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V 16K/32K/64K/128K x 9 Low-Voltage Deep Sync FIFOs • 3.3V operation for low power consumption and easy integration into low-voltage systems • High-speed, low-power, first-in first-out FIFO memories • 16K x 9 CY7C4261V • 32K x 9 CY7C4271V • 64K x 9 CY7C4281V • 128K x 9 CY7C4291V • 0.35-micron CMOS for optimum speed/power • High-speed 100-MHz operation 10-ns read/write cycle times • Low power ICC = 25 mA ISB = 4 mA • Fully asynchronous and simultaneous read and write operation • Empty, Full, and programmable Almost Empty and Almost Full status flags • Output Enable OE pin • Independent read and write enable pins • Supports free-running 50% duty cycle clock inputs • Width- Expansion capability • 32-pin PLCC • Pin-compatible density upgrade to CY7C42X1V family • Pin-compatible 3.3V solutions for CY7C4261/71/81/91 Functional Description The CY7C4261/71/81/91V are high-speed, low-power FIFO memories with clocked read and write interfaces. All are nine bits wide. The CY7C4261/71/81/91V are pin-compatible to the CY7C42x1V Synchronous FIFO family. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. These FIFOs have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock WCLK and two write-enable pins WEN1, WEN2/LD . When WEN1 is LOW and WEN2/LD is HIGH, data is written into the FIFO on the rising edge of the WCLK signal. While WEN1 and WEN2/LD are held active, data is continually written into the FIFO on each WCLK cycle. The output port is controlled in a similar manner by a free-running read clock RCLK and two read enable pins REN1, REN2 . In addition, the CY7C4261/71/81/91V has an output enable pin OE . The read RCLK and write WCLK clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable. Depth expansion is possible using one enable input for system control, while the other enable is controlled by expansion logic to direct the flow of data. LogicBlock Diagram D 0−8 Pin Configuration INPUT REGISTER PLCC Top View WCLK WEN1WEN2/LD WRITE CONTROL WRITE POINTER Dual Port RAM Array 16K/32K 64K/128K FLAG PROGRAM REGISTER FLAG LOGIC READ POINTER EF PAE PAF FF RESET LOGIC THREE-STATE OUTPUT REGISTER READ CONTROL Q0− 8 RCLK REN1 REN2 D1 D0 PAF PAE REN1 RCLK REN2 4 3 2 1 32 31 30 CY7C4261V 28 27 8 CY7C4271V 26 9 CY7C4281V 25 10 CY7C4291V 24 14 15 16 17 18 19 20 WEN1 WCLK WEN2/LD VCC Q8 Q7 Q6 Q5 Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V Ordering Information 16Kx9 Low-voltage Deep Sync FIFO Speed ns Ordering Code CY7C4261V-10JC CY7C4261V-15JC CY7C4261V-15JI CY7C4261V-25JC 32Kx9 Low-voltage Deep Sync FIFO Speed ns Ordering Code CY7C4271V-10JC CY7C4271V-15JC CY7C4271V-15JI CY7C4271V-25JC 64kx9 Low-voltage Deep Sync FIFO Speed ns Ordering Code CY7C4281V-10JC CY7C4281V-15JC CY7C4281V-15JI CY7C4281V-25JC 128kx9 Low-voltage Deep Sync FIFO Speed ns Ordering Code CY7C4291V-10JC CY7C4291V-15JC CY7C4291V-15JI CY7C4291V-25JC Package Name J65 Package Type 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier Package Name J65 Package Type 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier Package Name J65 Package Type 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier Package Name J65 Package Type 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier Operating Range Commercial Industrial Commercial Operating Range Commercial Industrial Commercial Operating Range Commercial Industrial Commercial Operating Range Commercial Industrial Commercial Page 14 of 16 Package Diagram CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V 32-Lead Plastic Leaded Chip Carrier J65 51-85002-*B Deep Sync is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Page 15 of 16 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V Document History Page Document Title CY7C4261V/CY7C4271V/CY7C4281V/CY7C4291V 16K/32K/64K/128K/X9 Low-Voltage Deep Sync FIFO Document Number 38-06013 Description of Change 106474 09/15/01 SZV Changed Spec number from 38-00656 to 38-06013 127858 09/04/03 FSG Changed tSKEW2 to tSKEW1 in Switching Waveforms “Empty Flag Timing” diagram Fixed flag timing diagram in Switching Waveforms section Page 16 of 16

PDF Datasheet Preview

CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V
16K/32K/64K/128K x 9 Low-Voltage Deep Sync FIFOs
• 3.3V operation for low power consumption and easy integration into low-voltage systems
• High-speed, low-power, first-in first-out FIFO memories
• 16K x 9 CY7C4261V
• 32K x 9 CY7C4271V
• 64K x 9 CY7C4281V
• 128K x 9 CY7C4291V
• 0.35-micron CMOS for optimum speed/power
• High-speed 100-MHz operation 10-ns read/write cycle
times
• Low power

ICC = 25 mA ISB = 4 mA
• Fully asynchronous and simultaneous read and write operation
• Empty, Full, and programmable Almost Empty and Almost Full status flags
• Output Enable OE pin
• Independent read and write enable pins
• Supports free-running 50% duty cycle clock inputs
• Width- Expansion capability
• 32-pin PLCC
• Pin-compatible density upgrade to CY7C42X1V family
• Pin-compatible 3.3V solutions for CY7C4261/71/81/91

Functional Description

The CY7C4261/71/81/91V are high-speed, low-power FIFO memories with clocked read and write interfaces. All are nine bits wide. The CY7C4261/71/81/91V are pin-compatible to the CY7C42x1V Synchronous FIFO family. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering.

These FIFOs have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock WCLK and two write-enable pins WEN1, WEN2/LD .

When WEN1 is LOW and WEN2/LD is HIGH, data is written into the FIFO on the rising edge of the WCLK signal. While WEN1 and WEN2/LD are held active, data is continually written into the FIFO on each WCLK cycle. The output port is controlled in a similar manner by a free-running read clock RCLK and two read enable pins REN1, REN2 . In addition, the CY7C4261/71/81/91V has an output enable pin OE . The read RCLK and write WCLK clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable. Depth expansion is possible using one enable input for system control, while the other enable is controlled by expansion logic to direct the flow of data.

LogicBlock Diagram D 0−8

Pin Configuration

INPUT REGISTER

PLCC Top View

WCLK WEN1WEN2/LD

WRITE CONTROL

WRITE POINTER

Dual Port RAM Array
16K/32K 64K/128K

FLAG PROGRAM REGISTER

FLAG LOGIC READ POINTER

EF PAE PAF FF

RESET LOGIC

THREE-STATE OUTPUT REGISTER

READ CONTROL

Q0− 8

RCLK REN1 REN2

D1 D0 PAF PAE

REN1 RCLK REN2
4 3 2 1 32 31 30

CY7C4261V
28 27
8 CY7C4271V 26
9 CY7C4281V 25
10 CY7C4291V 24
14 15 16 17 18 19 20

WEN1

WCLK WEN2/LD VCC Q8 Q7 Q6 Q5

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose, CA 95134
• 408-943-2600

CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V
Ordering Information
16Kx9 Low-voltage Deep Sync FIFO

Speed ns
Ordering Code

CY7C4261V-10JC

CY7C4261V-15JC

CY7C4261V-15JI

CY7C4261V-25JC
32Kx9 Low-voltage Deep Sync FIFO

Speed ns
Ordering Code

CY7C4271V-10JC

CY7C4271V-15JC

CY7C4271V-15JI

CY7C4271V-25JC
64kx9 Low-voltage Deep Sync FIFO

Speed ns
Ordering Code

CY7C4281V-10JC

CY7C4281V-15JC

CY7C4281V-15JI

CY7C4281V-25JC
128kx9 Low-voltage Deep Sync FIFO

Speed ns
Ordering Code CY7C4291V-10JC

CY7C4291V-15JC

CY7C4291V-15JI

CY7C4291V-25JC

Package Name J65

Package Type 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier

Package Name J65

Package Type 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier

Package Name J65

Package Type 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier

Package Name J65

Package Type 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier

Operating Range

Commercial Industrial Commercial

Operating Range

Commercial Industrial Commercial

Operating Range

Commercial Industrial Commercial

Operating Range

Commercial Industrial Commercial

Page 14 of 16

Package Diagram

CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V
32-Lead Plastic Leaded Chip Carrier J65
51-85002-*B

Deep Sync is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.

Page 15 of 16

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V

Document History Page

Document Title CY7C4261V/CY7C4271V/CY7C4281V/CY7C4291V 16K/32K/64K/128K/X9 Low-Voltage Deep Sync FIFO Document Number 38-06013

Description of Change
106474 09/15/01

SZV Changed Spec number from 38-00656 to 38-06013
127858 09/04/03

FSG Changed tSKEW2 to tSKEW1 in Switching Waveforms “Empty Flag Timing” diagram

Fixed flag timing diagram in Switching Waveforms section

Page 16 of 16

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C4261V-10JC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C4261V-10JC 508104