CY7C4261-15JXCT

CY7C4261-15JXCT Datasheet


CY7C4261, CY7C4271

Part Datasheet
CY7C4261-15JXCT CY7C4261-15JXCT CY7C4261-15JXCT (pdf)
Related Parts Information
CY7C4271-10JC CY7C4271-10JC CY7C4271-10JC
CY7C4261-15JXC CY7C4261-15JXC CY7C4261-15JXC
CY7C4261-15JC CY7C4261-15JC CY7C4261-15JC
CY7C4271-15AC CY7C4271-15AC CY7C4271-15AC
PDF Datasheet Preview
CY7C4261, CY7C4271
16K/32K x 9 Deep Sync FIFOs
• High speed, low power, first-in first-out FIFO memories
• 16K x 9 CY7C4261
• 32K x 9 CY7C4271
• micron CMOS for optimum speed and power
• High speed 100 MHz operation 10 ns read/write cycle times
• Low power ICC = 35 mA
• Fully asynchronous and simultaneous read and write operation
• Empty, Full, Half Full, and programmable Almost Empty and

Almost Full status flags
• TTL compatible
• Output Enable OE pins
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free running 50% duty cycle clock inputs
• Width Expansion Capability
• Military temp SMD Offering CY7C4271-15LMB
• 32-pin PLCC/LCC and 32-pin TQFP
• Pin compatible density upgrade to CY7C42X1 family
• Pin compatible density upgrade to IDT72201/11/21/31/41/51
• Pb-Free Packages Available

Functional Description

The CY7C4261/71 are high speed, low power FIFO memories with clocked read and write interfaces. All are nine bits wide. The CY7C4261/71 are pin compatible to the CY7C42X1 Synchronous FIFO family. The CY7C4261/71 can be cascaded to increase FIFO width. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high speed data acquisition, multiprocessor interfaces, and communications buffering.

These FIFOs have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock WCLK and two write-enable pins WEN1, WEN2/LD .

When WEN1 is LOW and WEN2/LD is HIGH, data is written into the FIFO on the rising edge of the WCLK signal. While WEN1, WEN2/LD is held active, data is continually written into the FIFO on each WCLK cycle. The output port is controlled in a similar manner by a free running read clock RCLK and two read enable pins REN1, REN2 . In addition, the CY7C4261/71 has an output enable pin OE . The read RCLK and write WCLK clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable. Depth expansion is possible using one enable input for system control, while the other enable is controlled by expansion logic to direct the flow of data.

Selection Guide

Parameter

Maximum Frequency

Maximum Access Time

Minimum Cycle Time

Minimum Data or Enable Setup

Minimum Data or Enable Hold

Maximum Flag Delay

Active Power Supply Commercial

Current ICC1

Industrial/

Military
7C4261/71-10 100 8 10 3 8 35 40
7C4261/71-15 10 15 4 1 10 35 40
7C4261/71-25 40 15 25 6 1 15 35 40
7C4261/71-35 20 35 7 2 20 35 40

Unit MHz ns
ns mA

Density Package

Parameter

CY7C4261 16K x 9 32-pin PLCC, TQFP

CY7C4271 32K x 9 32-pin LCC, PLCC, TQFP
• San Jose, CA 95134-1709
• 408-943-2600
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CY7C4261, CY7C4261

Logic Block Diagram

INPUT REGISTER

WCLK WEN1 WEN2/LD

WRITE CONTROL

WRITE POINTER

RAM ARRAY 16K x 9 32K x 9

FLAG PROGRAM REGISTER

FLAG LOGIC
Ordering Information
16Kx9 Deep Sync FIFO Speed ns Ordering Code
CY7C4261-10AC CY7C4261-10JC 10 CY7C4261-10AI CY7C4261-10JI CY7C4261-10JXI CY7C4261-15AC CY7C4261-15JC 15 CY7C4261-15JXC CY7C4261-15AI CY7C4261-15JI CY7C4261-25AC CY7C4261-25JC 25 CY7C4261-25AI CY7C4261-25JI CY7C4261-35AC CY7C4261-35JC 35 CY7C4261-35AI CY7C4261-35JI 32Kx9 Deep Sync FIFO Speed ns Ordering Code 10 CY7C4271-10AC CY7C4271-10JC CY7C4271-10AI CY7C4271-10JI 15 CY7C4271-15AC CY7C4271-15AXC CY7C4271-15JC CY7C4271-15AI CY7C4271-15JI CY7C4271-15LMB 5962-9736101QYA 25 CY7C4271-25AC CY7C4271-25JC CY7C4271-25AI CY7C4271-25JI 35 CY7C4271-35AC CY7C4271-35JC CY7C4271-35AI CY7C4271-35JI

Package Diagram

Package Type
51-85063
32-Pin Thin Quad Flat Pack 7 x 7 x mm
51-85002
32-Pin Plastic Leaded Chip Carrier
51-85063
32-Pin Thin Quad Flat Pack 7 x 7 x mm
51-85002
32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier Pb-Free
51-85063
32-Pin Thin Quad Flat Pack 7 x 7 x mm
51-85002
32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier Pb-Free
51-85063
32-Pin Thin Quad Flat Pack 7 x 7 x mm
51-85002
32-Pin Plastic Leaded Chip Carrier
51-85063
32-Pin Thin Quad Flat Pack 7 x 7 x mm
51-85002
32-Pin Plastic Leaded Chip Carrier
51-85063
32-Pin Thin Quad Flat Pack 7 x 7 x mm
51-85002
32-Pin Plastic Leaded Chip Carrier
51-85063
32-Pin Thin Quad Flat Pack 7 x 7 x mm
51-85002
32-Pin Plastic Leaded Chip Carrier
51-85063
32-Pin Thin Quad Flat Pack 7 x 7 x mm
51-85002
32-Pin Plastic Leaded Chip Carrier

Operating Range Commercial Industrial

Commercial Industrial

Commercial Industrial

Commercial Industrial

Package Diagram

Package Type
Added CY7C4261-10JXI, CY7C4261-15JXC to ordering information
2556036 VKN/AESA 08/22/2008 Updated ordering information and data sheet template. Removed Pb-Free

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Sales, Solutions, and Legal Information

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More datasheets: FR1D-13 | FR1A-13 | FR1K-13 | FR1M-13 | FR1B-13 | FR1G-13 | HCHDM32E | 67-21/R6C-AP2R1B/2A0 | CY7C4271-10JC | CY7C4261-15JXC


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Datasheet ID: CY7C4261-15JXCT 508103