CY7C4275V-10ASC

CY7C4275V-10ASC Datasheet


CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V

Part Datasheet
CY7C4275V-10ASC CY7C4275V-10ASC CY7C4275V-10ASC (pdf)
Related Parts Information
CY7C4275V-15ASC CY7C4275V-15ASC CY7C4275V-15ASC
PDF Datasheet Preview
CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V
32K/64Kx18 Low Voltage Deep Sync FIFOs
• 3.3V operation for low power consumption and easy integration into low voltage systems
• High speed, low power, first-in first-out FIFO memories
• 8K x 18 CY7C4255V
• 16K x 18 CY7C4265V
• 32K x 18 CY7C4275V
• 64K x 18 CY7C4285V
• micron CMOS for optimum speed and power
• High speed 100 MHz operation 10 ns read/write cycle times
• Low power ICC = 30 mA ISB = 4 mA
• Fully asynchronous and simultaneous read and write operation
• Empty, Full, Half Full, and programmable Almost Empty and Almost Full status flags
• Retransmit function
• Output Enable OE pin
• Independent read and write enable pins
• Supports free running 50% duty cycle clock inputs
• Width Expansion Capability
• Depth Expansion Capability
• 64-pin 10x10 STQFP
• Pin compatible density upgrade to CY7C42X5V-ASC families
• Pin compatible 3.3V solutions for CY7C4255/65/75/85

Selection Guide

Parameter Maximum Frequency MHz Maximum Access Time ns Minimum Cycle Time ns Minimum Data or Enable Setup ns Minimum Data or Enable Hold ns Maximum Flag Delay ns Active Power Supply Commercial Current ICC1 mA Industrial
7C4255/65/75/85V-10 100 8 10 0 8 30

Functional Description

The CY7C4255/65/75/85V are high speed, low power, first-in first-out FIFO memories with clocked read and write interfaces. All are 18 bits wide and are pin and functionally compatible to the CY7C42X5V Synchronous FIFO family. The CY7C4255/65/75/85V can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high speed data acquisition, multiprocessor interfaces, and communications buffering.

These FIFOs have 18-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock WCLK and a write enable pin WEN .

When WEN is asserted, data is written into the FIFO on the rising edge of the WCLK signal. While WEN is held active, data is continually written into the FIFO on each cycle. The output port is controlled in a similar manner by a free-running read clock RCLK and a read enable pin REN . In addition, the CY7C4255/65/75/85V have an output enable pin OE . The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read or write applications. Clock frequencies up to 67 MHz are achievable.

Retransmit and Synchronous Almost Full/Almost Empty flag features are available on these devices.

Depth expansion is possible using the cascade input WXI, RXI , cascade output WXO, RXO , and First Load FL pins. The WXO and RXO pins are connected to the WXI and RXI pins of the next device, and the WXO and RXO pins of the last device must be connected to the WXI and RXI pins of the first device. The FL pin of the first device is tied to VSS and the FL pin of all the remaining devices must be tied to VCC
7C4255/65/75/85V-15 10 15 4 0 10 30 35
7C4255/65/75/85V-25 40 15 25 6 1 15 30

Parameter Density Package

CY7C4255V 8K x 18 64-pin 10x10 TQFP

CY7C4265V 16K x 18 64-pin 10x10 TQFP

CY7C4275V 32K x 18 64-pin 10x10 TQFP

CY7C4285V 64K x 18 64-pin 10x10 TQFP
• San Jose, CA 95134-1709
• 408-943-2600
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CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V
Ordering Information
8Kx18 Low-Voltage Deep Sync FIFO
Speed ns Ordering Code Package Diagram

Package Type

Operating Range
51-85051
64-Pin Thin Quad Flat Pack 10 x 10 x mm Commercial
64-Pin Thin Quad Flat Pack 10 x 10 x mm Pb-Free
51-85051
64-Pin Thin Quad Flat Pack 10 x 10 x mm Commercial
64-Pin Thin Quad Flat Pack 10 x 10 x mm Pb-Free
51-85051
64-Pin Thin Quad Flat Pack 10 x 10 x mm Pb-Free Industrial
51-85051
64-Pin Thin Quad Flat Pack 10 x 10 x mm

Commercial
16Kx18 Low-Voltage Deep Sync FIFO
Speed ns Ordering Code Package Diagram

Package Type

Operating Range
51-85051
64-Pin Thin Quad Flat Pack 10 x 10 x mm

Commercial
51-85051
64-Pin Thin Quad Flat Pack 10 x 10 x mm

Commercial
51-85051
64-Pin Thin Quad Flat Pack 10 x 10 x mm

Commercial
32Kx18 Low-Voltage Deep Sync FIFO
Speed ns Ordering Code Package Diagram

Package Type

Operating Range
51-85051
64-Pin Thin Quad Flat Pack 10 x 10 x mm

Commercial
51-85051
64-Pin Thin Quad Flat Pack 10 x 10 x mm Commercial
64-Pin Thin Quad Flat Pack 10 x 10 x mm Pb-Free
64Kx18 Low-Voltage Deep Sync FIFO
Speed ns Ordering Code Package Diagram

Package Type

Operating Range
51-85051
64-Pin Thin Quad Flat Pack 10 x 10 x mm

Commercial
64-Pin Thin Quad Flat Pack 10 x 10 x mm Pb-Free
51-85051
64-Pin Thin Quad Flat Pack 10 x 10 x mm Pb-Free Commercial
51-85051
64-Pin Thin Quad Flat Pack 10 x 10 x mm 64-Pin Thin Quad Flat Pack 10 x 10 x mm Pb-Free

Industrial
51-85051
64-Pin Thin Quad Flat Pack 10 x 10 x mm

Commercial

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CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V

Package Diagrams

Figure 64-Pin Thin Plastic Quad Flat Pack 10 x 10 x mm
51-85051 *A

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CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V

Document History Page

Document Title CY7C4255V/CY7C4265V/CY7C4275V/CY7C4285V 32K/64Kx18 Low Voltage Deep Sync FIFOs Document Number 38-06012

Orig. of Submission

Change

Description of Change
106473
09/10/01 Change from Spec number 38-00654 to 38-06012
122264
12/26/02 Power up requirements added to Maximum Ratings Information
2556036 VKN/AESA 08/22/2008 Updated ordering information and data sheet template.

Sales, Solutions, and Legal Information

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Datasheet ID: CY7C4275V-10ASC 508101