CY7C4225V-15ASC
CY7C4225V-15ASC Datasheet
CY7C4425V /4205V/4215V CY7C4225V /4235V/4245V64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
| Part | Datasheet |
|---|---|
CY7C4225V-15ASC |
CY7C4225V-15ASC (pdf) |
| Related Parts | Information |
|---|---|
CY7C4205V-15ASXCT |
CY7C4205V-15ASXCT |
CY7C4235V-15ASC |
CY7C4235V-15ASC |
CY7C4245V-25ASXC |
CY7C4245V-25ASXC |
CY7C4245V-25ASXCT |
CY7C4245V-25ASXCT |
CY7C4225V-15ASXCT |
CY7C4225V-15ASXCT |
CY7C4205V-15ASXC |
CY7C4205V-15ASXC |
CY7C4235V-15ASXC |
CY7C4235V-15ASXC |
CY7C4245V-15ASXC |
CY7C4245V-15ASXC |
CY7C4225V-15ASXC |
CY7C4225V-15ASXC |
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| CY7C4425V /4205V/4215V CY7C4225V /4235V/4245V64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs • 3.3V operation for low power consumption and easy integration into low-voltage systems • High-speed, low-power, first-in first-out FIFO memories • 64 x 18 CY7C4425V • 256 x 18 CY7C4205V • 512 x 18 CY7C4215V • 1K x 18 CY7C4225V • 2K x 18 CY7C4235V • 4K x 18 CY7C4245V • CMOS • High-speed 67-MHz operation 15-ns read/write cycle times • Low power ICC = 30 mA • 5V tolerant inputs VIH MAX = 5V • Fully asynchronous and simultaneous read and write operation • Empty, Full, Half Full, and programmable Almost Empty and Almost Full status flags • TTL-compatible • Retransmit function • Output Enable OE pin • Independent read and write enable pins • Supports free-running 50% duty cycle clock inputs • Width-Expansion Capability • Depth-Expansion Capability • 64-pin 14 x 14 TQFP and 64-pin 10 x 10 STQFP • Pb-Free packages available Functional Description The CY7C42X5V are high-speed, low-power, first-in first-out FIFO memories with clocked read and write interfaces. All are 18 bits wide. The CY7C42X5V can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. These FIFOs have 18-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a Free-Running Clock WCLK and a Write Enable pin WEN . When WEN is asserted, data is written into the FIFO on the rising edge of the WCLK signal. While WEN is held active, data is continually written into the FIFO on each cycle. The output port is controlled in a similar manner by a Free-Running Read Clock RCLK and a Read Enable pin REN . In addition, the CY7C42X5V have an Output Enable pin OE . The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 66 MHz are achievable. Retransmit and Synchronous Almost Full/Almost Empty flag features are available on these devices. Depth expansion is possible using the Cascade Input WXI, RXI , Cascade Output WXO, RXO , and First Load FL pins. The WXO and RXO pins are connected to the WXI and RXI pins of the next device, and the WXO and RXO pins of the last device should be connected to the WXI and RXI pins of the first device. The FL pin of the first device is tied to VSS and the FL pin of all the remaining devices should be tied to VCC. The CY7C42X5V provides five status pins. These pins are decoded to determine one of five states Empty, Almost Empty, Half Full, Almost Full, and Full see Table The Half Full flag shares the WXO pin. This flag is valid in the stand-alone and width-expansion configurations. In the depth expansion, this pin provides the expansion out WXO information that is used to signal the next FIFO when it will be activated. The Empty and Full flags are synchronous, i.e., they change state relative to either the Read Clock RCLK or the write clock WCLK . When entering or exiting the Empty states, the flag is updated exclusively by the RCLK. The flag denoting Full states is updated exclusively by WCLK. The synchronous flag architecture guarantees that the flags will remain valid from one clock cycle to the next. As mentioned previously, the Almost Empty/Almost Full flags become synchronous if the VCC/SMODE is tied to VSS. All configurations are fabricated using an advanced P-Well CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Logic Block Diagram WCLK WRITE CONTROL FL/RT WXI WXO/HF RXI WRITE POINTER RESET LOGIC EXPANSION LOGIC Pin Configuration INPUT REGISTER RAM ARRAY 64 x 18 256 x 18 512 x 18 1K x 18 2K x 18 4K x 18 CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V FLAG PROGRAM REGISTER FLAG LOGIC READ POINTER FF EF PAE PAF SMODE OUTPUT REGISTER READ CONTROL RCLK STQFP/TQFP Top View Ordering Information 64 x 18 Low-Voltage Synchronous FIFO Speed ns Ordering Code CY7C4425V-15ASC CY7C4425V-25ASC CY7C4425V-35ASC 256 x 18 Low-Voltage Synchronous FIFO Speed ns Ordering Code CY7C4205V-15ASC CY7C4205V-15AC CY7C4205V-15ASXC CY7C4205V-25ASC CY7C4205V-35ASC 512 x 18 Low-Voltage Synchronous FIFO Speed ns Ordering Code CY7C4215V-15ASC CY7C4215V-15ASXC CY7C4215V-25ASC CY7C4215V-35ASC 1K x 18 Low-Voltage Synchronous FIFO Speed ns Ordering Code CY7C4225V-15ASC CY7C4225V-15ASXC CY7C4225V-15AC CY7C4225V-25ASC CY7C4225V-35ASC 2K x 18 Low-Voltage Synchronous FIFO Speed ns Ordering Code CY7C4235V-15ASC CY7C4235V-15ASXC CY7C4235V-25ASC CY7C4235V-35ASC 4K x 18 Low-Voltage Synchronous FIFO Speed ns Ordering Code CY7C4245V-15ASC CY7C4245V-15ASXC CY7C4245V-25ASC CY7C4245V-25ASXC CY7C4245V-35ASC Package Name A64 Package Name A64 A65 A64 Package Name A64 Package Name A64 A65 A64 Package Name A64 Package Name A64 Package Type 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack Package Type 64-Lead 10x10 Thin Quad Flatpack 64-Lead 14x14 Thin Quad Flatpack 64-Lead Pb-Free 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack Package Type 64-Lead 10x10 Thin Quad Flatpack 64-Lead Pb-Free 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack Package Type 64-Lead 10x10 Thin Quad Flatpack 64-Lead Pb-Free 10x10 Thin Quad Flatpack 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack Package Type 64-Lead 10x10 Thin Quad Flatpack 64-Lead Pb-Free 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack Package Type 64-Lead 10x10 Thin Quad Flatpack 64-Lead Pb-Free 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 64-Lead Pb-Free 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack Operating Range Commercial Operating Range Commercial Commercial Operating Range Commercial Commercial Operating Range Commercial Commercial Operating Range Commercial Commercial Operating Range Commercial Commercial Added Pb-Free parts to ordering information: CY7C4205V-15ASXC, CY7C4215V-15ASXC, CY7C4225V-15ASXC, CY7C4235V-15ASXC, CY7C4245V-15ASXC, CY7C4245V-25ASXC Page 20 of 20 [+] Feedback |
| More datasheets: DM74AS21N | 74LCX27SJX | 74LCX27MTC | 74LCX27M | 74LCX27SJ | 74LCX27MTCX | 74LCX27MX | CY7C4205V-15ASXCT | CY7C4235V-15ASC | CY7C4245V-25ASXC |
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